1325234Smw/*- 2368013Smw * SPDX-License-Identifier: BSD-3-Clause 3325234Smw * 4361534Smw * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5325234Smw * All rights reserved. 6325234Smw * 7325234Smw * Redistribution and use in source and binary forms, with or without 8325234Smw * modification, are permitted provided that the following conditions 9325234Smw * are met: 10325234Smw * 11325234Smw * * Redistributions of source code must retain the above copyright 12325234Smw * notice, this list of conditions and the following disclaimer. 13325234Smw * * Redistributions in binary form must reproduce the above copyright 14325234Smw * notice, this list of conditions and the following disclaimer in 15325234Smw * the documentation and/or other materials provided with the 16325234Smw * distribution. 17325234Smw * * Neither the name of copyright holder nor the names of its 18325234Smw * contributors may be used to endorse or promote products derived 19325234Smw * from this software without specific prior written permission. 20325234Smw * 21325234Smw * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22325234Smw * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23325234Smw * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24325234Smw * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25325234Smw * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26325234Smw * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27325234Smw * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28325234Smw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29325234Smw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30325234Smw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31325234Smw * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32325234Smw */ 33325234Smw#ifndef _ENA_ADMIN_H_ 34325234Smw#define _ENA_ADMIN_H_ 35325234Smw 36361467Smw#define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32 37361467Smw#define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32 38361467Smw 39368013Smw#define ENA_ADMIN_RSS_KEY_PARTS 10 40368013Smw 41325234Smwenum ena_admin_aq_opcode { 42361467Smw ENA_ADMIN_CREATE_SQ = 1, 43361467Smw ENA_ADMIN_DESTROY_SQ = 2, 44361467Smw ENA_ADMIN_CREATE_CQ = 3, 45361467Smw ENA_ADMIN_DESTROY_CQ = 4, 46361467Smw ENA_ADMIN_GET_FEATURE = 8, 47361467Smw ENA_ADMIN_SET_FEATURE = 9, 48361467Smw ENA_ADMIN_GET_STATS = 11, 49325234Smw}; 50325234Smw 51325234Smwenum ena_admin_aq_completion_status { 52361467Smw ENA_ADMIN_SUCCESS = 0, 53361467Smw ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 54361467Smw ENA_ADMIN_BAD_OPCODE = 2, 55361467Smw ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 56361467Smw ENA_ADMIN_MALFORMED_REQUEST = 4, 57325234Smw /* Additional status is provided in ACQ entry extended_status */ 58361467Smw ENA_ADMIN_ILLEGAL_PARAMETER = 5, 59361467Smw ENA_ADMIN_UNKNOWN_ERROR = 6, 60361467Smw ENA_ADMIN_RESOURCE_BUSY = 7, 61325234Smw}; 62325234Smw 63368013Smw/* subcommands for the set/get feature admin commands */ 64325234Smwenum ena_admin_aq_feature_id { 65361467Smw ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 66361467Smw ENA_ADMIN_MAX_QUEUES_NUM = 2, 67361467Smw ENA_ADMIN_HW_HINTS = 3, 68361467Smw ENA_ADMIN_LLQ = 4, 69361467Smw ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5, 70361467Smw ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6, 71361467Smw ENA_ADMIN_MAX_QUEUES_EXT = 7, 72361467Smw ENA_ADMIN_RSS_HASH_FUNCTION = 10, 73361467Smw ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 74368013Smw ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12, 75361467Smw ENA_ADMIN_MTU = 14, 76361467Smw ENA_ADMIN_RSS_HASH_INPUT = 18, 77361467Smw ENA_ADMIN_INTERRUPT_MODERATION = 20, 78361467Smw ENA_ADMIN_AENQ_CONFIG = 26, 79361467Smw ENA_ADMIN_LINK_CONFIG = 27, 80361467Smw ENA_ADMIN_HOST_ATTR_CONFIG = 28, 81361467Smw ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 82325234Smw}; 83325234Smw 84325234Smwenum ena_admin_placement_policy_type { 85325234Smw /* descriptors and headers are in host memory */ 86361467Smw ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 87325234Smw /* descriptors and headers are in device memory (a.k.a Low Latency 88325234Smw * Queue) 89325234Smw */ 90361467Smw ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 91325234Smw}; 92325234Smw 93325234Smwenum ena_admin_link_types { 94361467Smw ENA_ADMIN_LINK_SPEED_1G = 0x1, 95361467Smw ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 96361467Smw ENA_ADMIN_LINK_SPEED_5G = 0x4, 97361467Smw ENA_ADMIN_LINK_SPEED_10G = 0x8, 98361467Smw ENA_ADMIN_LINK_SPEED_25G = 0x10, 99361467Smw ENA_ADMIN_LINK_SPEED_40G = 0x20, 100361467Smw ENA_ADMIN_LINK_SPEED_50G = 0x40, 101361467Smw ENA_ADMIN_LINK_SPEED_100G = 0x80, 102361467Smw ENA_ADMIN_LINK_SPEED_200G = 0x100, 103361467Smw ENA_ADMIN_LINK_SPEED_400G = 0x200, 104325234Smw}; 105325234Smw 106325234Smwenum ena_admin_completion_policy_type { 107325234Smw /* completion queue entry for each sq descriptor */ 108361467Smw ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 109325234Smw /* completion queue entry upon request in sq descriptor */ 110361467Smw ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 111325234Smw /* current queue head pointer is updated in OS memory upon sq 112325234Smw * descriptor request 113325234Smw */ 114361467Smw ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 115325234Smw /* current queue head pointer is updated in OS memory for each sq 116325234Smw * descriptor 117325234Smw */ 118361467Smw ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 119325234Smw}; 120325234Smw 121325234Smw/* basic stats return ena_admin_basic_stats while extanded stats return a 122325234Smw * buffer (string format) with additional statistics per queue and per 123325234Smw * device id 124325234Smw */ 125325234Smwenum ena_admin_get_stats_type { 126361467Smw ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 127361467Smw ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 128368013Smw /* extra HW stats for specific network interface */ 129368013Smw ENA_ADMIN_GET_STATS_TYPE_ENI = 2, 130325234Smw}; 131325234Smw 132325234Smwenum ena_admin_get_stats_scope { 133361467Smw ENA_ADMIN_SPECIFIC_QUEUE = 0, 134361467Smw ENA_ADMIN_ETH_TRAFFIC = 1, 135325234Smw}; 136325234Smw 137325234Smwstruct ena_admin_aq_common_desc { 138325234Smw /* 11:0 : command_id 139325234Smw * 15:12 : reserved12 140325234Smw */ 141325234Smw uint16_t command_id; 142325234Smw 143325234Smw /* as appears in ena_admin_aq_opcode */ 144325234Smw uint8_t opcode; 145325234Smw 146325234Smw /* 0 : phase 147325234Smw * 1 : ctrl_data - control buffer address valid 148325234Smw * 2 : ctrl_data_indirect - control buffer address 149325234Smw * points to list of pages with addresses of control 150325234Smw * buffers 151325234Smw * 7:3 : reserved3 152325234Smw */ 153325234Smw uint8_t flags; 154325234Smw}; 155325234Smw 156325234Smw/* used in ena_admin_aq_entry. Can point directly to control data, or to a 157325234Smw * page list chunk. Used also at the end of indirect mode page list chunks, 158325234Smw * for chaining. 159325234Smw */ 160325234Smwstruct ena_admin_ctrl_buff_info { 161325234Smw uint32_t length; 162325234Smw 163325234Smw struct ena_common_mem_addr address; 164325234Smw}; 165325234Smw 166325234Smwstruct ena_admin_sq { 167325234Smw uint16_t sq_idx; 168325234Smw 169325234Smw /* 4:0 : reserved 170325234Smw * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 171325234Smw */ 172325234Smw uint8_t sq_identity; 173325234Smw 174325234Smw uint8_t reserved1; 175325234Smw}; 176325234Smw 177325234Smwstruct ena_admin_aq_entry { 178325234Smw struct ena_admin_aq_common_desc aq_common_descriptor; 179325234Smw 180325234Smw union { 181325234Smw uint32_t inline_data_w1[3]; 182325234Smw 183325234Smw struct ena_admin_ctrl_buff_info control_buffer; 184325234Smw } u; 185325234Smw 186325234Smw uint32_t inline_data_w4[12]; 187325234Smw}; 188325234Smw 189325234Smwstruct ena_admin_acq_common_desc { 190325234Smw /* command identifier to associate it with the aq descriptor 191325234Smw * 11:0 : command_id 192325234Smw * 15:12 : reserved12 193325234Smw */ 194325234Smw uint16_t command; 195325234Smw 196325234Smw uint8_t status; 197325234Smw 198325234Smw /* 0 : phase 199325234Smw * 7:1 : reserved1 200325234Smw */ 201325234Smw uint8_t flags; 202325234Smw 203325234Smw uint16_t extended_status; 204325234Smw 205361467Smw /* indicates to the driver which AQ entry has been consumed by the 206368013Smw * device and could be reused 207361467Smw */ 208325234Smw uint16_t sq_head_indx; 209325234Smw}; 210325234Smw 211325234Smwstruct ena_admin_acq_entry { 212325234Smw struct ena_admin_acq_common_desc acq_common_descriptor; 213325234Smw 214325234Smw uint32_t response_specific_data[14]; 215325234Smw}; 216325234Smw 217325234Smwstruct ena_admin_aq_create_sq_cmd { 218325234Smw struct ena_admin_aq_common_desc aq_common_descriptor; 219325234Smw 220325234Smw /* 4:0 : reserved0_w1 221325234Smw * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 222325234Smw */ 223325234Smw uint8_t sq_identity; 224325234Smw 225325234Smw uint8_t reserved8_w1; 226325234Smw 227325234Smw /* 3:0 : placement_policy - Describing where the SQ 228325234Smw * descriptor ring and the SQ packet headers reside: 229325234Smw * 0x1 - descriptors and headers are in OS memory, 230325234Smw * 0x3 - descriptors and headers in device memory 231325234Smw * (a.k.a Low Latency Queue) 232325234Smw * 6:4 : completion_policy - Describing what policy 233325234Smw * to use for generation completion entry (cqe) in 234325234Smw * the CQ associated with this SQ: 0x0 - cqe for each 235325234Smw * sq descriptor, 0x1 - cqe upon request in sq 236325234Smw * descriptor, 0x2 - current queue head pointer is 237325234Smw * updated in OS memory upon sq descriptor request 238325234Smw * 0x3 - current queue head pointer is updated in OS 239325234Smw * memory for each sq descriptor 240325234Smw * 7 : reserved15_w1 241325234Smw */ 242325234Smw uint8_t sq_caps_2; 243325234Smw 244325234Smw /* 0 : is_physically_contiguous - Described if the 245325234Smw * queue ring memory is allocated in physical 246325234Smw * contiguous pages or split. 247325234Smw * 7:1 : reserved17_w1 248325234Smw */ 249325234Smw uint8_t sq_caps_3; 250325234Smw 251368013Smw /* associated completion queue id. This CQ must be created prior to SQ 252368013Smw * creation 253325234Smw */ 254325234Smw uint16_t cq_idx; 255325234Smw 256325234Smw /* submission queue depth in entries */ 257325234Smw uint16_t sq_depth; 258325234Smw 259325234Smw /* SQ physical base address in OS memory. This field should not be 260325234Smw * used for Low Latency queues. Has to be page aligned. 261325234Smw */ 262325234Smw struct ena_common_mem_addr sq_ba; 263325234Smw 264325234Smw /* specifies queue head writeback location in OS memory. Valid if 265325234Smw * completion_policy is set to completion_policy_head_on_demand or 266325234Smw * completion_policy_head. Has to be cache aligned 267325234Smw */ 268325234Smw struct ena_common_mem_addr sq_head_writeback; 269325234Smw 270325234Smw uint32_t reserved0_w7; 271325234Smw 272325234Smw uint32_t reserved0_w8; 273325234Smw}; 274325234Smw 275325234Smwenum ena_admin_sq_direction { 276361467Smw ENA_ADMIN_SQ_DIRECTION_TX = 1, 277361467Smw ENA_ADMIN_SQ_DIRECTION_RX = 2, 278325234Smw}; 279325234Smw 280325234Smwstruct ena_admin_acq_create_sq_resp_desc { 281325234Smw struct ena_admin_acq_common_desc acq_common_desc; 282325234Smw 283325234Smw uint16_t sq_idx; 284325234Smw 285325234Smw uint16_t reserved; 286325234Smw 287325234Smw /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 288325234Smw uint32_t sq_doorbell_offset; 289325234Smw 290325234Smw /* low latency queue ring base address as an offset to PCIe MMIO 291325234Smw * LLQ_MEM BAR 292325234Smw */ 293325234Smw uint32_t llq_descriptors_offset; 294325234Smw 295325234Smw /* low latency queue headers' memory as an offset to PCIe MMIO 296325234Smw * LLQ_MEM BAR 297325234Smw */ 298325234Smw uint32_t llq_headers_offset; 299325234Smw}; 300325234Smw 301325234Smwstruct ena_admin_aq_destroy_sq_cmd { 302325234Smw struct ena_admin_aq_common_desc aq_common_descriptor; 303325234Smw 304325234Smw struct ena_admin_sq sq; 305325234Smw}; 306325234Smw 307325234Smwstruct ena_admin_acq_destroy_sq_resp_desc { 308325234Smw struct ena_admin_acq_common_desc acq_common_desc; 309325234Smw}; 310325234Smw 311325234Smwstruct ena_admin_aq_create_cq_cmd { 312325234Smw struct ena_admin_aq_common_desc aq_common_descriptor; 313325234Smw 314325234Smw /* 4:0 : reserved5 315325234Smw * 5 : interrupt_mode_enabled - if set, cq operates 316325234Smw * in interrupt mode, otherwise - polling 317325234Smw * 7:6 : reserved6 318325234Smw */ 319325234Smw uint8_t cq_caps_1; 320325234Smw 321325234Smw /* 4:0 : cq_entry_size_words - size of CQ entry in 322325234Smw * 32-bit words, valid values: 4, 8. 323325234Smw * 7:5 : reserved7 324325234Smw */ 325325234Smw uint8_t cq_caps_2; 326325234Smw 327325234Smw /* completion queue depth in # of entries. must be power of 2 */ 328325234Smw uint16_t cq_depth; 329325234Smw 330325234Smw /* msix vector assigned to this cq */ 331325234Smw uint32_t msix_vector; 332325234Smw 333325234Smw /* cq physical base address in OS memory. CQ must be physically 334325234Smw * contiguous 335325234Smw */ 336325234Smw struct ena_common_mem_addr cq_ba; 337325234Smw}; 338325234Smw 339325234Smwstruct ena_admin_acq_create_cq_resp_desc { 340325234Smw struct ena_admin_acq_common_desc acq_common_desc; 341325234Smw 342325234Smw uint16_t cq_idx; 343325234Smw 344325234Smw /* actual cq depth in number of entries */ 345325234Smw uint16_t cq_actual_depth; 346325234Smw 347325234Smw uint32_t numa_node_register_offset; 348325234Smw 349325234Smw uint32_t cq_head_db_register_offset; 350325234Smw 351325234Smw uint32_t cq_interrupt_unmask_register_offset; 352325234Smw}; 353325234Smw 354325234Smwstruct ena_admin_aq_destroy_cq_cmd { 355325234Smw struct ena_admin_aq_common_desc aq_common_descriptor; 356325234Smw 357325234Smw uint16_t cq_idx; 358325234Smw 359325234Smw uint16_t reserved1; 360325234Smw}; 361325234Smw 362325234Smwstruct ena_admin_acq_destroy_cq_resp_desc { 363325234Smw struct ena_admin_acq_common_desc acq_common_desc; 364325234Smw}; 365325234Smw 366325234Smw/* ENA AQ Get Statistics command. Extended statistics are placed in control 367325234Smw * buffer pointed by AQ entry 368325234Smw */ 369325234Smwstruct ena_admin_aq_get_stats_cmd { 370325234Smw struct ena_admin_aq_common_desc aq_common_descriptor; 371325234Smw 372325234Smw union { 373325234Smw /* command specific inline data */ 374325234Smw uint32_t inline_data_w1[3]; 375325234Smw 376325234Smw struct ena_admin_ctrl_buff_info control_buffer; 377325234Smw } u; 378325234Smw 379325234Smw /* stats type as defined in enum ena_admin_get_stats_type */ 380325234Smw uint8_t type; 381325234Smw 382325234Smw /* stats scope defined in enum ena_admin_get_stats_scope */ 383325234Smw uint8_t scope; 384325234Smw 385325234Smw uint16_t reserved3; 386325234Smw 387325234Smw /* queue id. used when scope is specific_queue */ 388325234Smw uint16_t queue_idx; 389325234Smw 390325234Smw /* device id, value 0xFFFF means mine. only privileged device can get 391368013Smw * stats of other device 392325234Smw */ 393325234Smw uint16_t device_id; 394325234Smw}; 395325234Smw 396325234Smw/* Basic Statistics Command. */ 397325234Smwstruct ena_admin_basic_stats { 398325234Smw uint32_t tx_bytes_low; 399325234Smw 400325234Smw uint32_t tx_bytes_high; 401325234Smw 402325234Smw uint32_t tx_pkts_low; 403325234Smw 404325234Smw uint32_t tx_pkts_high; 405325234Smw 406325234Smw uint32_t rx_bytes_low; 407325234Smw 408325234Smw uint32_t rx_bytes_high; 409325234Smw 410325234Smw uint32_t rx_pkts_low; 411325234Smw 412325234Smw uint32_t rx_pkts_high; 413325234Smw 414325234Smw uint32_t rx_drops_low; 415325234Smw 416325234Smw uint32_t rx_drops_high; 417361534Smw 418361534Smw uint32_t tx_drops_low; 419361534Smw 420361534Smw uint32_t tx_drops_high; 421325234Smw}; 422325234Smw 423368013Smw/* ENI Statistics Command. */ 424368013Smwstruct ena_admin_eni_stats { 425368013Smw /* The number of packets shaped due to inbound aggregate BW 426368013Smw * allowance being exceeded 427368013Smw */ 428368013Smw uint64_t bw_in_allowance_exceeded; 429368013Smw 430368013Smw /* The number of packets shaped due to outbound aggregate BW 431368013Smw * allowance being exceeded 432368013Smw */ 433368013Smw uint64_t bw_out_allowance_exceeded; 434368013Smw 435368013Smw /* The number of packets shaped due to PPS allowance being exceeded */ 436368013Smw uint64_t pps_allowance_exceeded; 437368013Smw 438368013Smw /* The number of packets shaped due to connection tracking 439368013Smw * allowance being exceeded and leading to failure in establishment 440368013Smw * of new connections 441368013Smw */ 442368013Smw uint64_t conntrack_allowance_exceeded; 443368013Smw 444368013Smw /* The number of packets shaped due to linklocal packet rate 445368013Smw * allowance being exceeded 446368013Smw */ 447368013Smw uint64_t linklocal_allowance_exceeded; 448368013Smw}; 449368013Smw 450325234Smwstruct ena_admin_acq_get_stats_resp { 451325234Smw struct ena_admin_acq_common_desc acq_common_desc; 452325234Smw 453368013Smw union { 454368013Smw uint64_t raw[7]; 455368013Smw 456368013Smw struct ena_admin_basic_stats basic_stats; 457368013Smw 458368013Smw struct ena_admin_eni_stats eni_stats; 459368013Smw } u; 460325234Smw}; 461325234Smw 462325234Smwstruct ena_admin_get_set_feature_common_desc { 463325234Smw /* 1:0 : select - 0x1 - current value; 0x3 - default 464325234Smw * value 465325234Smw * 7:3 : reserved3 466325234Smw */ 467325234Smw uint8_t flags; 468325234Smw 469325234Smw /* as appears in ena_admin_aq_feature_id */ 470325234Smw uint8_t feature_id; 471325234Smw 472361467Smw /* The driver specifies the max feature version it supports and the 473368013Smw * device responds with the currently supported feature version. The 474368013Smw * field is zero based 475361467Smw */ 476361467Smw uint8_t feature_version; 477361467Smw 478361467Smw uint8_t reserved8; 479325234Smw}; 480325234Smw 481325234Smwstruct ena_admin_device_attr_feature_desc { 482325234Smw uint32_t impl_id; 483325234Smw 484325234Smw uint32_t device_version; 485325234Smw 486368013Smw /* bitmap of ena_admin_aq_feature_id, which represents supported 487368013Smw * subcommands for the set/get feature admin commands. 488368013Smw */ 489325234Smw uint32_t supported_features; 490325234Smw 491325234Smw uint32_t reserved3; 492325234Smw 493325234Smw /* Indicates how many bits are used physical address access. */ 494325234Smw uint32_t phys_addr_width; 495325234Smw 496325234Smw /* Indicates how many bits are used virtual address access. */ 497325234Smw uint32_t virt_addr_width; 498325234Smw 499325234Smw /* unicast MAC address (in Network byte order) */ 500325234Smw uint8_t mac_addr[6]; 501325234Smw 502325234Smw uint8_t reserved7[2]; 503325234Smw 504325234Smw uint32_t max_mtu; 505325234Smw}; 506325234Smw 507325234Smwenum ena_admin_llq_header_location { 508325234Smw /* header is in descriptor list */ 509361467Smw ENA_ADMIN_INLINE_HEADER = 1, 510325234Smw /* header in a separate ring, implies 16B descriptor list entry */ 511361467Smw ENA_ADMIN_HEADER_RING = 2, 512325234Smw}; 513325234Smw 514325234Smwenum ena_admin_llq_ring_entry_size { 515361467Smw ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 516361467Smw ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 517361467Smw ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 518325234Smw}; 519325234Smw 520325234Smwenum ena_admin_llq_num_descs_before_header { 521361467Smw ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 522361467Smw ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 523361467Smw ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 524361467Smw ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 525361467Smw ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 526325234Smw}; 527325234Smw 528325234Smw/* packet descriptor list entry always starts with one or more descriptors, 529325234Smw * followed by a header. The rest of the descriptors are located in the 530325234Smw * beginning of the subsequent entry. Stride refers to how the rest of the 531325234Smw * descriptors are placed. This field is relevant only for inline header 532325234Smw * mode 533325234Smw */ 534325234Smwenum ena_admin_llq_stride_ctrl { 535361467Smw ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 536361467Smw ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 537325234Smw}; 538325234Smw 539361534Smwenum ena_admin_accel_mode_feat { 540361534Smw ENA_ADMIN_DISABLE_META_CACHING = 0, 541361534Smw ENA_ADMIN_LIMIT_TX_BURST = 1, 542361534Smw}; 543361534Smw 544361534Smwstruct ena_admin_accel_mode_get { 545361534Smw /* bit field of enum ena_admin_accel_mode_feat */ 546361534Smw uint16_t supported_flags; 547361534Smw 548361534Smw /* maximum burst size between two doorbells. The size is in bytes */ 549361534Smw uint16_t max_tx_burst_size; 550361534Smw}; 551361534Smw 552361534Smwstruct ena_admin_accel_mode_set { 553361534Smw /* bit field of enum ena_admin_accel_mode_feat */ 554361534Smw uint16_t enabled_flags; 555361534Smw 556361534Smw uint16_t reserved; 557361534Smw}; 558361534Smw 559361534Smwstruct ena_admin_accel_mode_req { 560361534Smw union { 561361534Smw uint32_t raw[2]; 562361534Smw 563361534Smw struct ena_admin_accel_mode_get get; 564361534Smw 565361534Smw struct ena_admin_accel_mode_set set; 566361534Smw } u; 567361534Smw}; 568361534Smw 569325234Smwstruct ena_admin_feature_llq_desc { 570325234Smw uint32_t max_llq_num; 571325234Smw 572325234Smw uint32_t max_llq_depth; 573325234Smw 574368013Smw /* specify the header locations the device supports. bitfield of enum 575368013Smw * ena_admin_llq_header_location. 576361467Smw */ 577361467Smw uint16_t header_location_ctrl_supported; 578325234Smw 579361467Smw /* the header location the driver selected to use. */ 580361467Smw uint16_t header_location_ctrl_enabled; 581361467Smw 582368013Smw /* if inline header is specified - this is the size of descriptor list 583368013Smw * entry. If header in a separate ring is specified - this is the size 584368013Smw * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size. 585368013Smw * specify the entry sizes the device supports 586325234Smw */ 587361467Smw uint16_t entry_size_ctrl_supported; 588325234Smw 589361467Smw /* the entry size the driver selected to use. */ 590361467Smw uint16_t entry_size_ctrl_enabled; 591361467Smw 592368013Smw /* valid only if inline header is specified. First entry associated with 593368013Smw * the packet includes descriptors and header. Rest of the entries 594368013Smw * occupied by descriptors. This parameter defines the max number of 595368013Smw * descriptors precedding the header in the first entry. The field is 596368013Smw * bitfield of enum ena_admin_llq_num_descs_before_header and specify 597368013Smw * the values the device supports 598325234Smw */ 599361467Smw uint16_t desc_num_before_header_supported; 600325234Smw 601361467Smw /* the desire field the driver selected to use */ 602361467Smw uint16_t desc_num_before_header_enabled; 603361467Smw 604361467Smw /* valid only if inline was chosen. bitfield of enum 605368013Smw * ena_admin_llq_stride_ctrl 606325234Smw */ 607361467Smw uint16_t descriptors_stride_ctrl_supported; 608361467Smw 609361467Smw /* the stride control the driver selected to use */ 610361467Smw uint16_t descriptors_stride_ctrl_enabled; 611361467Smw 612361534Smw /* reserved */ 613361534Smw uint32_t reserved1; 614361534Smw 615368013Smw /* accelerated low latency queues requirement. driver needs to 616368013Smw * support those requirements in order to use accelerated llq 617361467Smw */ 618361534Smw struct ena_admin_accel_mode_req accel_mode; 619325234Smw}; 620325234Smw 621361467Smwstruct ena_admin_queue_ext_feature_fields { 622361467Smw uint32_t max_tx_sq_num; 623361467Smw 624361467Smw uint32_t max_tx_cq_num; 625361467Smw 626361467Smw uint32_t max_rx_sq_num; 627361467Smw 628361467Smw uint32_t max_rx_cq_num; 629361467Smw 630361467Smw uint32_t max_tx_sq_depth; 631361467Smw 632361467Smw uint32_t max_tx_cq_depth; 633361467Smw 634361467Smw uint32_t max_rx_sq_depth; 635361467Smw 636361467Smw uint32_t max_rx_cq_depth; 637361467Smw 638361467Smw uint32_t max_tx_header_size; 639361467Smw 640368013Smw /* Maximum Descriptors number, including meta descriptor, allowed for a 641368013Smw * single Tx packet 642361467Smw */ 643361467Smw uint16_t max_per_packet_tx_descs; 644361467Smw 645361467Smw /* Maximum Descriptors number allowed for a single Rx packet */ 646361467Smw uint16_t max_per_packet_rx_descs; 647361467Smw}; 648361467Smw 649325234Smwstruct ena_admin_queue_feature_desc { 650325234Smw uint32_t max_sq_num; 651325234Smw 652325234Smw uint32_t max_sq_depth; 653325234Smw 654325234Smw uint32_t max_cq_num; 655325234Smw 656325234Smw uint32_t max_cq_depth; 657325234Smw 658325234Smw uint32_t max_legacy_llq_num; 659325234Smw 660325234Smw uint32_t max_legacy_llq_depth; 661325234Smw 662325234Smw uint32_t max_header_size; 663325234Smw 664368013Smw /* Maximum Descriptors number, including meta descriptor, allowed for a 665368013Smw * single Tx packet 666325234Smw */ 667325234Smw uint16_t max_packet_tx_descs; 668325234Smw 669325234Smw /* Maximum Descriptors number allowed for a single Rx packet */ 670325234Smw uint16_t max_packet_rx_descs; 671325234Smw}; 672325234Smw 673325234Smwstruct ena_admin_set_feature_mtu_desc { 674325234Smw /* exclude L2 */ 675325234Smw uint32_t mtu; 676325234Smw}; 677325234Smw 678361467Smwstruct ena_admin_get_extra_properties_strings_desc { 679361467Smw uint32_t count; 680361467Smw}; 681361467Smw 682361467Smwstruct ena_admin_get_extra_properties_flags_desc { 683361467Smw uint32_t flags; 684361467Smw}; 685361467Smw 686325234Smwstruct ena_admin_set_feature_host_attr_desc { 687325234Smw /* host OS info base address in OS memory. host info is 4KB of 688325234Smw * physically contiguous 689325234Smw */ 690325234Smw struct ena_common_mem_addr os_info_ba; 691325234Smw 692325234Smw /* host debug area base address in OS memory. debug area must be 693325234Smw * physically contiguous 694325234Smw */ 695325234Smw struct ena_common_mem_addr debug_ba; 696325234Smw 697325234Smw /* debug area size */ 698325234Smw uint32_t debug_area_size; 699325234Smw}; 700325234Smw 701325234Smwstruct ena_admin_feature_intr_moder_desc { 702325234Smw /* interrupt delay granularity in usec */ 703325234Smw uint16_t intr_delay_resolution; 704325234Smw 705325234Smw uint16_t reserved; 706325234Smw}; 707325234Smw 708325234Smwstruct ena_admin_get_feature_link_desc { 709325234Smw /* Link speed in Mb */ 710325234Smw uint32_t speed; 711325234Smw 712325234Smw /* bit field of enum ena_admin_link types */ 713325234Smw uint32_t supported; 714325234Smw 715325234Smw /* 0 : autoneg 716325234Smw * 1 : duplex - Full Duplex 717325234Smw * 31:2 : reserved2 718325234Smw */ 719325234Smw uint32_t flags; 720325234Smw}; 721325234Smw 722325234Smwstruct ena_admin_feature_aenq_desc { 723325234Smw /* bitmask for AENQ groups the device can report */ 724325234Smw uint32_t supported_groups; 725325234Smw 726325234Smw /* bitmask for AENQ groups to report */ 727325234Smw uint32_t enabled_groups; 728325234Smw}; 729325234Smw 730325234Smwstruct ena_admin_feature_offload_desc { 731325234Smw /* 0 : TX_L3_csum_ipv4 732325234Smw * 1 : TX_L4_ipv4_csum_part - The checksum field 733325234Smw * should be initialized with pseudo header checksum 734325234Smw * 2 : TX_L4_ipv4_csum_full 735325234Smw * 3 : TX_L4_ipv6_csum_part - The checksum field 736325234Smw * should be initialized with pseudo header checksum 737325234Smw * 4 : TX_L4_ipv6_csum_full 738325234Smw * 5 : tso_ipv4 739325234Smw * 6 : tso_ipv6 740325234Smw * 7 : tso_ecn 741325234Smw */ 742325234Smw uint32_t tx; 743325234Smw 744325234Smw /* Receive side supported stateless offload 745325234Smw * 0 : RX_L3_csum_ipv4 - IPv4 checksum 746325234Smw * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 747325234Smw * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 748325234Smw * 3 : RX_hash - Hash calculation 749325234Smw */ 750325234Smw uint32_t rx_supported; 751325234Smw 752325234Smw uint32_t rx_enabled; 753325234Smw}; 754325234Smw 755325234Smwenum ena_admin_hash_functions { 756361467Smw ENA_ADMIN_TOEPLITZ = 1, 757361467Smw ENA_ADMIN_CRC32 = 2, 758325234Smw}; 759325234Smw 760325234Smwstruct ena_admin_feature_rss_flow_hash_control { 761368013Smw uint32_t key_parts; 762325234Smw 763325234Smw uint32_t reserved; 764325234Smw 765368013Smw uint32_t key[ENA_ADMIN_RSS_KEY_PARTS]; 766325234Smw}; 767325234Smw 768325234Smwstruct ena_admin_feature_rss_flow_hash_function { 769325234Smw /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 770325234Smw uint32_t supported_func; 771325234Smw 772325234Smw /* 7:0 : selected_func - bitmask of 773325234Smw * ena_admin_hash_functions 774325234Smw */ 775325234Smw uint32_t selected_func; 776325234Smw 777325234Smw /* initial value */ 778325234Smw uint32_t init_val; 779325234Smw}; 780325234Smw 781325234Smw/* RSS flow hash protocols */ 782325234Smwenum ena_admin_flow_hash_proto { 783361467Smw ENA_ADMIN_RSS_TCP4 = 0, 784361467Smw ENA_ADMIN_RSS_UDP4 = 1, 785361467Smw ENA_ADMIN_RSS_TCP6 = 2, 786361467Smw ENA_ADMIN_RSS_UDP6 = 3, 787361467Smw ENA_ADMIN_RSS_IP4 = 4, 788361467Smw ENA_ADMIN_RSS_IP6 = 5, 789361467Smw ENA_ADMIN_RSS_IP4_FRAG = 6, 790361467Smw ENA_ADMIN_RSS_NOT_IP = 7, 791325234Smw /* TCPv6 with extension header */ 792361467Smw ENA_ADMIN_RSS_TCP6_EX = 8, 793325234Smw /* IPv6 with extension header */ 794361467Smw ENA_ADMIN_RSS_IP6_EX = 9, 795361467Smw ENA_ADMIN_RSS_PROTO_NUM = 16, 796325234Smw}; 797325234Smw 798325234Smw/* RSS flow hash fields */ 799325234Smwenum ena_admin_flow_hash_fields { 800325234Smw /* Ethernet Dest Addr */ 801361467Smw ENA_ADMIN_RSS_L2_DA = BIT(0), 802325234Smw /* Ethernet Src Addr */ 803361467Smw ENA_ADMIN_RSS_L2_SA = BIT(1), 804325234Smw /* ipv4/6 Dest Addr */ 805361467Smw ENA_ADMIN_RSS_L3_DA = BIT(2), 806325234Smw /* ipv4/6 Src Addr */ 807361467Smw ENA_ADMIN_RSS_L3_SA = BIT(3), 808325234Smw /* tcp/udp Dest Port */ 809361467Smw ENA_ADMIN_RSS_L4_DP = BIT(4), 810325234Smw /* tcp/udp Src Port */ 811361467Smw ENA_ADMIN_RSS_L4_SP = BIT(5), 812325234Smw}; 813325234Smw 814325234Smwstruct ena_admin_proto_input { 815325234Smw /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 816325234Smw uint16_t fields; 817325234Smw 818325234Smw uint16_t reserved2; 819325234Smw}; 820325234Smw 821325234Smwstruct ena_admin_feature_rss_hash_control { 822325234Smw struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 823325234Smw 824325234Smw struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 825325234Smw 826325234Smw struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 827325234Smw 828325234Smw struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 829325234Smw}; 830325234Smw 831325234Smwstruct ena_admin_feature_rss_flow_hash_input { 832325234Smw /* supported hash input sorting 833325234Smw * 1 : L3_sort - support swap L3 addresses if DA is 834325234Smw * smaller than SA 835325234Smw * 2 : L4_sort - support swap L4 ports if DP smaller 836325234Smw * SP 837325234Smw */ 838325234Smw uint16_t supported_input_sort; 839325234Smw 840325234Smw /* enabled hash input sorting 841325234Smw * 1 : enable_L3_sort - enable swap L3 addresses if 842325234Smw * DA smaller than SA 843325234Smw * 2 : enable_L4_sort - enable swap L4 ports if DP 844325234Smw * smaller than SP 845325234Smw */ 846325234Smw uint16_t enabled_input_sort; 847325234Smw}; 848325234Smw 849325234Smwenum ena_admin_os_type { 850361467Smw ENA_ADMIN_OS_LINUX = 1, 851361467Smw ENA_ADMIN_OS_WIN = 2, 852361467Smw ENA_ADMIN_OS_DPDK = 3, 853361467Smw ENA_ADMIN_OS_FREEBSD = 4, 854361467Smw ENA_ADMIN_OS_IPXE = 5, 855361467Smw ENA_ADMIN_OS_ESXI = 6, 856361467Smw ENA_ADMIN_OS_GROUPS_NUM = 6, 857325234Smw}; 858325234Smw 859325234Smwstruct ena_admin_host_info { 860325234Smw /* defined in enum ena_admin_os_type */ 861325234Smw uint32_t os_type; 862325234Smw 863325234Smw /* os distribution string format */ 864325234Smw uint8_t os_dist_str[128]; 865325234Smw 866325234Smw /* OS distribution numeric format */ 867325234Smw uint32_t os_dist; 868325234Smw 869325234Smw /* kernel version string format */ 870325234Smw uint8_t kernel_ver_str[32]; 871325234Smw 872325234Smw /* Kernel version numeric format */ 873325234Smw uint32_t kernel_ver; 874325234Smw 875325234Smw /* 7:0 : major 876325234Smw * 15:8 : minor 877325234Smw * 23:16 : sub_minor 878361467Smw * 31:24 : module_type 879325234Smw */ 880325234Smw uint32_t driver_version; 881325234Smw 882325234Smw /* features bitmap */ 883361467Smw uint32_t supported_network_features[2]; 884361467Smw 885361467Smw /* ENA spec version of driver */ 886361467Smw uint16_t ena_spec_version; 887361467Smw 888361467Smw /* ENA device's Bus, Device and Function 889361467Smw * 2:0 : function 890361467Smw * 7:3 : device 891361467Smw * 15:8 : bus 892361467Smw */ 893361467Smw uint16_t bdf; 894361467Smw 895361467Smw /* Number of CPUs */ 896361467Smw uint16_t num_cpus; 897361467Smw 898361467Smw uint16_t reserved; 899361534Smw 900368013Smw /* 0 : reserved 901361534Smw * 1 : rx_offset 902361534Smw * 2 : interrupt_moderation 903368013Smw * 3 : rx_buf_mirroring 904368013Smw * 4 : rss_configurable_function_key 905368013Smw * 31:5 : reserved 906361534Smw */ 907361534Smw uint32_t driver_supported_features; 908325234Smw}; 909325234Smw 910325234Smwstruct ena_admin_rss_ind_table_entry { 911325234Smw uint16_t cq_idx; 912325234Smw 913325234Smw uint16_t reserved; 914325234Smw}; 915325234Smw 916325234Smwstruct ena_admin_feature_rss_ind_table { 917325234Smw /* min supported table size (2^min_size) */ 918325234Smw uint16_t min_size; 919325234Smw 920325234Smw /* max supported table size (2^max_size) */ 921325234Smw uint16_t max_size; 922325234Smw 923325234Smw /* table size (2^size) */ 924325234Smw uint16_t size; 925325234Smw 926361467Smw /* 0 : one_entry_update - The ENA device supports 927361467Smw * setting a single RSS table entry 928361467Smw */ 929361467Smw uint8_t flags; 930325234Smw 931361467Smw uint8_t reserved; 932361467Smw 933325234Smw /* index of the inline entry. 0xFFFFFFFF means invalid */ 934325234Smw uint32_t inline_index; 935325234Smw 936325234Smw /* used for updating single entry, ignored when setting the entire 937325234Smw * table through the control buffer. 938325234Smw */ 939325234Smw struct ena_admin_rss_ind_table_entry inline_entry; 940325234Smw}; 941325234Smw 942325234Smw/* When hint value is 0, driver should use it's own predefined value */ 943325234Smwstruct ena_admin_ena_hw_hints { 944325234Smw /* value in ms */ 945325234Smw uint16_t mmio_read_timeout; 946325234Smw 947325234Smw /* value in ms */ 948325234Smw uint16_t driver_watchdog_timeout; 949325234Smw 950325234Smw /* Per packet tx completion timeout. value in ms */ 951325234Smw uint16_t missing_tx_completion_timeout; 952325234Smw 953325234Smw uint16_t missed_tx_completion_count_threshold_to_reset; 954325234Smw 955325234Smw /* value in ms */ 956325234Smw uint16_t admin_completion_tx_timeout; 957325234Smw 958325234Smw uint16_t netdev_wd_timeout; 959325234Smw 960325234Smw uint16_t max_tx_sgl_size; 961325234Smw 962325234Smw uint16_t max_rx_sgl_size; 963325234Smw 964325234Smw uint16_t reserved[8]; 965325234Smw}; 966325234Smw 967325234Smwstruct ena_admin_get_feat_cmd { 968325234Smw struct ena_admin_aq_common_desc aq_common_descriptor; 969325234Smw 970325234Smw struct ena_admin_ctrl_buff_info control_buffer; 971325234Smw 972325234Smw struct ena_admin_get_set_feature_common_desc feat_common; 973325234Smw 974325234Smw uint32_t raw[11]; 975325234Smw}; 976325234Smw 977361467Smwstruct ena_admin_queue_ext_feature_desc { 978361467Smw /* version */ 979361467Smw uint8_t version; 980361467Smw 981361467Smw uint8_t reserved1[3]; 982361467Smw 983361467Smw union { 984361467Smw struct ena_admin_queue_ext_feature_fields max_queue_ext; 985361467Smw 986361467Smw uint32_t raw[10]; 987368013Smw }; 988361467Smw}; 989361467Smw 990325234Smwstruct ena_admin_get_feat_resp { 991325234Smw struct ena_admin_acq_common_desc acq_common_desc; 992325234Smw 993325234Smw union { 994325234Smw uint32_t raw[14]; 995325234Smw 996325234Smw struct ena_admin_device_attr_feature_desc dev_attr; 997325234Smw 998325234Smw struct ena_admin_feature_llq_desc llq; 999325234Smw 1000325234Smw struct ena_admin_queue_feature_desc max_queue; 1001325234Smw 1002361467Smw struct ena_admin_queue_ext_feature_desc max_queue_ext; 1003361467Smw 1004325234Smw struct ena_admin_feature_aenq_desc aenq; 1005325234Smw 1006325234Smw struct ena_admin_get_feature_link_desc link; 1007325234Smw 1008325234Smw struct ena_admin_feature_offload_desc offload; 1009325234Smw 1010325234Smw struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1011325234Smw 1012325234Smw struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1013325234Smw 1014325234Smw struct ena_admin_feature_rss_ind_table ind_table; 1015325234Smw 1016325234Smw struct ena_admin_feature_intr_moder_desc intr_moderation; 1017325234Smw 1018325234Smw struct ena_admin_ena_hw_hints hw_hints; 1019361467Smw 1020361467Smw struct ena_admin_get_extra_properties_strings_desc extra_properties_strings; 1021361467Smw 1022361467Smw struct ena_admin_get_extra_properties_flags_desc extra_properties_flags; 1023325234Smw } u; 1024325234Smw}; 1025325234Smw 1026325234Smwstruct ena_admin_set_feat_cmd { 1027325234Smw struct ena_admin_aq_common_desc aq_common_descriptor; 1028325234Smw 1029325234Smw struct ena_admin_ctrl_buff_info control_buffer; 1030325234Smw 1031325234Smw struct ena_admin_get_set_feature_common_desc feat_common; 1032325234Smw 1033325234Smw union { 1034325234Smw uint32_t raw[11]; 1035325234Smw 1036325234Smw /* mtu size */ 1037325234Smw struct ena_admin_set_feature_mtu_desc mtu; 1038325234Smw 1039325234Smw /* host attributes */ 1040325234Smw struct ena_admin_set_feature_host_attr_desc host_attr; 1041325234Smw 1042325234Smw /* AENQ configuration */ 1043325234Smw struct ena_admin_feature_aenq_desc aenq; 1044325234Smw 1045325234Smw /* rss flow hash function */ 1046325234Smw struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1047325234Smw 1048325234Smw /* rss flow hash input */ 1049325234Smw struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1050325234Smw 1051325234Smw /* rss indirection table */ 1052325234Smw struct ena_admin_feature_rss_ind_table ind_table; 1053361467Smw 1054361467Smw /* LLQ configuration */ 1055361467Smw struct ena_admin_feature_llq_desc llq; 1056325234Smw } u; 1057325234Smw}; 1058325234Smw 1059325234Smwstruct ena_admin_set_feat_resp { 1060325234Smw struct ena_admin_acq_common_desc acq_common_desc; 1061325234Smw 1062325234Smw union { 1063325234Smw uint32_t raw[14]; 1064325234Smw } u; 1065325234Smw}; 1066325234Smw 1067325234Smwstruct ena_admin_aenq_common_desc { 1068325234Smw uint16_t group; 1069325234Smw 1070368013Smw uint16_t syndrome; 1071325234Smw 1072361467Smw /* 0 : phase 1073361467Smw * 7:1 : reserved - MBZ 1074361467Smw */ 1075325234Smw uint8_t flags; 1076325234Smw 1077325234Smw uint8_t reserved1[3]; 1078325234Smw 1079325234Smw uint32_t timestamp_low; 1080325234Smw 1081325234Smw uint32_t timestamp_high; 1082325234Smw}; 1083325234Smw 1084325234Smw/* asynchronous event notification groups */ 1085325234Smwenum ena_admin_aenq_group { 1086361467Smw ENA_ADMIN_LINK_CHANGE = 0, 1087361467Smw ENA_ADMIN_FATAL_ERROR = 1, 1088361467Smw ENA_ADMIN_WARNING = 2, 1089361467Smw ENA_ADMIN_NOTIFICATION = 3, 1090361467Smw ENA_ADMIN_KEEP_ALIVE = 4, 1091361467Smw ENA_ADMIN_AENQ_GROUPS_NUM = 5, 1092325234Smw}; 1093325234Smw 1094368013Smwenum ena_admin_aenq_notification_syndrome { 1095361467Smw ENA_ADMIN_SUSPEND = 0, 1096361467Smw ENA_ADMIN_RESUME = 1, 1097361467Smw ENA_ADMIN_UPDATE_HINTS = 2, 1098325234Smw}; 1099325234Smw 1100325234Smwstruct ena_admin_aenq_entry { 1101325234Smw struct ena_admin_aenq_common_desc aenq_common_desc; 1102325234Smw 1103325234Smw /* command specific inline data */ 1104325234Smw uint32_t inline_data_w4[12]; 1105325234Smw}; 1106325234Smw 1107325234Smwstruct ena_admin_aenq_link_change_desc { 1108325234Smw struct ena_admin_aenq_common_desc aenq_common_desc; 1109325234Smw 1110325234Smw /* 0 : link_status */ 1111325234Smw uint32_t flags; 1112325234Smw}; 1113325234Smw 1114325234Smwstruct ena_admin_aenq_keep_alive_desc { 1115325234Smw struct ena_admin_aenq_common_desc aenq_common_desc; 1116325234Smw 1117325234Smw uint32_t rx_drops_low; 1118325234Smw 1119325234Smw uint32_t rx_drops_high; 1120361534Smw 1121361534Smw uint32_t tx_drops_low; 1122361534Smw 1123361534Smw uint32_t tx_drops_high; 1124325234Smw}; 1125325234Smw 1126325234Smwstruct ena_admin_ena_mmio_req_read_less_resp { 1127325234Smw uint16_t req_id; 1128325234Smw 1129325234Smw uint16_t reg_off; 1130325234Smw 1131325234Smw /* value is valid when poll is cleared */ 1132325234Smw uint32_t reg_val; 1133325234Smw}; 1134325234Smw 1135325234Smw/* aq_common_desc */ 1136361467Smw#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1137361467Smw#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1138361467Smw#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1139361467Smw#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1140361467Smw#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1141361467Smw#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1142325234Smw 1143325234Smw/* sq */ 1144361467Smw#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1145361467Smw#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1146325234Smw 1147325234Smw/* acq_common_desc */ 1148361467Smw#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1149361467Smw#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1150325234Smw 1151325234Smw/* aq_create_sq_cmd */ 1152361467Smw#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1153361467Smw#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1154361467Smw#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1155361467Smw#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1156361467Smw#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1157325234Smw#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1158325234Smw 1159325234Smw/* aq_create_cq_cmd */ 1160325234Smw#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1161325234Smw#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1162325234Smw#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1163325234Smw 1164325234Smw/* get_set_feature_common_desc */ 1165361467Smw#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1166325234Smw 1167325234Smw/* get_feature_link_desc */ 1168361467Smw#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1169361467Smw#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1170361467Smw#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1171325234Smw 1172325234Smw/* feature_offload_desc */ 1173325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1174325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1175325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1176325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1177325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1178325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1179325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1180325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1181325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1182361467Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1183361467Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1184361467Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1185361467Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1186361467Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1187361467Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1188325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1189325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1190325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1191325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1192325234Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1193361467Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1194361467Smw#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1195325234Smw 1196325234Smw/* feature_rss_flow_hash_function */ 1197325234Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1198325234Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1199325234Smw 1200325234Smw/* feature_rss_flow_hash_input */ 1201325234Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1202361467Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1203325234Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1204361467Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1205325234Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1206325234Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1207325234Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1208325234Smw#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1209325234Smw 1210325234Smw/* host_info */ 1211361467Smw#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1212361467Smw#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1213361467Smw#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1214361467Smw#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1215361467Smw#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1216361467Smw#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1217361467Smw#define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1218361467Smw#define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1219361467Smw#define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1220361467Smw#define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1221361467Smw#define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1222361467Smw#define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1223361534Smw#define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 1224361534Smw#define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) 1225361534Smw#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 1226361534Smw#define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 1227368013Smw#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 1228368013Smw#define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) 1229368013Smw#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 1230368013Smw#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) 1231325234Smw 1232361467Smw/* feature_rss_ind_table */ 1233361467Smw#define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0) 1234361467Smw 1235325234Smw/* aenq_common_desc */ 1236361467Smw#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1237325234Smw 1238325234Smw/* aenq_link_change_desc */ 1239361467Smw#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1240325234Smw 1241361467Smw#if !defined(DEFS_LINUX_MAINLINE) 1242325234Smwstatic inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p) 1243325234Smw{ 1244325234Smw return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 1245325234Smw} 1246325234Smw 1247325234Smwstatic inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val) 1248325234Smw{ 1249325234Smw p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 1250325234Smw} 1251325234Smw 1252325234Smwstatic inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p) 1253325234Smw{ 1254325234Smw return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 1255325234Smw} 1256325234Smw 1257325234Smwstatic inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val) 1258325234Smw{ 1259325234Smw p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 1260325234Smw} 1261325234Smw 1262325234Smwstatic inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p) 1263325234Smw{ 1264325234Smw return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT; 1265325234Smw} 1266325234Smw 1267325234Smwstatic inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val) 1268325234Smw{ 1269325234Smw p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK; 1270325234Smw} 1271325234Smw 1272325234Smwstatic inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p) 1273325234Smw{ 1274325234Smw return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT; 1275325234Smw} 1276325234Smw 1277325234Smwstatic inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val) 1278325234Smw{ 1279325234Smw p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 1280325234Smw} 1281325234Smw 1282325234Smwstatic inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p) 1283325234Smw{ 1284325234Smw return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT; 1285325234Smw} 1286325234Smw 1287325234Smwstatic inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val) 1288325234Smw{ 1289325234Smw p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 1290325234Smw} 1291325234Smw 1292325234Smwstatic inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p) 1293325234Smw{ 1294325234Smw return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 1295325234Smw} 1296325234Smw 1297325234Smwstatic inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val) 1298325234Smw{ 1299325234Smw p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 1300325234Smw} 1301325234Smw 1302325234Smwstatic inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p) 1303325234Smw{ 1304325234Smw return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; 1305325234Smw} 1306325234Smw 1307325234Smwstatic inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val) 1308325234Smw{ 1309325234Smw p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; 1310325234Smw} 1311325234Smw 1312325234Smwstatic inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p) 1313325234Smw{ 1314325234Smw return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT; 1315325234Smw} 1316325234Smw 1317325234Smwstatic inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1318325234Smw{ 1319325234Smw p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1320325234Smw} 1321325234Smw 1322325234Smwstatic inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p) 1323325234Smw{ 1324325234Smw return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1325325234Smw} 1326325234Smw 1327325234Smwstatic inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1328325234Smw{ 1329325234Smw p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1330325234Smw} 1331325234Smw 1332325234Smwstatic inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p) 1333325234Smw{ 1334325234Smw return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT; 1335325234Smw} 1336325234Smw 1337325234Smwstatic inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1338325234Smw{ 1339325234Smw p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1340325234Smw} 1341325234Smw 1342325234Smwstatic inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p) 1343325234Smw{ 1344325234Smw return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1345325234Smw} 1346325234Smw 1347325234Smwstatic inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1348325234Smw{ 1349325234Smw p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1350325234Smw} 1351325234Smw 1352325234Smwstatic inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p) 1353325234Smw{ 1354325234Smw return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT; 1355325234Smw} 1356325234Smw 1357325234Smwstatic inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val) 1358325234Smw{ 1359325234Smw p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1360325234Smw} 1361325234Smw 1362325234Smwstatic inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p) 1363325234Smw{ 1364325234Smw return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1365325234Smw} 1366325234Smw 1367325234Smwstatic inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val) 1368325234Smw{ 1369325234Smw p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1370325234Smw} 1371325234Smw 1372325234Smwstatic inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p) 1373325234Smw{ 1374325234Smw return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; 1375325234Smw} 1376325234Smw 1377325234Smwstatic inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val) 1378325234Smw{ 1379325234Smw p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; 1380325234Smw} 1381325234Smw 1382325234Smwstatic inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p) 1383325234Smw{ 1384325234Smw return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; 1385325234Smw} 1386325234Smw 1387325234Smwstatic inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val) 1388325234Smw{ 1389325234Smw p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; 1390325234Smw} 1391325234Smw 1392325234Smwstatic inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p) 1393325234Smw{ 1394325234Smw return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT; 1395325234Smw} 1396325234Smw 1397325234Smwstatic inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val) 1398325234Smw{ 1399325234Smw p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK; 1400325234Smw} 1401325234Smw 1402325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p) 1403325234Smw{ 1404325234Smw return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; 1405325234Smw} 1406325234Smw 1407325234Smwstatic inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1408325234Smw{ 1409325234Smw p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; 1410325234Smw} 1411325234Smw 1412325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p) 1413325234Smw{ 1414325234Smw return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT; 1415325234Smw} 1416325234Smw 1417325234Smwstatic inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val) 1418325234Smw{ 1419325234Smw p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK; 1420325234Smw} 1421325234Smw 1422325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p) 1423325234Smw{ 1424325234Smw return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT; 1425325234Smw} 1426325234Smw 1427325234Smwstatic inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val) 1428325234Smw{ 1429325234Smw p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK; 1430325234Smw} 1431325234Smw 1432325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p) 1433325234Smw{ 1434325234Smw return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT; 1435325234Smw} 1436325234Smw 1437325234Smwstatic inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val) 1438325234Smw{ 1439325234Smw p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK; 1440325234Smw} 1441325234Smw 1442325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p) 1443325234Smw{ 1444325234Smw return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT; 1445325234Smw} 1446325234Smw 1447325234Smwstatic inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val) 1448325234Smw{ 1449325234Smw p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK; 1450325234Smw} 1451325234Smw 1452325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p) 1453325234Smw{ 1454325234Smw return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT; 1455325234Smw} 1456325234Smw 1457325234Smwstatic inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1458325234Smw{ 1459325234Smw p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK; 1460325234Smw} 1461325234Smw 1462325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p) 1463325234Smw{ 1464325234Smw return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT; 1465325234Smw} 1466325234Smw 1467325234Smwstatic inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val) 1468325234Smw{ 1469325234Smw p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK; 1470325234Smw} 1471325234Smw 1472325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p) 1473325234Smw{ 1474325234Smw return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT; 1475325234Smw} 1476325234Smw 1477325234Smwstatic inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val) 1478325234Smw{ 1479325234Smw p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK; 1480325234Smw} 1481325234Smw 1482325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p) 1483325234Smw{ 1484325234Smw return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK; 1485325234Smw} 1486325234Smw 1487325234Smwstatic inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1488325234Smw{ 1489325234Smw p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK; 1490325234Smw} 1491325234Smw 1492325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p) 1493325234Smw{ 1494325234Smw return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT; 1495325234Smw} 1496325234Smw 1497325234Smwstatic inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val) 1498325234Smw{ 1499325234Smw p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK; 1500325234Smw} 1501325234Smw 1502325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p) 1503325234Smw{ 1504325234Smw return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT; 1505325234Smw} 1506325234Smw 1507325234Smwstatic inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val) 1508325234Smw{ 1509325234Smw p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK; 1510325234Smw} 1511325234Smw 1512325234Smwstatic inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p) 1513325234Smw{ 1514325234Smw return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT; 1515325234Smw} 1516325234Smw 1517325234Smwstatic inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val) 1518325234Smw{ 1519325234Smw p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK; 1520325234Smw} 1521325234Smw 1522325234Smwstatic inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p) 1523325234Smw{ 1524325234Smw return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK; 1525325234Smw} 1526325234Smw 1527325234Smwstatic inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val) 1528325234Smw{ 1529325234Smw p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK; 1530325234Smw} 1531325234Smw 1532325234Smwstatic inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p) 1533325234Smw{ 1534325234Smw return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK; 1535325234Smw} 1536325234Smw 1537325234Smwstatic inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val) 1538325234Smw{ 1539325234Smw p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK; 1540325234Smw} 1541325234Smw 1542325234Smwstatic inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1543325234Smw{ 1544325234Smw return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT; 1545325234Smw} 1546325234Smw 1547325234Smwstatic inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1548325234Smw{ 1549325234Smw p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK; 1550325234Smw} 1551325234Smw 1552325234Smwstatic inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1553325234Smw{ 1554325234Smw return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT; 1555325234Smw} 1556325234Smw 1557325234Smwstatic inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1558325234Smw{ 1559325234Smw p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 1560325234Smw} 1561325234Smw 1562325234Smwstatic inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1563325234Smw{ 1564325234Smw return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT; 1565325234Smw} 1566325234Smw 1567325234Smwstatic inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1568325234Smw{ 1569325234Smw p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK; 1570325234Smw} 1571325234Smw 1572325234Smwstatic inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1573325234Smw{ 1574325234Smw return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT; 1575325234Smw} 1576325234Smw 1577325234Smwstatic inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1578325234Smw{ 1579325234Smw p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK; 1580325234Smw} 1581325234Smw 1582325234Smwstatic inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p) 1583325234Smw{ 1584325234Smw return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK; 1585325234Smw} 1586325234Smw 1587325234Smwstatic inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val) 1588325234Smw{ 1589325234Smw p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK; 1590325234Smw} 1591325234Smw 1592325234Smwstatic inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p) 1593325234Smw{ 1594325234Smw return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT; 1595325234Smw} 1596325234Smw 1597325234Smwstatic inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val) 1598325234Smw{ 1599325234Smw p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK; 1600325234Smw} 1601325234Smw 1602325234Smwstatic inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p) 1603325234Smw{ 1604325234Smw return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT; 1605325234Smw} 1606325234Smw 1607325234Smwstatic inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val) 1608325234Smw{ 1609325234Smw p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK; 1610325234Smw} 1611325234Smw 1612361467Smwstatic inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p) 1613361467Smw{ 1614361467Smw return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT; 1615361467Smw} 1616361467Smw 1617361467Smwstatic inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val) 1618361467Smw{ 1619361467Smw p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK; 1620361467Smw} 1621361467Smw 1622361467Smwstatic inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p) 1623361467Smw{ 1624361467Smw return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK; 1625361467Smw} 1626361467Smw 1627361467Smwstatic inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val) 1628361467Smw{ 1629361467Smw p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK; 1630361467Smw} 1631361467Smw 1632361467Smwstatic inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p) 1633361467Smw{ 1634361467Smw return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT; 1635361467Smw} 1636361467Smw 1637361467Smwstatic inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val) 1638361467Smw{ 1639361467Smw p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK; 1640361467Smw} 1641361467Smw 1642361467Smwstatic inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p) 1643361467Smw{ 1644361467Smw return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT; 1645361467Smw} 1646361467Smw 1647361467Smwstatic inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val) 1648361467Smw{ 1649361467Smw p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK; 1650361467Smw} 1651361467Smw 1652361534Smwstatic inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p) 1653361534Smw{ 1654361534Smw return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT; 1655361534Smw} 1656361534Smw 1657361534Smwstatic inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val) 1658361534Smw{ 1659361534Smw p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 1660361534Smw} 1661361534Smw 1662361534Smwstatic inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p) 1663361534Smw{ 1664361534Smw return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT; 1665361534Smw} 1666361534Smw 1667361534Smwstatic inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val) 1668361534Smw{ 1669361534Smw p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK; 1670361534Smw} 1671361534Smw 1672368013Smwstatic inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p) 1673361534Smw{ 1674368013Smw return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT; 1675361534Smw} 1676361534Smw 1677368013Smwstatic inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val) 1678361534Smw{ 1679368013Smw p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK; 1680361534Smw} 1681361534Smw 1682368013Smwstatic inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p) 1683368013Smw{ 1684368013Smw return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK) >> ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT; 1685368013Smw} 1686368013Smw 1687368013Smwstatic inline void set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info *p, uint32_t val) 1688368013Smw{ 1689368013Smw p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK; 1690368013Smw} 1691368013Smw 1692361467Smwstatic inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p) 1693361467Smw{ 1694361467Smw return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK; 1695361467Smw} 1696361467Smw 1697361467Smwstatic inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val) 1698361467Smw{ 1699361467Smw p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK; 1700361467Smw} 1701361467Smw 1702325234Smwstatic inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p) 1703325234Smw{ 1704325234Smw return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; 1705325234Smw} 1706325234Smw 1707325234Smwstatic inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val) 1708325234Smw{ 1709325234Smw p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; 1710325234Smw} 1711325234Smw 1712325234Smwstatic inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p) 1713325234Smw{ 1714325234Smw return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 1715325234Smw} 1716325234Smw 1717325234Smwstatic inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val) 1718325234Smw{ 1719325234Smw p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 1720325234Smw} 1721325234Smw 1722361467Smw#endif /* !defined(DEFS_LINUX_MAINLINE) */ 1723361534Smw#endif /* _ENA_ADMIN_H_ */ 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