1320731Szbb/*- 2320731Szbb * BSD LICENSE 3320731Szbb * 4320731Szbb * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates. 5320731Szbb * All rights reserved. 6320731Szbb * 7320731Szbb * Redistribution and use in source and binary forms, with or without 8320731Szbb * modification, are permitted provided that the following conditions 9320731Szbb * are met: 10320731Szbb * 11320731Szbb * * Redistributions of source code must retain the above copyright 12320731Szbb * notice, this list of conditions and the following disclaimer. 13320731Szbb * * Redistributions in binary form must reproduce the above copyright 14320731Szbb * notice, this list of conditions and the following disclaimer in 15320731Szbb * the documentation and/or other materials provided with the 16320731Szbb * distribution. 17320731Szbb * * Neither the name of copyright holder nor the names of its 18320731Szbb * contributors may be used to endorse or promote products derived 19320731Szbb * from this software without specific prior written permission. 20320731Szbb * 21320731Szbb * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22320731Szbb * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23320731Szbb * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24320731Szbb * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25320731Szbb * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26320731Szbb * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27320731Szbb * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28320731Szbb * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29320731Szbb * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30320731Szbb * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31320731Szbb * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32320731Szbb */ 33320731Szbb 34320731Szbb#ifndef _ENA_ADMIN_H_ 35320731Szbb#define _ENA_ADMIN_H_ 36320731Szbb 37320731Szbbenum ena_admin_aq_opcode { 38320731Szbb ENA_ADMIN_CREATE_SQ = 1, 39320731Szbb 40320731Szbb ENA_ADMIN_DESTROY_SQ = 2, 41320731Szbb 42320731Szbb ENA_ADMIN_CREATE_CQ = 3, 43320731Szbb 44320731Szbb ENA_ADMIN_DESTROY_CQ = 4, 45320731Szbb 46320731Szbb ENA_ADMIN_GET_FEATURE = 8, 47320731Szbb 48320731Szbb ENA_ADMIN_SET_FEATURE = 9, 49320731Szbb 50320731Szbb ENA_ADMIN_GET_STATS = 11, 51320731Szbb}; 52320731Szbb 53320731Szbbenum ena_admin_aq_completion_status { 54320731Szbb ENA_ADMIN_SUCCESS = 0, 55320731Szbb 56320731Szbb ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 57320731Szbb 58320731Szbb ENA_ADMIN_BAD_OPCODE = 2, 59320731Szbb 60320731Szbb ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 61320731Szbb 62320731Szbb ENA_ADMIN_MALFORMED_REQUEST = 4, 63320731Szbb 64320731Szbb /* Additional status is provided in ACQ entry extended_status */ 65320731Szbb ENA_ADMIN_ILLEGAL_PARAMETER = 5, 66320731Szbb 67320731Szbb ENA_ADMIN_UNKNOWN_ERROR = 6, 68320731Szbb}; 69320731Szbb 70320731Szbbenum ena_admin_aq_feature_id { 71320731Szbb ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 72320731Szbb 73320731Szbb ENA_ADMIN_MAX_QUEUES_NUM = 2, 74320731Szbb 75320731Szbb ENA_ADMIN_HW_HINTS = 3, 76320731Szbb 77320731Szbb ENA_ADMIN_RSS_HASH_FUNCTION = 10, 78320731Szbb 79320731Szbb ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 80320731Szbb 81320731Szbb ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, 82320731Szbb 83320731Szbb ENA_ADMIN_MTU = 14, 84320731Szbb 85320731Szbb ENA_ADMIN_RSS_HASH_INPUT = 18, 86320731Szbb 87320731Szbb ENA_ADMIN_INTERRUPT_MODERATION = 20, 88320731Szbb 89320731Szbb ENA_ADMIN_AENQ_CONFIG = 26, 90320731Szbb 91320731Szbb ENA_ADMIN_LINK_CONFIG = 27, 92320731Szbb 93320731Szbb ENA_ADMIN_HOST_ATTR_CONFIG = 28, 94320731Szbb 95320731Szbb ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 96320731Szbb}; 97320731Szbb 98320731Szbbenum ena_admin_placement_policy_type { 99320731Szbb /* descriptors and headers are in host memory */ 100320731Szbb ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 101320731Szbb 102320731Szbb /* descriptors and headers are in device memory (a.k.a Low Latency 103320731Szbb * Queue) 104320731Szbb */ 105320731Szbb ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 106320731Szbb}; 107320731Szbb 108320731Szbbenum ena_admin_link_types { 109320731Szbb ENA_ADMIN_LINK_SPEED_1G = 0x1, 110320731Szbb 111320731Szbb ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 112320731Szbb 113320731Szbb ENA_ADMIN_LINK_SPEED_5G = 0x4, 114320731Szbb 115320731Szbb ENA_ADMIN_LINK_SPEED_10G = 0x8, 116320731Szbb 117320731Szbb ENA_ADMIN_LINK_SPEED_25G = 0x10, 118320731Szbb 119320731Szbb ENA_ADMIN_LINK_SPEED_40G = 0x20, 120320731Szbb 121320731Szbb ENA_ADMIN_LINK_SPEED_50G = 0x40, 122320731Szbb 123320731Szbb ENA_ADMIN_LINK_SPEED_100G = 0x80, 124320731Szbb 125320731Szbb ENA_ADMIN_LINK_SPEED_200G = 0x100, 126320731Szbb 127320731Szbb ENA_ADMIN_LINK_SPEED_400G = 0x200, 128320731Szbb}; 129320731Szbb 130320731Szbbenum ena_admin_completion_policy_type { 131320731Szbb /* completion queue entry for each sq descriptor */ 132320731Szbb ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 133320731Szbb 134320731Szbb /* completion queue entry upon request in sq descriptor */ 135320731Szbb ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 136320731Szbb 137320731Szbb /* current queue head pointer is updated in OS memory upon sq 138320731Szbb * descriptor request 139320731Szbb */ 140320731Szbb ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 141320731Szbb 142320731Szbb /* current queue head pointer is updated in OS memory for each sq 143320731Szbb * descriptor 144320731Szbb */ 145320731Szbb ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 146320731Szbb}; 147320731Szbb 148320731Szbb/* basic stats return ena_admin_basic_stats while extanded stats return a 149320731Szbb * buffer (string format) with additional statistics per queue and per 150320731Szbb * device id 151320731Szbb */ 152320731Szbbenum ena_admin_get_stats_type { 153320731Szbb ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 154320731Szbb 155320731Szbb ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 156320731Szbb}; 157320731Szbb 158320731Szbbenum ena_admin_get_stats_scope { 159320731Szbb ENA_ADMIN_SPECIFIC_QUEUE = 0, 160320731Szbb 161320731Szbb ENA_ADMIN_ETH_TRAFFIC = 1, 162320731Szbb}; 163320731Szbb 164320731Szbbstruct ena_admin_aq_common_desc { 165320731Szbb /* 11:0 : command_id 166320731Szbb * 15:12 : reserved12 167320731Szbb */ 168320731Szbb uint16_t command_id; 169320731Szbb 170320731Szbb /* as appears in ena_admin_aq_opcode */ 171320731Szbb uint8_t opcode; 172320731Szbb 173320731Szbb /* 0 : phase 174320731Szbb * 1 : ctrl_data - control buffer address valid 175320731Szbb * 2 : ctrl_data_indirect - control buffer address 176320731Szbb * points to list of pages with addresses of control 177320731Szbb * buffers 178320731Szbb * 7:3 : reserved3 179320731Szbb */ 180320731Szbb uint8_t flags; 181320731Szbb}; 182320731Szbb 183320731Szbb/* used in ena_admin_aq_entry. Can point directly to control data, or to a 184320731Szbb * page list chunk. Used also at the end of indirect mode page list chunks, 185320731Szbb * for chaining. 186320731Szbb */ 187320731Szbbstruct ena_admin_ctrl_buff_info { 188320731Szbb uint32_t length; 189320731Szbb 190320731Szbb struct ena_common_mem_addr address; 191320731Szbb}; 192320731Szbb 193320731Szbbstruct ena_admin_sq { 194320731Szbb uint16_t sq_idx; 195320731Szbb 196320731Szbb /* 4:0 : reserved 197320731Szbb * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 198320731Szbb */ 199320731Szbb uint8_t sq_identity; 200320731Szbb 201320731Szbb uint8_t reserved1; 202320731Szbb}; 203320731Szbb 204320731Szbbstruct ena_admin_aq_entry { 205320731Szbb struct ena_admin_aq_common_desc aq_common_descriptor; 206320731Szbb 207320731Szbb union { 208320731Szbb uint32_t inline_data_w1[3]; 209320731Szbb 210320731Szbb struct ena_admin_ctrl_buff_info control_buffer; 211320731Szbb } u; 212320731Szbb 213320731Szbb uint32_t inline_data_w4[12]; 214320731Szbb}; 215320731Szbb 216320731Szbbstruct ena_admin_acq_common_desc { 217320731Szbb /* command identifier to associate it with the aq descriptor 218320731Szbb * 11:0 : command_id 219320731Szbb * 15:12 : reserved12 220320731Szbb */ 221320731Szbb uint16_t command; 222320731Szbb 223320731Szbb uint8_t status; 224320731Szbb 225320731Szbb /* 0 : phase 226320731Szbb * 7:1 : reserved1 227320731Szbb */ 228320731Szbb uint8_t flags; 229320731Szbb 230320731Szbb uint16_t extended_status; 231320731Szbb 232320731Szbb /* serves as a hint what AQ entries can be revoked */ 233320731Szbb uint16_t sq_head_indx; 234320731Szbb}; 235320731Szbb 236320731Szbbstruct ena_admin_acq_entry { 237320731Szbb struct ena_admin_acq_common_desc acq_common_descriptor; 238320731Szbb 239320731Szbb uint32_t response_specific_data[14]; 240320731Szbb}; 241320731Szbb 242320731Szbbstruct ena_admin_aq_create_sq_cmd { 243320731Szbb struct ena_admin_aq_common_desc aq_common_descriptor; 244320731Szbb 245320731Szbb /* 4:0 : reserved0_w1 246320731Szbb * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 247320731Szbb */ 248320731Szbb uint8_t sq_identity; 249320731Szbb 250320731Szbb uint8_t reserved8_w1; 251320731Szbb 252320731Szbb /* 3:0 : placement_policy - Describing where the SQ 253320731Szbb * descriptor ring and the SQ packet headers reside: 254320731Szbb * 0x1 - descriptors and headers are in OS memory, 255320731Szbb * 0x3 - descriptors and headers in device memory 256320731Szbb * (a.k.a Low Latency Queue) 257320731Szbb * 6:4 : completion_policy - Describing what policy 258320731Szbb * to use for generation completion entry (cqe) in 259320731Szbb * the CQ associated with this SQ: 0x0 - cqe for each 260320731Szbb * sq descriptor, 0x1 - cqe upon request in sq 261320731Szbb * descriptor, 0x2 - current queue head pointer is 262320731Szbb * updated in OS memory upon sq descriptor request 263320731Szbb * 0x3 - current queue head pointer is updated in OS 264320731Szbb * memory for each sq descriptor 265320731Szbb * 7 : reserved15_w1 266320731Szbb */ 267320731Szbb uint8_t sq_caps_2; 268320731Szbb 269320731Szbb /* 0 : is_physically_contiguous - Described if the 270320731Szbb * queue ring memory is allocated in physical 271320731Szbb * contiguous pages or split. 272320731Szbb * 7:1 : reserved17_w1 273320731Szbb */ 274320731Szbb uint8_t sq_caps_3; 275320731Szbb 276320731Szbb /* associated completion queue id. This CQ must be created prior to 277320731Szbb * SQ creation 278320731Szbb */ 279320731Szbb uint16_t cq_idx; 280320731Szbb 281320731Szbb /* submission queue depth in entries */ 282320731Szbb uint16_t sq_depth; 283320731Szbb 284320731Szbb /* SQ physical base address in OS memory. This field should not be 285320731Szbb * used for Low Latency queues. Has to be page aligned. 286320731Szbb */ 287320731Szbb struct ena_common_mem_addr sq_ba; 288320731Szbb 289320731Szbb /* specifies queue head writeback location in OS memory. Valid if 290320731Szbb * completion_policy is set to completion_policy_head_on_demand or 291320731Szbb * completion_policy_head. Has to be cache aligned 292320731Szbb */ 293320731Szbb struct ena_common_mem_addr sq_head_writeback; 294320731Szbb 295320731Szbb uint32_t reserved0_w7; 296320731Szbb 297320731Szbb uint32_t reserved0_w8; 298320731Szbb}; 299320731Szbb 300320731Szbbenum ena_admin_sq_direction { 301320731Szbb ENA_ADMIN_SQ_DIRECTION_TX = 1, 302320731Szbb 303320731Szbb ENA_ADMIN_SQ_DIRECTION_RX = 2, 304320731Szbb}; 305320731Szbb 306320731Szbbstruct ena_admin_acq_create_sq_resp_desc { 307320731Szbb struct ena_admin_acq_common_desc acq_common_desc; 308320731Szbb 309320731Szbb uint16_t sq_idx; 310320731Szbb 311320731Szbb uint16_t reserved; 312320731Szbb 313320731Szbb /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 314320731Szbb uint32_t sq_doorbell_offset; 315320731Szbb 316320731Szbb /* low latency queue ring base address as an offset to PCIe MMIO 317320731Szbb * LLQ_MEM BAR 318320731Szbb */ 319320731Szbb uint32_t llq_descriptors_offset; 320320731Szbb 321320731Szbb /* low latency queue headers' memory as an offset to PCIe MMIO 322320731Szbb * LLQ_MEM BAR 323320731Szbb */ 324320731Szbb uint32_t llq_headers_offset; 325320731Szbb}; 326320731Szbb 327320731Szbbstruct ena_admin_aq_destroy_sq_cmd { 328320731Szbb struct ena_admin_aq_common_desc aq_common_descriptor; 329320731Szbb 330320731Szbb struct ena_admin_sq sq; 331320731Szbb}; 332320731Szbb 333320731Szbbstruct ena_admin_acq_destroy_sq_resp_desc { 334320731Szbb struct ena_admin_acq_common_desc acq_common_desc; 335320731Szbb}; 336320731Szbb 337320731Szbbstruct ena_admin_aq_create_cq_cmd { 338320731Szbb struct ena_admin_aq_common_desc aq_common_descriptor; 339320731Szbb 340320731Szbb /* 4:0 : reserved5 341320731Szbb * 5 : interrupt_mode_enabled - if set, cq operates 342320731Szbb * in interrupt mode, otherwise - polling 343320731Szbb * 7:6 : reserved6 344320731Szbb */ 345320731Szbb uint8_t cq_caps_1; 346320731Szbb 347320731Szbb /* 4:0 : cq_entry_size_words - size of CQ entry in 348320731Szbb * 32-bit words, valid values: 4, 8. 349320731Szbb * 7:5 : reserved7 350320731Szbb */ 351320731Szbb uint8_t cq_caps_2; 352320731Szbb 353320731Szbb /* completion queue depth in # of entries. must be power of 2 */ 354320731Szbb uint16_t cq_depth; 355320731Szbb 356320731Szbb /* msix vector assigned to this cq */ 357320731Szbb uint32_t msix_vector; 358320731Szbb 359320731Szbb /* cq physical base address in OS memory. CQ must be physically 360320731Szbb * contiguous 361320731Szbb */ 362320731Szbb struct ena_common_mem_addr cq_ba; 363320731Szbb}; 364320731Szbb 365320731Szbbstruct ena_admin_acq_create_cq_resp_desc { 366320731Szbb struct ena_admin_acq_common_desc acq_common_desc; 367320731Szbb 368320731Szbb uint16_t cq_idx; 369320731Szbb 370320731Szbb /* actual cq depth in number of entries */ 371320731Szbb uint16_t cq_actual_depth; 372320731Szbb 373320731Szbb uint32_t numa_node_register_offset; 374320731Szbb 375320731Szbb uint32_t cq_head_db_register_offset; 376320731Szbb 377320731Szbb uint32_t cq_interrupt_unmask_register_offset; 378320731Szbb}; 379320731Szbb 380320731Szbbstruct ena_admin_aq_destroy_cq_cmd { 381320731Szbb struct ena_admin_aq_common_desc aq_common_descriptor; 382320731Szbb 383320731Szbb uint16_t cq_idx; 384320731Szbb 385320731Szbb uint16_t reserved1; 386320731Szbb}; 387320731Szbb 388320731Szbbstruct ena_admin_acq_destroy_cq_resp_desc { 389320731Szbb struct ena_admin_acq_common_desc acq_common_desc; 390320731Szbb}; 391320731Szbb 392320731Szbb/* ENA AQ Get Statistics command. Extended statistics are placed in control 393320731Szbb * buffer pointed by AQ entry 394320731Szbb */ 395320731Szbbstruct ena_admin_aq_get_stats_cmd { 396320731Szbb struct ena_admin_aq_common_desc aq_common_descriptor; 397320731Szbb 398320731Szbb union { 399320731Szbb /* command specific inline data */ 400320731Szbb uint32_t inline_data_w1[3]; 401320731Szbb 402320731Szbb struct ena_admin_ctrl_buff_info control_buffer; 403320731Szbb } u; 404320731Szbb 405320731Szbb /* stats type as defined in enum ena_admin_get_stats_type */ 406320731Szbb uint8_t type; 407320731Szbb 408320731Szbb /* stats scope defined in enum ena_admin_get_stats_scope */ 409320731Szbb uint8_t scope; 410320731Szbb 411320731Szbb uint16_t reserved3; 412320731Szbb 413320731Szbb /* queue id. used when scope is specific_queue */ 414320731Szbb uint16_t queue_idx; 415320731Szbb 416320731Szbb /* device id, value 0xFFFF means mine. only privileged device can get 417320731Szbb * stats of other device 418320731Szbb */ 419320731Szbb uint16_t device_id; 420320731Szbb}; 421320731Szbb 422320731Szbb/* Basic Statistics Command. */ 423320731Szbbstruct ena_admin_basic_stats { 424320731Szbb uint32_t tx_bytes_low; 425320731Szbb 426320731Szbb uint32_t tx_bytes_high; 427320731Szbb 428320731Szbb uint32_t tx_pkts_low; 429320731Szbb 430320731Szbb uint32_t tx_pkts_high; 431320731Szbb 432320731Szbb uint32_t rx_bytes_low; 433320731Szbb 434320731Szbb uint32_t rx_bytes_high; 435320731Szbb 436320731Szbb uint32_t rx_pkts_low; 437320731Szbb 438320731Szbb uint32_t rx_pkts_high; 439320731Szbb 440320731Szbb uint32_t rx_drops_low; 441320731Szbb 442320731Szbb uint32_t rx_drops_high; 443320731Szbb}; 444320731Szbb 445320731Szbbstruct ena_admin_acq_get_stats_resp { 446320731Szbb struct ena_admin_acq_common_desc acq_common_desc; 447320731Szbb 448320731Szbb struct ena_admin_basic_stats basic_stats; 449320731Szbb}; 450320731Szbb 451320731Szbbstruct ena_admin_get_set_feature_common_desc { 452320731Szbb /* 1:0 : select - 0x1 - current value; 0x3 - default 453320731Szbb * value 454320731Szbb * 7:3 : reserved3 455320731Szbb */ 456320731Szbb uint8_t flags; 457320731Szbb 458320731Szbb /* as appears in ena_admin_aq_feature_id */ 459320731Szbb uint8_t feature_id; 460320731Szbb 461320731Szbb uint16_t reserved16; 462320731Szbb}; 463320731Szbb 464320731Szbbstruct ena_admin_device_attr_feature_desc { 465320731Szbb uint32_t impl_id; 466320731Szbb 467320731Szbb uint32_t device_version; 468320731Szbb 469320731Szbb /* bitmap of ena_admin_aq_feature_id */ 470320731Szbb uint32_t supported_features; 471320731Szbb 472320731Szbb uint32_t reserved3; 473320731Szbb 474320731Szbb /* Indicates how many bits are used physical address access. */ 475320731Szbb uint32_t phys_addr_width; 476320731Szbb 477320731Szbb /* Indicates how many bits are used virtual address access. */ 478320731Szbb uint32_t virt_addr_width; 479320731Szbb 480320731Szbb /* unicast MAC address (in Network byte order) */ 481320731Szbb uint8_t mac_addr[6]; 482320731Szbb 483320731Szbb uint8_t reserved7[2]; 484320731Szbb 485320731Szbb uint32_t max_mtu; 486320731Szbb}; 487320731Szbb 488320731Szbbstruct ena_admin_queue_feature_desc { 489320731Szbb /* including LLQs */ 490320731Szbb uint32_t max_sq_num; 491320731Szbb 492320731Szbb uint32_t max_sq_depth; 493320731Szbb 494320731Szbb uint32_t max_cq_num; 495320731Szbb 496320731Szbb uint32_t max_cq_depth; 497320731Szbb 498320731Szbb uint32_t max_llq_num; 499320731Szbb 500320731Szbb uint32_t max_llq_depth; 501320731Szbb 502320731Szbb uint32_t max_header_size; 503320731Szbb 504320731Szbb /* Maximum Descriptors number, including meta descriptor, allowed for 505320731Szbb * a single Tx packet 506320731Szbb */ 507320731Szbb uint16_t max_packet_tx_descs; 508320731Szbb 509320731Szbb /* Maximum Descriptors number allowed for a single Rx packet */ 510320731Szbb uint16_t max_packet_rx_descs; 511320731Szbb}; 512320731Szbb 513320731Szbbstruct ena_admin_set_feature_mtu_desc { 514320731Szbb /* exclude L2 */ 515320731Szbb uint32_t mtu; 516320731Szbb}; 517320731Szbb 518320731Szbbstruct ena_admin_set_feature_host_attr_desc { 519320731Szbb /* host OS info base address in OS memory. host info is 4KB of 520320731Szbb * physically contiguous 521320731Szbb */ 522320731Szbb struct ena_common_mem_addr os_info_ba; 523320731Szbb 524320731Szbb /* host debug area base address in OS memory. debug area must be 525320731Szbb * physically contiguous 526320731Szbb */ 527320731Szbb struct ena_common_mem_addr debug_ba; 528320731Szbb 529320731Szbb /* debug area size */ 530320731Szbb uint32_t debug_area_size; 531320731Szbb}; 532320731Szbb 533320731Szbbstruct ena_admin_feature_intr_moder_desc { 534320731Szbb /* interrupt delay granularity in usec */ 535320731Szbb uint16_t intr_delay_resolution; 536320731Szbb 537320731Szbb uint16_t reserved; 538320731Szbb}; 539320731Szbb 540320731Szbbstruct ena_admin_get_feature_link_desc { 541320731Szbb /* Link speed in Mb */ 542320731Szbb uint32_t speed; 543320731Szbb 544320731Szbb /* bit field of enum ena_admin_link types */ 545320731Szbb uint32_t supported; 546320731Szbb 547320731Szbb /* 0 : autoneg 548320731Szbb * 1 : duplex - Full Duplex 549320731Szbb * 31:2 : reserved2 550320731Szbb */ 551320731Szbb uint32_t flags; 552320731Szbb}; 553320731Szbb 554320731Szbbstruct ena_admin_feature_aenq_desc { 555320731Szbb /* bitmask for AENQ groups the device can report */ 556320731Szbb uint32_t supported_groups; 557320731Szbb 558320731Szbb /* bitmask for AENQ groups to report */ 559320731Szbb uint32_t enabled_groups; 560320731Szbb}; 561320731Szbb 562320731Szbbstruct ena_admin_feature_offload_desc { 563320731Szbb /* 0 : TX_L3_csum_ipv4 564320731Szbb * 1 : TX_L4_ipv4_csum_part - The checksum field 565320731Szbb * should be initialized with pseudo header checksum 566320731Szbb * 2 : TX_L4_ipv4_csum_full 567320731Szbb * 3 : TX_L4_ipv6_csum_part - The checksum field 568320731Szbb * should be initialized with pseudo header checksum 569320731Szbb * 4 : TX_L4_ipv6_csum_full 570320731Szbb * 5 : tso_ipv4 571320731Szbb * 6 : tso_ipv6 572320731Szbb * 7 : tso_ecn 573320731Szbb */ 574320731Szbb uint32_t tx; 575320731Szbb 576320731Szbb /* Receive side supported stateless offload 577320731Szbb * 0 : RX_L3_csum_ipv4 - IPv4 checksum 578320731Szbb * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 579320731Szbb * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 580320731Szbb * 3 : RX_hash - Hash calculation 581320731Szbb */ 582320731Szbb uint32_t rx_supported; 583320731Szbb 584320731Szbb uint32_t rx_enabled; 585320731Szbb}; 586320731Szbb 587320731Szbbenum ena_admin_hash_functions { 588320731Szbb ENA_ADMIN_TOEPLITZ = 1, 589320731Szbb 590320731Szbb ENA_ADMIN_CRC32 = 2, 591320731Szbb}; 592320731Szbb 593320731Szbbstruct ena_admin_feature_rss_flow_hash_control { 594320731Szbb uint32_t keys_num; 595320731Szbb 596320731Szbb uint32_t reserved; 597320731Szbb 598320731Szbb uint32_t key[10]; 599320731Szbb}; 600320731Szbb 601320731Szbbstruct ena_admin_feature_rss_flow_hash_function { 602320731Szbb /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 603320731Szbb uint32_t supported_func; 604320731Szbb 605320731Szbb /* 7:0 : selected_func - bitmask of 606320731Szbb * ena_admin_hash_functions 607320731Szbb */ 608320731Szbb uint32_t selected_func; 609320731Szbb 610320731Szbb /* initial value */ 611320731Szbb uint32_t init_val; 612320731Szbb}; 613320731Szbb 614320731Szbb/* RSS flow hash protocols */ 615320731Szbbenum ena_admin_flow_hash_proto { 616320731Szbb ENA_ADMIN_RSS_TCP4 = 0, 617320731Szbb 618320731Szbb ENA_ADMIN_RSS_UDP4 = 1, 619320731Szbb 620320731Szbb ENA_ADMIN_RSS_TCP6 = 2, 621320731Szbb 622320731Szbb ENA_ADMIN_RSS_UDP6 = 3, 623320731Szbb 624320731Szbb ENA_ADMIN_RSS_IP4 = 4, 625320731Szbb 626320731Szbb ENA_ADMIN_RSS_IP6 = 5, 627320731Szbb 628320731Szbb ENA_ADMIN_RSS_IP4_FRAG = 6, 629320731Szbb 630320731Szbb ENA_ADMIN_RSS_NOT_IP = 7, 631320731Szbb 632320731Szbb /* TCPv6 with extension header */ 633320731Szbb ENA_ADMIN_RSS_TCP6_EX = 8, 634320731Szbb 635320731Szbb /* IPv6 with extension header */ 636320731Szbb ENA_ADMIN_RSS_IP6_EX = 9, 637320731Szbb 638320731Szbb ENA_ADMIN_RSS_PROTO_NUM = 16, 639320731Szbb}; 640320731Szbb 641320731Szbb/* RSS flow hash fields */ 642320731Szbbenum ena_admin_flow_hash_fields { 643320731Szbb /* Ethernet Dest Addr */ 644320731Szbb ENA_ADMIN_RSS_L2_DA = BIT(0), 645320731Szbb 646320731Szbb /* Ethernet Src Addr */ 647320731Szbb ENA_ADMIN_RSS_L2_SA = BIT(1), 648320731Szbb 649320731Szbb /* ipv4/6 Dest Addr */ 650320731Szbb ENA_ADMIN_RSS_L3_DA = BIT(2), 651320731Szbb 652320731Szbb /* ipv4/6 Src Addr */ 653320731Szbb ENA_ADMIN_RSS_L3_SA = BIT(3), 654320731Szbb 655320731Szbb /* tcp/udp Dest Port */ 656320731Szbb ENA_ADMIN_RSS_L4_DP = BIT(4), 657320731Szbb 658320731Szbb /* tcp/udp Src Port */ 659320731Szbb ENA_ADMIN_RSS_L4_SP = BIT(5), 660320731Szbb}; 661320731Szbb 662320731Szbbstruct ena_admin_proto_input { 663320731Szbb /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 664320731Szbb uint16_t fields; 665320731Szbb 666320731Szbb uint16_t reserved2; 667320731Szbb}; 668320731Szbb 669320731Szbbstruct ena_admin_feature_rss_hash_control { 670320731Szbb struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 671320731Szbb 672320731Szbb struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 673320731Szbb 674320731Szbb struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 675320731Szbb 676320731Szbb struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 677320731Szbb}; 678320731Szbb 679320731Szbbstruct ena_admin_feature_rss_flow_hash_input { 680320731Szbb /* supported hash input sorting 681320731Szbb * 1 : L3_sort - support swap L3 addresses if DA is 682320731Szbb * smaller than SA 683320731Szbb * 2 : L4_sort - support swap L4 ports if DP smaller 684320731Szbb * SP 685320731Szbb */ 686320731Szbb uint16_t supported_input_sort; 687320731Szbb 688320731Szbb /* enabled hash input sorting 689320731Szbb * 1 : enable_L3_sort - enable swap L3 addresses if 690320731Szbb * DA smaller than SA 691320731Szbb * 2 : enable_L4_sort - enable swap L4 ports if DP 692320731Szbb * smaller than SP 693320731Szbb */ 694320731Szbb uint16_t enabled_input_sort; 695320731Szbb}; 696320731Szbb 697320731Szbbenum ena_admin_os_type { 698320731Szbb ENA_ADMIN_OS_LINUX = 1, 699320731Szbb 700320731Szbb ENA_ADMIN_OS_WIN = 2, 701320731Szbb 702320731Szbb ENA_ADMIN_OS_DPDK = 3, 703320731Szbb 704320731Szbb ENA_ADMIN_OS_FREEBSD = 4, 705320731Szbb 706320731Szbb ENA_ADMIN_OS_IPXE = 5, 707320731Szbb}; 708320731Szbb 709320731Szbbstruct ena_admin_host_info { 710320731Szbb /* defined in enum ena_admin_os_type */ 711320731Szbb uint32_t os_type; 712320731Szbb 713320731Szbb /* os distribution string format */ 714320731Szbb uint8_t os_dist_str[128]; 715320731Szbb 716320731Szbb /* OS distribution numeric format */ 717320731Szbb uint32_t os_dist; 718320731Szbb 719320731Szbb /* kernel version string format */ 720320731Szbb uint8_t kernel_ver_str[32]; 721320731Szbb 722320731Szbb /* Kernel version numeric format */ 723320731Szbb uint32_t kernel_ver; 724320731Szbb 725320731Szbb /* 7:0 : major 726320731Szbb * 15:8 : minor 727320731Szbb * 23:16 : sub_minor 728320731Szbb */ 729320731Szbb uint32_t driver_version; 730320731Szbb 731320731Szbb /* features bitmap */ 732320731Szbb uint32_t supported_network_features[4]; 733320731Szbb}; 734320731Szbb 735320731Szbbstruct ena_admin_rss_ind_table_entry { 736320731Szbb uint16_t cq_idx; 737320731Szbb 738320731Szbb uint16_t reserved; 739320731Szbb}; 740320731Szbb 741320731Szbbstruct ena_admin_feature_rss_ind_table { 742320731Szbb /* min supported table size (2^min_size) */ 743320731Szbb uint16_t min_size; 744320731Szbb 745320731Szbb /* max supported table size (2^max_size) */ 746320731Szbb uint16_t max_size; 747320731Szbb 748320731Szbb /* table size (2^size) */ 749320731Szbb uint16_t size; 750320731Szbb 751320731Szbb uint16_t reserved; 752320731Szbb 753320731Szbb /* index of the inline entry. 0xFFFFFFFF means invalid */ 754320731Szbb uint32_t inline_index; 755320731Szbb 756320731Szbb /* used for updating single entry, ignored when setting the entire 757320731Szbb * table through the control buffer. 758320731Szbb */ 759320731Szbb struct ena_admin_rss_ind_table_entry inline_entry; 760320731Szbb}; 761320731Szbb 762320731Szbb/* When hint value is 0, driver should use it's own predefined value */ 763320731Szbbstruct ena_admin_ena_hw_hints { 764320731Szbb /* value in ms */ 765320731Szbb uint16_t mmio_read_timeout; 766320731Szbb 767320731Szbb /* value in ms */ 768320731Szbb uint16_t driver_watchdog_timeout; 769320731Szbb 770320731Szbb /* Per packet tx completion timeout. value in ms */ 771320731Szbb uint16_t missing_tx_completion_timeout; 772320731Szbb 773320731Szbb uint16_t missed_tx_completion_count_threshold_to_reset; 774320731Szbb 775320731Szbb /* value in ms */ 776320731Szbb uint16_t admin_completion_tx_timeout; 777320731Szbb 778320731Szbb uint16_t netdev_wd_timeout; 779320731Szbb 780320731Szbb uint16_t max_tx_sgl_size; 781320731Szbb 782320731Szbb uint16_t max_rx_sgl_size; 783320731Szbb 784320731Szbb uint16_t reserved[8]; 785320731Szbb}; 786320731Szbb 787320731Szbbstruct ena_admin_get_feat_cmd { 788320731Szbb struct ena_admin_aq_common_desc aq_common_descriptor; 789320731Szbb 790320731Szbb struct ena_admin_ctrl_buff_info control_buffer; 791320731Szbb 792320731Szbb struct ena_admin_get_set_feature_common_desc feat_common; 793320731Szbb 794320731Szbb uint32_t raw[11]; 795320731Szbb}; 796320731Szbb 797320731Szbbstruct ena_admin_get_feat_resp { 798320731Szbb struct ena_admin_acq_common_desc acq_common_desc; 799320731Szbb 800320731Szbb union { 801320731Szbb uint32_t raw[14]; 802320731Szbb 803320731Szbb struct ena_admin_device_attr_feature_desc dev_attr; 804320731Szbb 805320731Szbb struct ena_admin_queue_feature_desc max_queue; 806320731Szbb 807320731Szbb struct ena_admin_feature_aenq_desc aenq; 808320731Szbb 809320731Szbb struct ena_admin_get_feature_link_desc link; 810320731Szbb 811320731Szbb struct ena_admin_feature_offload_desc offload; 812320731Szbb 813320731Szbb struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 814320731Szbb 815320731Szbb struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 816320731Szbb 817320731Szbb struct ena_admin_feature_rss_ind_table ind_table; 818320731Szbb 819320731Szbb struct ena_admin_feature_intr_moder_desc intr_moderation; 820320731Szbb 821320731Szbb struct ena_admin_ena_hw_hints hw_hints; 822320731Szbb } u; 823320731Szbb}; 824320731Szbb 825320731Szbbstruct ena_admin_set_feat_cmd { 826320731Szbb struct ena_admin_aq_common_desc aq_common_descriptor; 827320731Szbb 828320731Szbb struct ena_admin_ctrl_buff_info control_buffer; 829320731Szbb 830320731Szbb struct ena_admin_get_set_feature_common_desc feat_common; 831320731Szbb 832320731Szbb union { 833320731Szbb uint32_t raw[11]; 834320731Szbb 835320731Szbb /* mtu size */ 836320731Szbb struct ena_admin_set_feature_mtu_desc mtu; 837320731Szbb 838320731Szbb /* host attributes */ 839320731Szbb struct ena_admin_set_feature_host_attr_desc host_attr; 840320731Szbb 841320731Szbb /* AENQ configuration */ 842320731Szbb struct ena_admin_feature_aenq_desc aenq; 843320731Szbb 844320731Szbb /* rss flow hash function */ 845320731Szbb struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 846320731Szbb 847320731Szbb /* rss flow hash input */ 848320731Szbb struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 849320731Szbb 850320731Szbb /* rss indirection table */ 851320731Szbb struct ena_admin_feature_rss_ind_table ind_table; 852320731Szbb } u; 853320731Szbb}; 854320731Szbb 855320731Szbbstruct ena_admin_set_feat_resp { 856320731Szbb struct ena_admin_acq_common_desc acq_common_desc; 857320731Szbb 858320731Szbb union { 859320731Szbb uint32_t raw[14]; 860320731Szbb } u; 861320731Szbb}; 862320731Szbb 863320731Szbbstruct ena_admin_aenq_common_desc { 864320731Szbb uint16_t group; 865320731Szbb 866320731Szbb uint16_t syndrom; 867320731Szbb 868320731Szbb /* 0 : phase */ 869320731Szbb uint8_t flags; 870320731Szbb 871320731Szbb uint8_t reserved1[3]; 872320731Szbb 873320731Szbb uint32_t timestamp_low; 874320731Szbb 875320731Szbb uint32_t timestamp_high; 876320731Szbb}; 877320731Szbb 878320731Szbb/* asynchronous event notification groups */ 879320731Szbbenum ena_admin_aenq_group { 880320731Szbb ENA_ADMIN_LINK_CHANGE = 0, 881320731Szbb 882320731Szbb ENA_ADMIN_FATAL_ERROR = 1, 883320731Szbb 884320731Szbb ENA_ADMIN_WARNING = 2, 885320731Szbb 886320731Szbb ENA_ADMIN_NOTIFICATION = 3, 887320731Szbb 888320731Szbb ENA_ADMIN_KEEP_ALIVE = 4, 889320731Szbb 890320731Szbb ENA_ADMIN_AENQ_GROUPS_NUM = 5, 891320731Szbb}; 892320731Szbb 893320731Szbbenum ena_admin_aenq_notification_syndrom { 894320731Szbb ENA_ADMIN_SUSPEND = 0, 895320731Szbb 896320731Szbb ENA_ADMIN_RESUME = 1, 897320731Szbb 898320731Szbb ENA_ADMIN_UPDATE_HINTS = 2, 899320731Szbb}; 900320731Szbb 901320731Szbbstruct ena_admin_aenq_entry { 902320731Szbb struct ena_admin_aenq_common_desc aenq_common_desc; 903320731Szbb 904320731Szbb /* command specific inline data */ 905320731Szbb uint32_t inline_data_w4[12]; 906320731Szbb}; 907320731Szbb 908320731Szbbstruct ena_admin_aenq_link_change_desc { 909320731Szbb struct ena_admin_aenq_common_desc aenq_common_desc; 910320731Szbb 911320731Szbb /* 0 : link_status */ 912320731Szbb uint32_t flags; 913320731Szbb}; 914320731Szbb 915320731Szbbstruct ena_admin_aenq_keep_alive_desc { 916320731Szbb struct ena_admin_aenq_common_desc aenq_common_desc; 917320731Szbb 918320731Szbb uint32_t rx_drops_low; 919320731Szbb 920320731Szbb uint32_t rx_drops_high; 921320731Szbb}; 922320731Szbb 923320731Szbbstruct ena_admin_ena_mmio_req_read_less_resp { 924320731Szbb uint16_t req_id; 925320731Szbb 926320731Szbb uint16_t reg_off; 927320731Szbb 928320731Szbb /* value is valid when poll is cleared */ 929320731Szbb uint32_t reg_val; 930320731Szbb}; 931320731Szbb 932320731Szbb/* aq_common_desc */ 933320731Szbb#define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 934320731Szbb#define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 935320731Szbb#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 936320731Szbb#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 937320731Szbb#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 938320731Szbb#define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 939320731Szbb 940320731Szbb/* sq */ 941320731Szbb#define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 942320731Szbb#define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 943320731Szbb 944320731Szbb/* acq_common_desc */ 945320731Szbb#define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 946320731Szbb#define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 947320731Szbb 948320731Szbb/* aq_create_sq_cmd */ 949320731Szbb#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 950320731Szbb#define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 951320731Szbb#define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 952320731Szbb#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 953320731Szbb#define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 954320731Szbb#define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 955320731Szbb 956320731Szbb/* aq_create_cq_cmd */ 957320731Szbb#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 958320731Szbb#define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 959320731Szbb#define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 960320731Szbb 961320731Szbb/* get_set_feature_common_desc */ 962320731Szbb#define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 963320731Szbb 964320731Szbb/* get_feature_link_desc */ 965320731Szbb#define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 966320731Szbb#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 967320731Szbb#define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 968320731Szbb 969320731Szbb/* feature_offload_desc */ 970320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 971320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 972320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 973320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 974320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 975320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 976320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 977320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 978320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 979320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 980320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 981320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 982320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 983320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 984320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 985320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 986320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 987320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 988320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 989320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 990320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 991320731Szbb#define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 992320731Szbb 993320731Szbb/* feature_rss_flow_hash_function */ 994320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 995320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 996320731Szbb 997320731Szbb/* feature_rss_flow_hash_input */ 998320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 999320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1000320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1001320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1002320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1003320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1004320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1005320731Szbb#define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1006320731Szbb 1007320731Szbb/* host_info */ 1008320731Szbb#define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1009320731Szbb#define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1010320731Szbb#define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1011320731Szbb#define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1012320731Szbb#define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1013320731Szbb 1014320731Szbb/* aenq_common_desc */ 1015320731Szbb#define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1016320731Szbb 1017320731Szbb/* aenq_link_change_desc */ 1018320731Szbb#define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1019320731Szbb 1020320731Szbb#if !defined(ENA_DEFS_LINUX_MAINLINE) 1021320731Szbbstatic inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p) 1022320731Szbb{ 1023320731Szbb return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 1024320731Szbb} 1025320731Szbb 1026320731Szbbstatic inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val) 1027320731Szbb{ 1028320731Szbb p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 1029320731Szbb} 1030320731Szbb 1031320731Szbbstatic inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p) 1032320731Szbb{ 1033320731Szbb return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 1034320731Szbb} 1035320731Szbb 1036320731Szbbstatic inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val) 1037320731Szbb{ 1038320731Szbb p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 1039320731Szbb} 1040320731Szbb 1041320731Szbbstatic inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p) 1042320731Szbb{ 1043320731Szbb return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT; 1044320731Szbb} 1045320731Szbb 1046320731Szbbstatic inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val) 1047320731Szbb{ 1048320731Szbb p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK; 1049320731Szbb} 1050320731Szbb 1051320731Szbbstatic inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p) 1052320731Szbb{ 1053320731Szbb return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT; 1054320731Szbb} 1055320731Szbb 1056320731Szbbstatic inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val) 1057320731Szbb{ 1058320731Szbb p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 1059320731Szbb} 1060320731Szbb 1061320731Szbbstatic inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p) 1062320731Szbb{ 1063320731Szbb return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT; 1064320731Szbb} 1065320731Szbb 1066320731Szbbstatic inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val) 1067320731Szbb{ 1068320731Szbb p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 1069320731Szbb} 1070320731Szbb 1071320731Szbbstatic inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p) 1072320731Szbb{ 1073320731Szbb return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 1074320731Szbb} 1075320731Szbb 1076320731Szbbstatic inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val) 1077320731Szbb{ 1078320731Szbb p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 1079320731Szbb} 1080320731Szbb 1081320731Szbbstatic inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p) 1082320731Szbb{ 1083320731Szbb return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; 1084320731Szbb} 1085320731Szbb 1086320731Szbbstatic inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val) 1087320731Szbb{ 1088320731Szbb p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; 1089320731Szbb} 1090320731Szbb 1091320731Szbbstatic inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p) 1092320731Szbb{ 1093320731Szbb return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT; 1094320731Szbb} 1095320731Szbb 1096320731Szbbstatic inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1097320731Szbb{ 1098320731Szbb p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1099320731Szbb} 1100320731Szbb 1101320731Szbbstatic inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p) 1102320731Szbb{ 1103320731Szbb return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1104320731Szbb} 1105320731Szbb 1106320731Szbbstatic inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1107320731Szbb{ 1108320731Szbb p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1109320731Szbb} 1110320731Szbb 1111320731Szbbstatic inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p) 1112320731Szbb{ 1113320731Szbb return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT; 1114320731Szbb} 1115320731Szbb 1116320731Szbbstatic inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1117320731Szbb{ 1118320731Szbb p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1119320731Szbb} 1120320731Szbb 1121320731Szbbstatic inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p) 1122320731Szbb{ 1123320731Szbb return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1124320731Szbb} 1125320731Szbb 1126320731Szbbstatic inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1127320731Szbb{ 1128320731Szbb p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1129320731Szbb} 1130320731Szbb 1131320731Szbbstatic inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p) 1132320731Szbb{ 1133320731Szbb return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT; 1134320731Szbb} 1135320731Szbb 1136320731Szbbstatic inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val) 1137320731Szbb{ 1138320731Szbb p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1139320731Szbb} 1140320731Szbb 1141320731Szbbstatic inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p) 1142320731Szbb{ 1143320731Szbb return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1144320731Szbb} 1145320731Szbb 1146320731Szbbstatic inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val) 1147320731Szbb{ 1148320731Szbb p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1149320731Szbb} 1150320731Szbb 1151320731Szbbstatic inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p) 1152320731Szbb{ 1153320731Szbb return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; 1154320731Szbb} 1155320731Szbb 1156320731Szbbstatic inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val) 1157320731Szbb{ 1158320731Szbb p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; 1159320731Szbb} 1160320731Szbb 1161320731Szbbstatic inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p) 1162320731Szbb{ 1163320731Szbb return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; 1164320731Szbb} 1165320731Szbb 1166320731Szbbstatic inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val) 1167320731Szbb{ 1168320731Szbb p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; 1169320731Szbb} 1170320731Szbb 1171320731Szbbstatic inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p) 1172320731Szbb{ 1173320731Szbb return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT; 1174320731Szbb} 1175320731Szbb 1176320731Szbbstatic inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val) 1177320731Szbb{ 1178320731Szbb p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK; 1179320731Szbb} 1180320731Szbb 1181320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p) 1182320731Szbb{ 1183320731Szbb return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; 1184320731Szbb} 1185320731Szbb 1186320731Szbbstatic inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1187320731Szbb{ 1188320731Szbb p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; 1189320731Szbb} 1190320731Szbb 1191320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p) 1192320731Szbb{ 1193320731Szbb return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT; 1194320731Szbb} 1195320731Szbb 1196320731Szbbstatic inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val) 1197320731Szbb{ 1198320731Szbb p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK; 1199320731Szbb} 1200320731Szbb 1201320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p) 1202320731Szbb{ 1203320731Szbb return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT; 1204320731Szbb} 1205320731Szbb 1206320731Szbbstatic inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val) 1207320731Szbb{ 1208320731Szbb p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK; 1209320731Szbb} 1210320731Szbb 1211320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p) 1212320731Szbb{ 1213320731Szbb return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT; 1214320731Szbb} 1215320731Szbb 1216320731Szbbstatic inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val) 1217320731Szbb{ 1218320731Szbb p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK; 1219320731Szbb} 1220320731Szbb 1221320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p) 1222320731Szbb{ 1223320731Szbb return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT; 1224320731Szbb} 1225320731Szbb 1226320731Szbbstatic inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val) 1227320731Szbb{ 1228320731Szbb p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK; 1229320731Szbb} 1230320731Szbb 1231320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p) 1232320731Szbb{ 1233320731Szbb return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT; 1234320731Szbb} 1235320731Szbb 1236320731Szbbstatic inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1237320731Szbb{ 1238320731Szbb p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK; 1239320731Szbb} 1240320731Szbb 1241320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p) 1242320731Szbb{ 1243320731Szbb return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT; 1244320731Szbb} 1245320731Szbb 1246320731Szbbstatic inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val) 1247320731Szbb{ 1248320731Szbb p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK; 1249320731Szbb} 1250320731Szbb 1251320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p) 1252320731Szbb{ 1253320731Szbb return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT; 1254320731Szbb} 1255320731Szbb 1256320731Szbbstatic inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val) 1257320731Szbb{ 1258320731Szbb p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK; 1259320731Szbb} 1260320731Szbb 1261320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p) 1262320731Szbb{ 1263320731Szbb return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK; 1264320731Szbb} 1265320731Szbb 1266320731Szbbstatic inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1267320731Szbb{ 1268320731Szbb p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK; 1269320731Szbb} 1270320731Szbb 1271320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p) 1272320731Szbb{ 1273320731Szbb return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT; 1274320731Szbb} 1275320731Szbb 1276320731Szbbstatic inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val) 1277320731Szbb{ 1278320731Szbb p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK; 1279320731Szbb} 1280320731Szbb 1281320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p) 1282320731Szbb{ 1283320731Szbb return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT; 1284320731Szbb} 1285320731Szbb 1286320731Szbbstatic inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val) 1287320731Szbb{ 1288320731Szbb p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK; 1289320731Szbb} 1290320731Szbb 1291320731Szbbstatic inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p) 1292320731Szbb{ 1293320731Szbb return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT; 1294320731Szbb} 1295320731Szbb 1296320731Szbbstatic inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val) 1297320731Szbb{ 1298320731Szbb p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK; 1299320731Szbb} 1300320731Szbb 1301320731Szbbstatic inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p) 1302320731Szbb{ 1303320731Szbb return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK; 1304320731Szbb} 1305320731Szbb 1306320731Szbbstatic inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val) 1307320731Szbb{ 1308320731Szbb p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK; 1309320731Szbb} 1310320731Szbb 1311320731Szbbstatic inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p) 1312320731Szbb{ 1313320731Szbb return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK; 1314320731Szbb} 1315320731Szbb 1316320731Szbbstatic inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val) 1317320731Szbb{ 1318320731Szbb p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK; 1319320731Szbb} 1320320731Szbb 1321320731Szbbstatic inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1322320731Szbb{ 1323320731Szbb return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT; 1324320731Szbb} 1325320731Szbb 1326320731Szbbstatic inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1327320731Szbb{ 1328320731Szbb p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK; 1329320731Szbb} 1330320731Szbb 1331320731Szbbstatic inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1332320731Szbb{ 1333320731Szbb return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT; 1334320731Szbb} 1335320731Szbb 1336320731Szbbstatic inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1337320731Szbb{ 1338320731Szbb p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 1339320731Szbb} 1340320731Szbb 1341320731Szbbstatic inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1342320731Szbb{ 1343320731Szbb return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT; 1344320731Szbb} 1345320731Szbb 1346320731Szbbstatic inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1347320731Szbb{ 1348320731Szbb p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK; 1349320731Szbb} 1350320731Szbb 1351320731Szbbstatic inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1352320731Szbb{ 1353320731Szbb return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT; 1354320731Szbb} 1355320731Szbb 1356320731Szbbstatic inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1357320731Szbb{ 1358320731Szbb p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK; 1359320731Szbb} 1360320731Szbb 1361320731Szbbstatic inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p) 1362320731Szbb{ 1363320731Szbb return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK; 1364320731Szbb} 1365320731Szbb 1366320731Szbbstatic inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val) 1367320731Szbb{ 1368320731Szbb p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK; 1369320731Szbb} 1370320731Szbb 1371320731Szbbstatic inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p) 1372320731Szbb{ 1373320731Szbb return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT; 1374320731Szbb} 1375320731Szbb 1376320731Szbbstatic inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val) 1377320731Szbb{ 1378320731Szbb p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK; 1379320731Szbb} 1380320731Szbb 1381320731Szbbstatic inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p) 1382320731Szbb{ 1383320731Szbb return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT; 1384320731Szbb} 1385320731Szbb 1386320731Szbbstatic inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val) 1387320731Szbb{ 1388320731Szbb p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK; 1389320731Szbb} 1390320731Szbb 1391320731Szbbstatic inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p) 1392320731Szbb{ 1393320731Szbb return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; 1394320731Szbb} 1395320731Szbb 1396320731Szbbstatic inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val) 1397320731Szbb{ 1398320731Szbb p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; 1399320731Szbb} 1400320731Szbb 1401320731Szbbstatic inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p) 1402320731Szbb{ 1403320731Szbb return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 1404320731Szbb} 1405320731Szbb 1406320731Szbbstatic inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val) 1407320731Szbb{ 1408320731Szbb p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 1409320731Szbb} 1410320731Szbb 1411320731Szbb#endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */ 1412320731Szbb#endif /*_ENA_ADMIN_H_ */ 1413