1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#ifndef __REG_WASP_REG_MAP_H__ 18250003Sadrian 19250003Sadrianstruct host_intf_reg_ar9340 { 20250003Sadrian volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */ 21250003Sadrian volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */ 22250003Sadrian volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */ 23250003Sadrian volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */ 24250003Sadrian volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */ 25250003Sadrian volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */ 26250003Sadrian volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */ 27250003Sadrian volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */ 28250003Sadrian volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */ 29250003Sadrian volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */ 30250003Sadrian volatile u_int32_t HOST_INTF_INTR_ASYNC_ENABLE; /* 0x4024 - 0x4028 */ 31250003Sadrian volatile u_int32_t HOST_INTF_GPIO_OUT; /* 0x4028 - 0x402c */ 32250003Sadrian volatile u_int32_t HOST_INTF_GPIO_IN; /* 0x402c - 0x4030 */ 33250003Sadrian volatile u_int32_t HOST_INTF_GPIO_OE; /* 0x4030 - 0x4034 */ 34250003Sadrian volatile u_int32_t HOST_INTF_GPIO_OE1; /* 0x4034 - 0x4038 */ 35250003Sadrian volatile u_int32_t HOST_INTF_GPIO_INTR_POLAR; /* 0x4038 - 0x403c */ 36250003Sadrian volatile u_int32_t HOST_INTF_GPIO_INPUT_VALUE; /* 0x403c - 0x4040 */ 37250003Sadrian volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX1; /* 0x4040 - 0x4044 */ 38250003Sadrian volatile u_int32_t HOST_INTF_GPIO_INPUT_MUX2; /* 0x4044 - 0x4048 */ 39250003Sadrian volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX1; /* 0x4048 - 0x404c */ 40250003Sadrian volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX2; /* 0x404c - 0x4050 */ 41250003Sadrian volatile u_int32_t HOST_INTF_GPIO_OUTPUT_MUX3; /* 0x4050 - 0x4054 */ 42250003Sadrian volatile u_int32_t HOST_INTF_GPIO_INPUT_STATE; /* 0x4054 - 0x4058 */ 43250003Sadrian volatile u_int32_t HOST_INTF_CLKRUN; /* 0x4058 - 0x405c */ 44250003Sadrian volatile u_int32_t HOST_INTF_OBS_CTRL; /* 0x405c - 0x4060 */ 45250003Sadrian volatile u_int32_t HOST_INTF_RFSILENT; /* 0x4060 - 0x4064 */ 46250003Sadrian volatile char pad__3[0x10]; /* 0x4064 - 0x4074 */ 47250003Sadrian volatile u_int32_t HOST_INTF_MISC; /* 0x4074 - 0x4078 */ 48250003Sadrian volatile u_int32_t HOST_INTF_MAC_TDMA_CCA_CNTL; /* 0x4078 - 0x407c */ 49250003Sadrian volatile u_int32_t HOST_INTF_MAC_TXAPSYNC; /* 0x407c - 0x4080 */ 50250003Sadrian volatile u_int32_t HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR; 51250003Sadrian /* 0x4080 - 0x4084 */ 52250003Sadrian volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_CAUSE; 53250003Sadrian /* 0x4084 - 0x4088 */ 54250003Sadrian volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_ENABLE; 55250003Sadrian /* 0x4088 - 0x408c */ 56250003Sadrian volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_MASK; 57250003Sadrian /* 0x408c - 0x4090 */ 58250003Sadrian volatile u_int32_t HOST_INTF_INTR_PRIORITY_SYNC_MASK; 59250003Sadrian /* 0x4090 - 0x4094 */ 60250003Sadrian volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE; 61250003Sadrian /* 0x4094 - 0x4098 */ 62250003Sadrian volatile u_int32_t HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE; 63250003Sadrian /* 0x4098 - 0x409c */ 64250003Sadrian volatile u_int32_t HOST_INTF_AXI_BYTE_SWAP; /* 0x409c - 0x40a0 */ 65250003Sadrian volatile char pad__4[0x20]; /* 0x40a4 - 0x40c4 */ 66250003Sadrian volatile u_int32_t HOST_INTF_WORK_AROUND; /* 0x40c4 - 0x40c8 */ 67250003Sadrian volatile u_int32_t HOST_INTF_EEPROM_STS; /* 0x40c8 - 0x40cc */ 68250003Sadrian volatile u_int32_t HOST_INTF_PCIE_MSI; /* 0x40d8 - 0x40dc */ 69250003Sadrian}; 70250003Sadrian 71250003Sadrian#endif /* __REG_WASP_REG_MAP_H__ */ 72