1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian 18250003Sadrian /* Contains descriptor definitions for Osprey */ 19250003Sadrian 20250003Sadrian 21250003Sadrian#ifndef _ATH_AR9300_DESC_H_ 22250003Sadrian#define _ATH_AR9300_DESC_H_ 23250003Sadrian 24250008Sadrian#ifdef _KERNEL 25250008Sadrian#include "ar9300_freebsd_inc.h" 26250008Sadrian#endif 27250003Sadrian 28250003Sadrian/* Osprey Status Descriptor. */ 29250003Sadrianstruct ar9300_txs { 30250003Sadrian u_int32_t ds_info; 31250003Sadrian u_int32_t status1; 32250003Sadrian u_int32_t status2; 33250003Sadrian u_int32_t status3; 34250003Sadrian u_int32_t status4; 35250003Sadrian u_int32_t status5; 36250003Sadrian u_int32_t status6; 37250003Sadrian u_int32_t status7; 38250003Sadrian u_int32_t status8; 39250003Sadrian}; 40250003Sadrian 41250003Sadrianstruct ar9300_rxs { 42250003Sadrian u_int32_t ds_info; 43250003Sadrian u_int32_t status1; 44250003Sadrian u_int32_t status2; 45250003Sadrian u_int32_t status3; 46250003Sadrian u_int32_t status4; 47250003Sadrian u_int32_t status5; 48250003Sadrian u_int32_t status6; 49250003Sadrian u_int32_t status7; 50250003Sadrian u_int32_t status8; 51250003Sadrian u_int32_t status9; 52250003Sadrian u_int32_t status10; 53250003Sadrian u_int32_t status11; 54250003Sadrian}; 55250003Sadrian 56250003Sadrian/* Transmit Control Descriptor */ 57250003Sadrianstruct ar9300_txc { 58250003Sadrian u_int32_t ds_info; /* descriptor information */ 59250003Sadrian u_int32_t ds_link; /* link pointer */ 60250003Sadrian u_int32_t ds_data0; /* data pointer to 1st buffer */ 61250003Sadrian u_int32_t ds_ctl3; /* DMA control 3 */ 62250003Sadrian u_int32_t ds_data1; /* data pointer to 2nd buffer */ 63250003Sadrian u_int32_t ds_ctl5; /* DMA control 5 */ 64250003Sadrian u_int32_t ds_data2; /* data pointer to 3rd buffer */ 65250003Sadrian u_int32_t ds_ctl7; /* DMA control 7 */ 66250003Sadrian u_int32_t ds_data3; /* data pointer to 4th buffer */ 67250003Sadrian u_int32_t ds_ctl9; /* DMA control 9 */ 68250003Sadrian u_int32_t ds_ctl10; /* DMA control 10 */ 69250003Sadrian u_int32_t ds_ctl11; /* DMA control 11 */ 70250003Sadrian u_int32_t ds_ctl12; /* DMA control 12 */ 71250003Sadrian u_int32_t ds_ctl13; /* DMA control 13 */ 72250003Sadrian u_int32_t ds_ctl14; /* DMA control 14 */ 73250003Sadrian u_int32_t ds_ctl15; /* DMA control 15 */ 74250003Sadrian u_int32_t ds_ctl16; /* DMA control 16 */ 75250003Sadrian u_int32_t ds_ctl17; /* DMA control 17 */ 76250003Sadrian u_int32_t ds_ctl18; /* DMA control 18 */ 77250003Sadrian u_int32_t ds_ctl19; /* DMA control 19 */ 78250003Sadrian u_int32_t ds_ctl20; /* DMA control 20 */ 79250003Sadrian u_int32_t ds_ctl21; /* DMA control 21 */ 80250003Sadrian u_int32_t ds_ctl22; /* DMA control 22 */ 81277304Sadrian u_int32_t ds_ctl23; /* DMA control 23 */ 82277304Sadrian u_int32_t ds_pad[8]; /* pad to cache line (128 bytes/32 dwords) */ 83250003Sadrian}; 84250003Sadrian 85250003Sadrian 86250003Sadrian#define AR9300RXS(_rxs) ((struct ar9300_rxs *)(_rxs)) 87250003Sadrian#define AR9300TXS(_txs) ((struct ar9300_txs *)(_txs)) 88250003Sadrian#define AR9300TXC(_ds) ((struct ar9300_txc *)(_ds)) 89250003Sadrian 90250003Sadrian#define AR9300TXC_CONST(_ds) ((const struct ar9300_txc *)(_ds)) 91250003Sadrian 92250003Sadrian 93250003Sadrian/* ds_info */ 94250003Sadrian#define AR_desc_len 0x000000ff 95250003Sadrian#define AR_rx_priority 0x00000100 96250003Sadrian#define AR_tx_qcu_num 0x00000f00 97250003Sadrian#define AR_tx_qcu_num_S 8 98250003Sadrian#define AR_ctrl_stat 0x00004000 99250003Sadrian#define AR_ctrl_stat_S 14 100250003Sadrian#define AR_tx_rx_desc 0x00008000 101250003Sadrian#define AR_tx_rx_desc_S 15 102250003Sadrian#define AR_desc_id 0xffff0000 103250003Sadrian#define AR_desc_id_S 16 104250003Sadrian 105250003Sadrian/*********** 106250003Sadrian * TX Desc * 107250003Sadrian ***********/ 108250003Sadrian 109250003Sadrian/* ds_ctl3 */ 110250003Sadrian/* ds_ctl5 */ 111250003Sadrian/* ds_ctl7 */ 112250003Sadrian/* ds_ctl9 */ 113250003Sadrian#define AR_buf_len 0x0fff0000 114250003Sadrian#define AR_buf_len_S 16 115250003Sadrian 116250003Sadrian/* ds_ctl10 */ 117250003Sadrian#define AR_tx_desc_id 0xffff0000 118250003Sadrian#define AR_tx_desc_id_S 16 119250003Sadrian#define AR_tx_ptr_chk_sum 0x0000ffff 120250003Sadrian 121250003Sadrian/* ds_ctl11 */ 122250003Sadrian#define AR_frame_len 0x00000fff 123250003Sadrian#define AR_virt_more_frag 0x00001000 124250003Sadrian#define AR_tx_ctl_rsvd00 0x00002000 125250003Sadrian#define AR_low_rx_chain 0x00004000 126250003Sadrian#define AR_tx_clear_retry 0x00008000 127250003Sadrian#define AR_xmit_power0 0x003f0000 128250003Sadrian#define AR_xmit_power0_S 16 129250003Sadrian#define AR_rts_enable 0x00400000 130250003Sadrian#define AR_veol 0x00800000 131250003Sadrian#define AR_clr_dest_mask 0x01000000 132250003Sadrian#define AR_tx_bf0 0x02000000 133250003Sadrian#define AR_tx_bf1 0x04000000 134250003Sadrian#define AR_tx_bf2 0x08000000 135250003Sadrian#define AR_tx_bf3 0x10000000 136250003Sadrian#define AR_TxBfSteered 0x1e000000 /* for tx_bf*/ 137250003Sadrian#define AR_tx_intr_req 0x20000000 138250003Sadrian#define AR_dest_idx_valid 0x40000000 139250003Sadrian#define AR_cts_enable 0x80000000 140250003Sadrian 141250003Sadrian/* ds_ctl12 */ 142250003Sadrian#define AR_tx_ctl_rsvd02 0x000001ff 143250003Sadrian#define AR_paprd_chain_mask 0x00000e00 144250003Sadrian#define AR_paprd_chain_mask_S 9 145250003Sadrian#define AR_tx_more 0x00001000 146250003Sadrian#define AR_dest_idx 0x000fe000 147250003Sadrian#define AR_dest_idx_S 13 148250003Sadrian#define AR_frame_type 0x00f00000 149250003Sadrian#define AR_frame_type_S 20 150250003Sadrian#define AR_no_ack 0x01000000 151250003Sadrian#define AR_insert_ts 0x02000000 152250003Sadrian#define AR_corrupt_fcs 0x04000000 153250003Sadrian#define AR_ext_only 0x08000000 154250003Sadrian#define AR_ext_and_ctl 0x10000000 155250003Sadrian#define AR_more_aggr 0x20000000 156250003Sadrian#define AR_is_aggr 0x40000000 157250003Sadrian#define AR_more_rifs 0x80000000 158250003Sadrian#define AR_loc_mode 0x00000100 /* Positioning bit in TX desc */ 159250003Sadrian 160250003Sadrian/* ds_ctl13 */ 161250003Sadrian#define AR_burst_dur 0x00007fff 162250003Sadrian#define AR_burst_dur_S 0 163250003Sadrian#define AR_dur_update_ena 0x00008000 164250003Sadrian#define AR_xmit_data_tries0 0x000f0000 165250003Sadrian#define AR_xmit_data_tries0_S 16 166250003Sadrian#define AR_xmit_data_tries1 0x00f00000 167250003Sadrian#define AR_xmit_data_tries1_S 20 168250003Sadrian#define AR_xmit_data_tries2 0x0f000000 169250003Sadrian#define AR_xmit_data_tries2_S 24 170250003Sadrian#define AR_xmit_data_tries3 0xf0000000 171250003Sadrian#define AR_xmit_data_tries3_S 28 172250003Sadrian 173250003Sadrian/* ds_ctl14 */ 174250003Sadrian#define AR_xmit_rate0 0x000000ff 175250003Sadrian#define AR_xmit_rate0_S 0 176250003Sadrian#define AR_xmit_rate1 0x0000ff00 177250003Sadrian#define AR_xmit_rate1_S 8 178250003Sadrian#define AR_xmit_rate2 0x00ff0000 179250003Sadrian#define AR_xmit_rate2_S 16 180250003Sadrian#define AR_xmit_rate3 0xff000000 181250003Sadrian#define AR_xmit_rate3_S 24 182250003Sadrian 183250003Sadrian/* ds_ctl15 */ 184250003Sadrian#define AR_packet_dur0 0x00007fff 185250003Sadrian#define AR_packet_dur0_S 0 186250003Sadrian#define AR_rts_cts_qual0 0x00008000 187250003Sadrian#define AR_packet_dur1 0x7fff0000 188250003Sadrian#define AR_packet_dur1_S 16 189250003Sadrian#define AR_rts_cts_qual1 0x80000000 190250003Sadrian 191250003Sadrian/* ds_ctl16 */ 192250003Sadrian#define AR_packet_dur2 0x00007fff 193250003Sadrian#define AR_packet_dur2_S 0 194250003Sadrian#define AR_rts_cts_qual2 0x00008000 195250003Sadrian#define AR_packet_dur3 0x7fff0000 196250003Sadrian#define AR_packet_dur3_S 16 197250003Sadrian#define AR_rts_cts_qual3 0x80000000 198250003Sadrian 199250003Sadrian/* ds_ctl17 */ 200250003Sadrian#define AR_aggr_len 0x0000ffff 201250003Sadrian#define AR_aggr_len_S 0 202250003Sadrian#define AR_tx_ctl_rsvd60 0x00030000 203250003Sadrian#define AR_pad_delim 0x03fc0000 204250003Sadrian#define AR_pad_delim_S 18 205250003Sadrian#define AR_encr_type 0x1c000000 206250003Sadrian#define AR_encr_type_S 26 207250003Sadrian#define AR_tx_dc_ap_sta_sel 0x40000000 208250003Sadrian#define AR_tx_ctl_rsvd61 0xc0000000 209250003Sadrian#define AR_calibrating 0x40000000 210250003Sadrian#define AR_ldpc 0x80000000 211250003Sadrian 212250003Sadrian/* ds_ctl18 */ 213250003Sadrian#define AR_2040_0 0x00000001 214250003Sadrian#define AR_gi0 0x00000002 215250003Sadrian#define AR_chain_sel0 0x0000001c 216250003Sadrian#define AR_chain_sel0_S 2 217250003Sadrian#define AR_2040_1 0x00000020 218250003Sadrian#define AR_gi1 0x00000040 219250003Sadrian#define AR_chain_sel1 0x00000380 220250003Sadrian#define AR_chain_sel1_S 7 221250003Sadrian#define AR_2040_2 0x00000400 222250003Sadrian#define AR_gi2 0x00000800 223250003Sadrian#define AR_chain_sel2 0x00007000 224250003Sadrian#define AR_chain_sel2_S 12 225250003Sadrian#define AR_2040_3 0x00008000 226250003Sadrian#define AR_gi3 0x00010000 227250003Sadrian#define AR_chain_sel3 0x000e0000 228250003Sadrian#define AR_chain_sel3_S 17 229250003Sadrian#define AR_rts_cts_rate 0x0ff00000 230250003Sadrian#define AR_rts_cts_rate_S 20 231250003Sadrian#define AR_stbc0 0x10000000 232250003Sadrian#define AR_stbc1 0x20000000 233250003Sadrian#define AR_stbc2 0x40000000 234250003Sadrian#define AR_stbc3 0x80000000 235250003Sadrian 236250003Sadrian/* ds_ctl19 */ 237250003Sadrian#define AR_tx_ant0 0x00ffffff 238250003Sadrian#define AR_tx_ant_sel0 0x80000000 239250003Sadrian#define AR_RTS_HTC_TRQ 0x10000000 /* bit 28 for rts_htc_TRQ*/ /*for tx_bf*/ 240250003Sadrian#define AR_not_sounding 0x20000000 241250003Sadrian#define AR_ness 0xc0000000 242250003Sadrian#define AR_ness_S 30 243250003Sadrian 244250003Sadrian/* ds_ctl20 */ 245250003Sadrian#define AR_tx_ant1 0x00ffffff 246250003Sadrian#define AR_xmit_power1 0x3f000000 247250003Sadrian#define AR_xmit_power1_S 24 248250003Sadrian#define AR_tx_ant_sel1 0x80000000 249250003Sadrian#define AR_ness1 0xc0000000 250250003Sadrian#define AR_ness1_S 30 251250003Sadrian 252250003Sadrian/* ds_ctl21 */ 253250003Sadrian#define AR_tx_ant2 0x00ffffff 254250003Sadrian#define AR_xmit_power2 0x3f000000 255250003Sadrian#define AR_xmit_power2_S 24 256250003Sadrian#define AR_tx_ant_sel2 0x80000000 257250003Sadrian#define AR_ness2 0xc0000000 258250003Sadrian#define AR_ness2_S 30 259250003Sadrian 260250003Sadrian/* ds_ctl22 */ 261250003Sadrian#define AR_tx_ant3 0x00ffffff 262250003Sadrian#define AR_xmit_power3 0x3f000000 263250003Sadrian#define AR_xmit_power3_S 24 264250003Sadrian#define AR_tx_ant_sel3 0x80000000 265250003Sadrian#define AR_ness3 0xc0000000 266250003Sadrian#define AR_ness3_S 30 267250003Sadrian 268250003Sadrian/************* 269250003Sadrian * TX Status * 270250003Sadrian *************/ 271250003Sadrian 272250003Sadrian/* ds_status1 */ 273250003Sadrian#define AR_tx_status_rsvd 0x0000ffff 274250003Sadrian 275250003Sadrian/* ds_status2 */ 276250003Sadrian#define AR_tx_rssi_ant00 0x000000ff 277250003Sadrian#define AR_tx_rssi_ant00_S 0 278250003Sadrian#define AR_tx_rssi_ant01 0x0000ff00 279250003Sadrian#define AR_tx_rssi_ant01_S 8 280250003Sadrian#define AR_tx_rssi_ant02 0x00ff0000 281250003Sadrian#define AR_tx_rssi_ant02_S 16 282250003Sadrian#define AR_tx_status_rsvd00 0x3f000000 283250003Sadrian#define AR_tx_ba_status 0x40000000 284250003Sadrian#define AR_tx_status_rsvd01 0x80000000 285250003Sadrian 286250003Sadrian/* ds_status3 */ 287250003Sadrian#define AR_frm_xmit_ok 0x00000001 288250003Sadrian#define AR_excessive_retries 0x00000002 289250003Sadrian#define AR_fifounderrun 0x00000004 290250003Sadrian#define AR_filtered 0x00000008 291250003Sadrian#define AR_rts_fail_cnt 0x000000f0 292250003Sadrian#define AR_rts_fail_cnt_S 4 293250003Sadrian#define AR_data_fail_cnt 0x00000f00 294250003Sadrian#define AR_data_fail_cnt_S 8 295250003Sadrian#define AR_virt_retry_cnt 0x0000f000 296250003Sadrian#define AR_virt_retry_cnt_S 12 297250003Sadrian#define AR_tx_delim_underrun 0x00010000 298250003Sadrian#define AR_tx_data_underrun 0x00020000 299250003Sadrian#define AR_desc_cfg_err 0x00040000 300250003Sadrian#define AR_tx_timer_expired 0x00080000 301250003Sadrian#define AR_tx_status_rsvd10 0xfff00000 302250003Sadrian 303250003Sadrian/* ds_status7 */ 304250003Sadrian#define AR_tx_rssi_ant10 0x000000ff 305250003Sadrian#define AR_tx_rssi_ant10_S 0 306250003Sadrian#define AR_tx_rssi_ant11 0x0000ff00 307250003Sadrian#define AR_tx_rssi_ant11_S 8 308250003Sadrian#define AR_tx_rssi_ant12 0x00ff0000 309250003Sadrian#define AR_tx_rssi_ant12_S 16 310250003Sadrian#define AR_tx_rssi_combined 0xff000000 311250003Sadrian#define AR_tx_rssi_combined_S 24 312250003Sadrian 313250003Sadrian/* ds_status8 */ 314250003Sadrian#define AR_tx_done 0x00000001 315250003Sadrian#define AR_seq_num 0x00001ffe 316250003Sadrian#define AR_seq_num_S 1 317250003Sadrian#define AR_tx_status_rsvd80 0x0001e000 318250003Sadrian#define AR_tx_op_exceeded 0x00020000 319250003Sadrian#define AR_tx_status_rsvd81 0x001c0000 320250003Sadrian#define AR_TXBFStatus 0x001c0000 321250003Sadrian#define AR_TXBFStatus_S 18 322250003Sadrian#define AR_tx_bf_bw_mismatch 0x00040000 323250003Sadrian#define AR_tx_bf_stream_miss 0x00080000 324250003Sadrian#define AR_final_tx_idx 0x00600000 325250003Sadrian#define AR_final_tx_idx_S 21 326250003Sadrian#define AR_tx_bf_dest_miss 0x00800000 327250003Sadrian#define AR_tx_bf_expired 0x01000000 328250003Sadrian#define AR_power_mgmt 0x02000000 329250003Sadrian#define AR_tx_status_rsvd83 0x0c000000 330250003Sadrian#define AR_tx_tid 0xf0000000 331250003Sadrian#define AR_tx_tid_S 28 332250003Sadrian#define AR_tx_fast_ts 0x08000000 /* 27th bit for locationing */ 333250003Sadrian 334250003Sadrian 335250003Sadrian/************* 336250003Sadrian * Rx Status * 337250003Sadrian *************/ 338250003Sadrian 339250003Sadrian/* ds_status1 */ 340250003Sadrian#define AR_rx_rssi_ant00 0x000000ff 341250003Sadrian#define AR_rx_rssi_ant00_S 0 342250003Sadrian#define AR_rx_rssi_ant01 0x0000ff00 343250003Sadrian#define AR_rx_rssi_ant01_S 8 344250003Sadrian#define AR_rx_rssi_ant02 0x00ff0000 345250003Sadrian#define AR_rx_rssi_ant02_S 16 346250003Sadrian#define AR_rx_rate 0xff000000 347250003Sadrian#define AR_rx_rate_S 24 348250003Sadrian 349250003Sadrian/* ds_status2 */ 350250003Sadrian#define AR_data_len 0x00000fff 351273056Ssbruno#define AR_data_len_S 0 352250003Sadrian#define AR_rx_more 0x00001000 353250003Sadrian#define AR_num_delim 0x003fc000 354250003Sadrian#define AR_num_delim_S 14 355250003Sadrian#define AR_hw_upload_data 0x00400000 356250003Sadrian#define AR_hw_upload_data_S 22 357250003Sadrian#define AR_rx_status_rsvd10 0xff800000 358250003Sadrian 359250003Sadrian 360250003Sadrian/* ds_status4 */ 361250003Sadrian#define AR_gi 0x00000001 362250003Sadrian#define AR_2040 0x00000002 363250003Sadrian#define AR_parallel40 0x00000004 364250003Sadrian#define AR_parallel40_S 2 365250003Sadrian#define AR_rx_stbc 0x00000008 366250003Sadrian#define AR_rx_not_sounding 0x00000010 367250003Sadrian#define AR_rx_ness 0x00000060 368250003Sadrian#define AR_rx_ness_S 5 369250003Sadrian#define AR_hw_upload_data_valid 0x00000080 370250003Sadrian#define AR_hw_upload_data_valid_S 7 371250003Sadrian#define AR_rx_antenna 0xffffff00 372250003Sadrian#define AR_rx_antenna_S 8 373250003Sadrian 374250003Sadrian/* ds_status5 */ 375250003Sadrian#define AR_rx_rssi_ant10 0x000000ff 376250003Sadrian#define AR_rx_rssi_ant10_S 0 377250003Sadrian#define AR_rx_rssi_ant11 0x0000ff00 378250003Sadrian#define AR_rx_rssi_ant11_S 8 379250003Sadrian#define AR_rx_rssi_ant12 0x00ff0000 380250003Sadrian#define AR_rx_rssi_ant12_S 16 381250003Sadrian#define AR_rx_rssi_combined 0xff000000 382250003Sadrian#define AR_rx_rssi_combined_S 24 383250003Sadrian 384250003Sadrian/* ds_status6 */ 385250003Sadrian#define AR_rx_evm0 status6 386250003Sadrian 387250003Sadrian/* ds_status7 */ 388250003Sadrian#define AR_rx_evm1 status7 389250003Sadrian 390250003Sadrian/* ds_status8 */ 391250003Sadrian#define AR_rx_evm2 status8 392250003Sadrian 393250003Sadrian/* ds_status9 */ 394250003Sadrian#define AR_rx_evm3 status9 395250003Sadrian 396250003Sadrian/* ds_status11 */ 397250003Sadrian#define AR_rx_done 0x00000001 398250003Sadrian#define AR_rx_frame_ok 0x00000002 399250003Sadrian#define AR_crc_err 0x00000004 400250003Sadrian#define AR_decrypt_crc_err 0x00000008 401250003Sadrian#define AR_phyerr 0x00000010 402250003Sadrian#define AR_michael_err 0x00000020 403250003Sadrian#define AR_pre_delim_crc_err 0x00000040 404250003Sadrian#define AR_apsd_trig 0x00000080 405250003Sadrian#define AR_rx_key_idx_valid 0x00000100 406250003Sadrian#define AR_key_idx 0x0000fe00 407250003Sadrian#define AR_key_idx_S 9 408250003Sadrian#define AR_phy_err_code 0x0000ff00 409250003Sadrian#define AR_phy_err_code_S 8 410250003Sadrian#define AR_rx_more_aggr 0x00010000 411250003Sadrian#define AR_rx_aggr 0x00020000 412250003Sadrian#define AR_post_delim_crc_err 0x00040000 413250003Sadrian#define AR_rx_status_rsvd71 0x01f80000 414250003Sadrian#define AR_hw_upload_data_type 0x06000000 415250003Sadrian#define AR_hw_upload_data_type_S 25 416250003Sadrian#define AR_position_bit 0x08000000 /* positioning bit */ 417250003Sadrian#define AR_hi_rx_chain 0x10000000 418250003Sadrian#define AR_rx_first_aggr 0x20000000 419250003Sadrian#define AR_decrypt_busy_err 0x40000000 420250003Sadrian#define AR_key_miss 0x80000000 421250003Sadrian 422250003Sadrian#define TXCTL_OFFSET(ah) 11 423250003Sadrian#define TXCTL_NUMWORDS(ah) 12 424250003Sadrian#define TXSTATUS_OFFSET(ah) 2 425250003Sadrian#define TXSTATUS_NUMWORDS(ah) 7 426250003Sadrian 427250003Sadrian#define RXCTL_OFFSET(ah) 0 428250003Sadrian#define RXCTL_NUMWORDS(ah) 0 429250003Sadrian#define RXSTATUS_OFFSET(ah) 1 430250003Sadrian#define RXSTATUS_NUMWORDS(ah) 11 431250003Sadrian 432250003Sadrian 433277304Sadrian#define TXC_INFO(_qcu, _desclen) (ATHEROS_VENDOR_ID << AR_desc_id_S) \ 434250003Sadrian | (1 << AR_tx_rx_desc_S) \ 435250003Sadrian | (1 << AR_ctrl_stat_S) \ 436250003Sadrian | (_qcu << AR_tx_qcu_num_S) \ 437277304Sadrian | (_desclen) 438250003Sadrian 439250003Sadrian#define VALID_KEY_TYPES \ 440250003Sadrian ((1 << HAL_KEY_TYPE_CLEAR) | (1 << HAL_KEY_TYPE_WEP)|\ 441250003Sadrian (1 << HAL_KEY_TYPE_AES) | (1 << HAL_KEY_TYPE_TKIP)) 442250003Sadrian#define is_valid_key_type(_t) ((1 << (_t)) & VALID_KEY_TYPES) 443250003Sadrian 444250003Sadrian#define set_11n_tries(_series, _index) \ 445250003Sadrian (SM((_series)[_index].Tries, AR_xmit_data_tries##_index)) 446250003Sadrian 447250003Sadrian#define set_11n_rate(_series, _index) \ 448250003Sadrian (SM((_series)[_index].Rate, AR_xmit_rate##_index)) 449250003Sadrian 450250003Sadrian#define set_11n_pkt_dur_rts_cts(_series, _index) \ 451250003Sadrian (SM((_series)[_index].PktDuration, AR_packet_dur##_index) |\ 452250003Sadrian ((_series)[_index].RateFlags & HAL_RATESERIES_RTS_CTS ?\ 453250003Sadrian AR_rts_cts_qual##_index : 0)) 454250003Sadrian 455250003Sadrian#define not_two_stream_rate(_rate) (((_rate) >0x8f) || ((_rate)<0x88)) 456250003Sadrian 457250003Sadrian#define set_11n_tx_bf_ldpc( _series) \ 458250003Sadrian ((( not_two_stream_rate((_series)[0].Rate) && (not_two_stream_rate((_series)[1].Rate)|| \ 459250003Sadrian (!(_series)[1].Tries)) && (not_two_stream_rate((_series)[2].Rate)||(!(_series)[2].Tries)) \ 460250003Sadrian && (not_two_stream_rate((_series)[3].Rate)||(!(_series)[3].Tries)))) \ 461250003Sadrian ? AR_ldpc : 0) 462250003Sadrian 463250003Sadrian#define set_11n_rate_flags(_series, _index) \ 464250003Sadrian ((_series)[_index].RateFlags & HAL_RATESERIES_2040 ? AR_2040_##_index : 0) \ 465250003Sadrian |((_series)[_index].RateFlags & HAL_RATESERIES_HALFGI ? AR_gi##_index : 0) \ 466250003Sadrian |((_series)[_index].RateFlags & HAL_RATESERIES_STBC ? AR_stbc##_index : 0) \ 467250008Sadrian |SM((_series)[_index].ChSel, AR_chain_sel##_index) 468250003Sadrian 469250003Sadrian#define set_11n_tx_power(_index, _txpower) \ 470250003Sadrian SM(_txpower, AR_xmit_power##_index) 471250003Sadrian 472250003Sadrian#define IS_3CHAIN_TX(_ah) (AH9300(_ah)->ah_tx_chainmask == 7) 473250003Sadrian/* 474250003Sadrian * Descriptor Access Functions 475250003Sadrian */ 476250003Sadrian/* XXX valid Tx rates will change for 3 stream support */ 477250003Sadrian#define VALID_PKT_TYPES \ 478250003Sadrian ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\ 479250003Sadrian (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\ 480250003Sadrian (1<<HAL_PKT_TYPE_BEACON)) 481250003Sadrian#define is_valid_pkt_type(_t) ((1<<(_t)) & VALID_PKT_TYPES) 482250003Sadrian#define VALID_TX_RATES \ 483250003Sadrian ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\ 484250003Sadrian (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\ 485250003Sadrian (1<<0x1d)|(1<<0x18)|(1<<0x1c)) 486250003Sadrian#define is_valid_tx_rate(_r) ((1<<(_r)) & VALID_TX_RATES) 487250003Sadrian 488250008Sadrian 489250008Sadrian#ifdef _KERNEL 490250003Sadrian /* TX common functions */ 491250003Sadrian 492250003Sadrianextern HAL_BOOL ar9300_update_tx_trig_level(struct ath_hal *, 493250003Sadrian HAL_BOOL IncTrigLevel); 494250003Sadrianextern u_int16_t ar9300_get_tx_trig_level(struct ath_hal *); 495250003Sadrianextern HAL_BOOL ar9300_set_tx_queue_props(struct ath_hal *ah, int q, 496250003Sadrian const HAL_TXQ_INFO *q_info); 497250003Sadrianextern HAL_BOOL ar9300_get_tx_queue_props(struct ath_hal *ah, int q, 498250003Sadrian HAL_TXQ_INFO *q_info); 499250003Sadrianextern int ar9300_setup_tx_queue(struct ath_hal *ah, HAL_TX_QUEUE type, 500250003Sadrian const HAL_TXQ_INFO *q_info); 501250003Sadrianextern HAL_BOOL ar9300_release_tx_queue(struct ath_hal *ah, u_int q); 502250003Sadrianextern HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q); 503250003Sadrianextern u_int32_t ar9300_get_tx_dp(struct ath_hal *ah, u_int q); 504250003Sadrianextern HAL_BOOL ar9300_set_tx_dp(struct ath_hal *ah, u_int q, u_int32_t txdp); 505250003Sadrianextern HAL_BOOL ar9300_start_tx_dma(struct ath_hal *ah, u_int q); 506250003Sadrianextern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q); 507250003Sadrianextern HAL_BOOL ar9300_stop_tx_dma(struct ath_hal *ah, u_int q, u_int timeout); 508250003Sadrianextern HAL_BOOL ar9300_stop_tx_dma_indv_que(struct ath_hal *ah, u_int q, u_int timeout); 509250003Sadrianextern HAL_BOOL ar9300_abort_tx_dma(struct ath_hal *ah); 510250003Sadrianextern void ar9300_get_tx_intr_queue(struct ath_hal *ah, u_int32_t *); 511250003Sadrian 512250003Sadrianextern void ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds); 513250008Sadrianextern HAL_BOOL ar9300_fill_tx_desc(struct ath_hal *ah, void *ds, HAL_DMA_ADDR *buf_addr, 514250003Sadrian u_int32_t *seg_len, u_int desc_id, u_int qcu, HAL_KEY_TYPE key_type, HAL_BOOL first_seg, 515250003Sadrian HAL_BOOL last_seg, const void *ds0); 516250003Sadrianextern void ar9300_set_desc_link(struct ath_hal *, void *ds, u_int32_t link); 517250003Sadrianextern void ar9300_get_desc_link_ptr(struct ath_hal *, void *ds, u_int32_t **link); 518250003Sadrianextern void ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds); 519250003Sadrian#ifdef ATH_SWRETRY 520250003Sadrianextern void ar9300_clear_dest_mask(struct ath_hal *ah, void *ds); 521250003Sadrian#endif 522250003Sadrianextern HAL_STATUS ar9300_proc_tx_desc(struct ath_hal *ah, void *); 523250003Sadrianextern void ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *); 524250003Sadrianextern void ar9300_get_tx_rate_code(struct ath_hal *ah, void *, struct ath_tx_status *); 525250003Sadrianextern u_int32_t ar9300_calc_tx_airtime(struct ath_hal *ah, void *, struct ath_tx_status *, 526250003Sadrian HAL_BOOL comp_wastedt, u_int8_t nbad, u_int8_t nframes); 527250003Sadrianextern void ar9300_setup_tx_status_ring(struct ath_hal *ah, void *, u_int32_t , u_int16_t); 528250003Sadrianextern void ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num); 529250003SadrianHAL_STATUS ar9300_is_tx_done(struct ath_hal *ah); 530250003Sadrianextern void ar9300_set_11n_tx_desc(struct ath_hal *ah, void *ds, 531250003Sadrian u_int pkt_len, HAL_PKT_TYPE type, u_int tx_power, 532250003Sadrian u_int key_ix, HAL_KEY_TYPE key_type, u_int flags); 533250003Sadrianextern void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask); 534250003Sadrianextern void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit); 535250003Sadrian 536250003Sadrian/* for tx_bf*/ 537250003Sadrian#define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 538250003Sadrian/* for tx_bf*/ 539250003Sadrian 540250003Sadrianextern void ar9300_set_11n_rate_scenario(struct ath_hal *ah, void *ds, 541250003Sadrian void *lastds, u_int dur_update_en, u_int rts_cts_rate, u_int rts_cts_duration, HAL_11N_RATE_SERIES series[], 542250003Sadrian u_int nseries, u_int flags, u_int32_t smartAntenna); 543250008Sadrianextern void ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, 544250008Sadrian u_int aggr_len, u_int num_delims); 545250008Sadrianextern void ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, 546250003Sadrian u_int num_delims); 547250008Sadrianextern void ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); 548250008Sadrianextern void ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds); 549250008Sadrianextern void ar9300_set_11n_burst_duration(struct ath_hal *ah, 550250008Sadrian struct ath_desc *ds, u_int burst_duration); 551250003Sadrianextern void ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds); 552250003Sadrianextern void ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds); 553250003Sadrianextern void ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds); 554250003Sadrianextern void ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds); 555250008Sadrianextern void ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, 556250008Sadrian struct ath_desc *ds, u_int vmf); 557250003Sadrian#ifdef AH_PRIVATE_DIAG 558250003Sadrianextern void ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode); 559250003Sadrian#endif 560250003Sadrian 561250003Sadrian /* RX common functions */ 562250003Sadrian 563250003Sadrianextern u_int32_t ar9300_get_rx_dp(struct ath_hal *ath, HAL_RX_QUEUE qtype); 564250003Sadrianextern void ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype); 565250003Sadrianextern void ar9300_enable_receive(struct ath_hal *ah); 566250003Sadrianextern HAL_BOOL ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout); 567250003Sadrianextern void ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning); 568250003Sadrianextern void ar9300_stop_pcu_receive(struct ath_hal *ah); 569250003Sadrianextern void ar9300_set_multicast_filter(struct ath_hal *ah, 570250003Sadrian u_int32_t filter0, u_int32_t filter1); 571250003Sadrianextern u_int32_t ar9300_get_rx_filter(struct ath_hal *ah); 572250003Sadrianextern void ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits); 573250003Sadrianextern HAL_BOOL ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL, HAL_BOOL); 574250008Sadrianextern HAL_BOOL ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL); 575250003Sadrian 576250003Sadrianextern HAL_STATUS ar9300_proc_rx_desc(struct ath_hal *ah, 577250003Sadrian struct ath_desc *, u_int32_t, struct ath_desc *, u_int64_t, struct ath_rx_status *); 578250003Sadrianextern HAL_STATUS ar9300_get_rx_key_idx(struct ath_hal *ah, 579250003Sadrian struct ath_desc *, u_int8_t *, u_int8_t *); 580250003Sadrianextern HAL_STATUS ar9300_proc_rx_desc_fast(struct ath_hal *ah, struct ath_desc *, 581250003Sadrian u_int32_t, struct ath_desc *, struct ath_rx_status *, void *); 582250003Sadrian 583250003Sadrianextern void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable); 584250003Sadrianextern void ar9300_read_pktlog_reg(struct ath_hal *ah, u_int32_t *, u_int32_t *, u_int32_t *, u_int32_t *); 585250003Sadrianextern void ar9300_write_pktlog_reg(struct ath_hal *ah, HAL_BOOL , u_int32_t , u_int32_t , u_int32_t , u_int32_t ); 586250003Sadrian 587250003Sadrian#endif 588250003Sadrian 589250008Sadrian#endif /* _ATH_AR9300_DESC_H_ */ 590