1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#include "opt_ah.h" 18250003Sadrian 19250003Sadrian#include "ah.h" 20250003Sadrian#include "ah_internal.h" 21250003Sadrian 22250003Sadrian#include "ar9300/ar9300.h" 23250003Sadrian#include "ar9300/ar9300reg.h" 24250003Sadrian#include "ar9300/ar9300desc.h" 25250003Sadrian 26250003Sadriantypedef struct gen_timer_configuation { 27250003Sadrian u_int32_t next_addr; 28250003Sadrian u_int32_t period_addr; 29250003Sadrian u_int32_t mode_addr; 30250003Sadrian u_int32_t mode_mask; 31250003Sadrian} GEN_TIMER_CONFIGURATION; 32250003Sadrian 33250003Sadrian#define AR_GEN_TIMERS2_CFG(num) \ 34250003Sadrian AR_GEN_TIMERS2_ ## num ## _NEXT, \ 35250003Sadrian AR_GEN_TIMERS2_ ## num ## _PERIOD, \ 36250003Sadrian AR_GEN_TIMERS2_MODE, \ 37250003Sadrian (1 << num) 38250003Sadrianstatic const GEN_TIMER_CONFIGURATION gen_timer_configuration[] = 39250003Sadrian{ 40250003Sadrian {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 41250003Sadrian {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 42250003Sadrian {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 43250003Sadrian {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 44250003Sadrian {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 45250003Sadrian {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 46250003Sadrian {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 47250003Sadrian {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, 48250003Sadrian {AR_GEN_TIMERS2_CFG(0)}, 49250003Sadrian {AR_GEN_TIMERS2_CFG(1)}, 50250003Sadrian {AR_GEN_TIMERS2_CFG(2)}, 51250003Sadrian {AR_GEN_TIMERS2_CFG(3)}, 52250003Sadrian {AR_GEN_TIMERS2_CFG(4)}, 53250003Sadrian {AR_GEN_TIMERS2_CFG(5)}, 54250003Sadrian {AR_GEN_TIMERS2_CFG(6)}, 55250003Sadrian {AR_GEN_TIMERS2_CFG(7)} 56250003Sadrian}; 57250003Sadrian 58250003Sadrian#define AR_GENTMR_BIT(_index) (1 << (_index)) 59250003Sadrian 60250003Sadrianint 61250003Sadrianar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf) 62250003Sadrian{ 63250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 64250003Sadrian u_int32_t i, mask; 65250003Sadrian u_int32_t avail_timer_start, avail_timer_end; 66250003Sadrian 67250003Sadrian if (tsf == HAL_GEN_TIMER_TSF) { 68250003Sadrian avail_timer_start = AR_FIRST_NDP_TIMER; 69250003Sadrian avail_timer_end = AR_GEN_TIMER_BANK_1_LEN; 70250003Sadrian } else { 71250003Sadrian avail_timer_start = AR_GEN_TIMER_BANK_1_LEN; 72250003Sadrian avail_timer_end = AR_NUM_GEN_TIMERS; 73250003Sadrian } 74250003Sadrian 75250003Sadrian /* Find the first availabe timer index */ 76250003Sadrian i = avail_timer_start; 77250003Sadrian mask = ahp->ah_avail_gen_timers >> i; 78250003Sadrian for ( ; mask && (i < avail_timer_end) ; mask >>= 1, i++ ) { 79250003Sadrian if (mask & 0x1) { 80250003Sadrian ahp->ah_avail_gen_timers &= ~(AR_GENTMR_BIT(i)); 81250003Sadrian 82250003Sadrian if ((tsf == HAL_GEN_TIMER_TSF2) && !ahp->ah_enable_tsf2) { 83250003Sadrian ahp->ah_enable_tsf2 = AH_TRUE; 84250003Sadrian ar9300_start_tsf2(ah); 85250003Sadrian } 86250003Sadrian return i; 87250003Sadrian } 88250003Sadrian } 89250003Sadrian return -1; 90250003Sadrian} 91250003Sadrian 92250003Sadrianvoid ar9300_start_tsf2(struct ath_hal *ah) 93250003Sadrian{ 94250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 95250003Sadrian 96250003Sadrian if (ahp->ah_enable_tsf2) { 97250003Sadrian /* Delay might be needed after TSF2 reset */ 98250003Sadrian OS_REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); 99250003Sadrian OS_REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); 100250003Sadrian } 101250003Sadrian} 102250003Sadrian 103250003Sadrianvoid 104250003Sadrianar9300_free_generic_timer(struct ath_hal *ah, int index) 105250003Sadrian{ 106250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 107250003Sadrian 108250003Sadrian ar9300_stop_generic_timer(ah, index); 109250003Sadrian ahp->ah_avail_gen_timers |= AR_GENTMR_BIT(index); 110250003Sadrian} 111250003Sadrian 112250003Sadrianvoid 113250003Sadrianar9300_start_generic_timer( 114250003Sadrian struct ath_hal *ah, 115250003Sadrian int index, 116250003Sadrian u_int32_t timer_next, 117250003Sadrian u_int32_t timer_period) 118250003Sadrian{ 119250003Sadrian if ((index < AR_FIRST_NDP_TIMER) || (index >= AR_NUM_GEN_TIMERS)) { 120250003Sadrian return; 121250003Sadrian } 122250003Sadrian 123250003Sadrian /* 124250003Sadrian * Program generic timer registers 125250003Sadrian */ 126250003Sadrian OS_REG_WRITE(ah, gen_timer_configuration[index].next_addr, timer_next); 127250003Sadrian OS_REG_WRITE(ah, gen_timer_configuration[index].period_addr, timer_period); 128250003Sadrian OS_REG_SET_BIT(ah, 129250003Sadrian gen_timer_configuration[index].mode_addr, 130250003Sadrian gen_timer_configuration[index].mode_mask); 131250003Sadrian 132250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 133250003Sadrian /* 134250003Sadrian * Starting from Jupiter, each generic timer can select which tsf to 135250003Sadrian * use. But we still follow the old rule, 0 - 7 use tsf and 8 - 15 136250003Sadrian * use tsf2. 137250003Sadrian */ 138250003Sadrian if ((index < AR_GEN_TIMER_BANK_1_LEN)) { 139250003Sadrian OS_REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, (1 << index)); 140250003Sadrian } 141250003Sadrian else { 142250003Sadrian OS_REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, (1 << index)); 143250003Sadrian } 144250003Sadrian } 145250003Sadrian 146250003Sadrian /* Enable both trigger and thresh interrupt masks */ 147250003Sadrian OS_REG_SET_BIT(ah, AR_IMR_S5, 148250003Sadrian (SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_THRESH) | 149250003Sadrian SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_TRIG))); 150250003Sadrian} 151250003Sadrian 152250003Sadrianvoid 153250003Sadrianar9300_stop_generic_timer(struct ath_hal *ah, int index) 154250003Sadrian{ 155250003Sadrian if ((index < AR_FIRST_NDP_TIMER) || (index >= AR_NUM_GEN_TIMERS)) { 156250003Sadrian return; 157250003Sadrian } 158250003Sadrian 159250003Sadrian /* 160250003Sadrian * Clear generic timer enable bits. 161250003Sadrian */ 162250003Sadrian OS_REG_CLR_BIT(ah, 163250003Sadrian gen_timer_configuration[index].mode_addr, 164250003Sadrian gen_timer_configuration[index].mode_mask); 165250003Sadrian 166250003Sadrian /* Disable both trigger and thresh interrupt masks */ 167250003Sadrian OS_REG_CLR_BIT(ah, AR_IMR_S5, 168250003Sadrian (SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_THRESH) | 169250003Sadrian SM(AR_GENTMR_BIT(index), AR_IMR_S5_GENTIMER_TRIG))); 170250003Sadrian} 171250003Sadrian 172250003Sadrianvoid 173250003Sadrianar9300_get_gen_timer_interrupts( 174250003Sadrian struct ath_hal *ah, 175250003Sadrian u_int32_t *trigger, 176250003Sadrian u_int32_t *thresh) 177250003Sadrian{ 178250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 179250003Sadrian *trigger = ahp->ah_intr_gen_timer_trigger; 180250003Sadrian *thresh = ahp->ah_intr_gen_timer_thresh; 181250003Sadrian} 182