ar9300_misc.c revision 286337
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "opt_ah.h" 18 19#include "ah.h" 20#include "ah_internal.h" 21#include "ah_devid.h" 22#ifdef AH_DEBUG 23#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24#endif 25 26#include "ar9300/ar9300.h" 27#include "ar9300/ar9300reg.h" 28#include "ar9300/ar9300phy.h" 29 30 31void 32ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 33{ 34 struct ath_hal_9300 *ahp = AH9300(ah); 35 *hangs = 0; 36 37 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 38 *hangs |= HAL_RIFS_BB_HANG_WAR; 39 } 40 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 41 *hangs |= HAL_DFS_BB_HANG_WAR; 42 } 43 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 44 == HAL_OK) 45 { 46 *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 47 } 48 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 49 *hangs |= HAL_MAC_HANG_WAR; 50 } 51 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 52 == HAL_OK) 53 { 54 *hangs |= HAL_PHYRESTART_CLR_WAR; 55 } 56 57 ahp->ah_hang_wars = *hangs; 58} 59 60/* 61 * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about 62 * HT20, HT40, fast-clock, turbo mode, etc. 63 */ 64static u_int 65ar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 66{ 67#if 0 68 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 69 70 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 71 return (ath_hal_mac_usec(ah, clks) / 2); 72 } else { 73 return (ath_hal_mac_usec(ah, clks)); 74 } 75#endif 76 return (ath_hal_mac_usec(ah, clks)); 77} 78 79u_int 80ar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 81{ 82#if 0 83 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 84 85 if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 86 return (ath_hal_mac_clks(ah, usecs) * 2); 87 } else { 88 return (ath_hal_mac_clks(ah, usecs)); 89 } 90#endif 91 return (ath_hal_mac_clks(ah, usecs)); 92} 93 94void 95ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 96{ 97 struct ath_hal_9300 *ahp = AH9300(ah); 98 99 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 100} 101 102HAL_BOOL 103ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 104{ 105 struct ath_hal_9300 *ahp = AH9300(ah); 106 107 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 108 return AH_TRUE; 109} 110 111void 112ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 113{ 114 struct ath_hal_9300 *ahp = AH9300(ah); 115 116 OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 117} 118 119HAL_BOOL 120ar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 121{ 122 struct ath_hal_9300 *ahp = AH9300(ah); 123 124 /* save it since it must be rewritten on reset */ 125 OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 126 127 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 128 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 129 return AH_TRUE; 130} 131 132/* 133 * Attempt to change the cards operating regulatory domain to the given value 134 * Returns: A_EINVAL for an unsupported regulatory domain. 135 * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 136 */ 137HAL_BOOL 138ar9300_set_regulatory_domain(struct ath_hal *ah, 139 u_int16_t reg_domain, HAL_STATUS *status) 140{ 141 HAL_STATUS ecode; 142 143 if (AH_PRIVATE(ah)->ah_currentRD == 0) { 144 AH_PRIVATE(ah)->ah_currentRD = reg_domain; 145 return AH_TRUE; 146 } 147 ecode = HAL_EIO; 148 149#if 0 150bad: 151#endif 152 if (status) { 153 *status = ecode; 154 } 155 return AH_FALSE; 156} 157 158/* 159 * Return the wireless modes (a,b,g,t) supported by hardware. 160 * 161 * This value is what is actually supported by the hardware 162 * and is unaffected by regulatory/country code settings. 163 * 164 */ 165u_int 166ar9300_get_wireless_modes(struct ath_hal *ah) 167{ 168 return AH_PRIVATE(ah)->ah_caps.halWirelessModes; 169} 170 171/* 172 * Set the interrupt and GPIO values so the ISR can disable RF 173 * on a switch signal. Assumes GPIO port and interrupt polarity 174 * are set prior to call. 175 */ 176void 177ar9300_enable_rf_kill(struct ath_hal *ah) 178{ 179 /* TODO - can this really be above the hal on the GPIO interface for 180 * TODO - the client only? 181 */ 182 struct ath_hal_9300 *ahp = AH9300(ah); 183 184 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 185 /* Check RF kill GPIO before set/clear RFSILENT bits. */ 186 if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 187 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 188 AR_RFSILENT_FORCE); 189 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 190 } 191 else { 192 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 193 AR_RFSILENT_FORCE); 194 OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 195 } 196 } 197 else { 198 /* Connect rfsilent_bb_l to baseband */ 199 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 200 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 201 202 /* Set input mux for rfsilent_bb_l to GPIO #0 */ 203 OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 204 AR_GPIO_INPUT_MUX2_RFSILENT); 205 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 206 (ahp->ah_gpio_select & 0x0f) << 4); 207 208 /* 209 * Configure the desired GPIO port for input and 210 * enable baseband rf silence 211 */ 212 ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select); 213 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 214 } 215 216 /* 217 * If radio disable switch connection to GPIO bit x is enabled 218 * program GPIO interrupt. 219 * If rfkill bit on eeprom is 1, setupeeprommap routine has already 220 * verified that it is a later version of eeprom, it has a place for 221 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 222 * connection is present. 223 */ 224 /* 225 * RFKill uses polling not interrupt, 226 * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 227 */ 228 if (ath_hal_hasrfkill_int(ah)) { 229 if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 230 /* switch already closed, set to interrupt upon open */ 231 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 232 } else { 233 ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 234 } 235 } 236} 237 238/* 239 * Change the LED blinking pattern to correspond to the connectivity 240 */ 241void 242ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 243{ 244 static const u_int32_t ledbits[8] = { 245 AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 246 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 247 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 248 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 249 AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 250 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 251 AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 252 AR_CFG_LED_ASSOC_NONE, 253 }; 254 255 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 256} 257 258/* 259 * Sets the Power LED on the cardbus without affecting the Network LED. 260 */ 261void 262ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 263{ 264 u_int32_t val; 265 266 val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 267 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 268} 269 270/* 271 * Sets the Network LED on the cardbus without affecting the Power LED. 272 */ 273void 274ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 275{ 276 u_int32_t val; 277 278 val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 279 OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 280} 281 282/* 283 * Change association related fields programmed into the hardware. 284 * Writing a valid BSSID to the hardware effectively enables the hardware 285 * to synchronize its TSF to the correct beacons and receive frames coming 286 * from that BSSID. It is called by the SME JOIN operation. 287 */ 288void 289ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 290 u_int16_t assoc_id) 291{ 292 struct ath_hal_9300 *ahp = AH9300(ah); 293 294 /* save bssid and assoc_id for restore on reset */ 295 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 296 ahp->ah_assoc_id = assoc_id; 297 298 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 299 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 300 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 301} 302 303/* 304 * Get the current hardware tsf for stamlme 305 */ 306u_int64_t 307ar9300_get_tsf64(struct ath_hal *ah) 308{ 309 u_int64_t tsf; 310 311 /* XXX sync multi-word read? */ 312 tsf = OS_REG_READ(ah, AR_TSF_U32); 313 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 314 return tsf; 315} 316 317void 318ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 319{ 320 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 321 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 322} 323 324/* 325 * Get the current hardware tsf for stamlme 326 */ 327u_int32_t 328ar9300_get_tsf32(struct ath_hal *ah) 329{ 330 return OS_REG_READ(ah, AR_TSF_L32); 331} 332 333u_int32_t 334ar9300_get_tsf2_32(struct ath_hal *ah) 335{ 336 return OS_REG_READ(ah, AR_TSF2_L32); 337} 338 339/* 340 * Reset the current hardware tsf for stamlme. 341 */ 342void 343ar9300_reset_tsf(struct ath_hal *ah) 344{ 345 int count; 346 347 count = 0; 348 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 349 count++; 350 if (count > 10) { 351 HALDEBUG(ah, HAL_DEBUG_RESET, 352 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 353 break; 354 } 355 OS_DELAY(10); 356 } 357 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 358} 359 360/* 361 * Set or clear hardware basic rate bit 362 * Set hardware basic rate set if basic rate is found 363 * and basic rate is equal or less than 2Mbps 364 */ 365void 366ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 367{ 368 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 369 u_int32_t reg; 370 u_int8_t xset; 371 int i; 372 373 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) { 374 return; 375 } 376 xset = 0; 377 for (i = 0; i < rs->rs_count; i++) { 378 u_int8_t rset = rs->rs_rates[i]; 379 /* Basic rate defined? */ 380 if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 381 xset = rset; 382 } 383 } 384 /* 385 * Set the h/w bit to reflect whether or not the basic 386 * rate is found to be equal or less than 2Mbps. 387 */ 388 reg = OS_REG_READ(ah, AR_STA_ID1); 389 if (xset && xset / 2 <= 2) { 390 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 391 } else { 392 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 393 } 394} 395 396/* 397 * Grab a semi-random value from hardware registers - may not 398 * change often 399 */ 400u_int32_t 401ar9300_get_random_seed(struct ath_hal *ah) 402{ 403 u_int32_t nf; 404 405 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 406 if (nf & 0x100) { 407 nf = 0 - ((nf ^ 0x1ff) + 1); 408 } 409 return (OS_REG_READ(ah, AR_TSF_U32) ^ 410 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 411} 412 413/* 414 * Detect if our card is present 415 */ 416HAL_BOOL 417ar9300_detect_card_present(struct ath_hal *ah) 418{ 419 u_int16_t mac_version, mac_rev; 420 u_int32_t v; 421 422 /* 423 * Read the Silicon Revision register and compare that 424 * to what we read at attach time. If the same, we say 425 * a card/device is present. 426 */ 427 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 428 if (v == 0xFF) { 429 /* new SREV format */ 430 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 431 /* 432 * Include 6-bit Chip Type (masked to 0) to differentiate 433 * from pre-Sowl versions 434 */ 435 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 436 mac_rev = MS(v, AR_SREV_REVISION2); 437 } else { 438 mac_version = MS(v, AR_SREV_VERSION); 439 mac_rev = v & AR_SREV_REVISION; 440 } 441 return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 442 AH_PRIVATE(ah)->ah_macRev == mac_rev); 443} 444 445/* 446 * Update MIB Counters 447 */ 448void 449ar9300_update_mib_mac_stats(struct ath_hal *ah) 450{ 451 struct ath_hal_9300 *ahp = AH9300(ah); 452 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 453 454 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 455 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 456 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 457 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 458 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 459} 460 461void 462ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 463{ 464 struct ath_hal_9300 *ahp = AH9300(ah); 465 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 466 467 stats->ackrcv_bad = istats->ackrcv_bad; 468 stats->rts_bad = istats->rts_bad; 469 stats->fcs_bad = istats->fcs_bad; 470 stats->rts_good = istats->rts_good; 471 stats->beacons = istats->beacons; 472} 473 474/* 475 * Detect if the HW supports spreading a CCK signal on channel 14 476 */ 477HAL_BOOL 478ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 479{ 480 return AH_TRUE; 481} 482 483/* 484 * Get the rssi of frame curently being received. 485 */ 486u_int32_t 487ar9300_get_cur_rssi(struct ath_hal *ah) 488{ 489 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 490 /* get combined RSSI */ 491 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 492} 493 494#if ATH_GEN_RANDOMNESS 495/* 496 * Get the rssi value from BB on ctl chain0. 497 */ 498u_int32_t 499ar9300_get_rssi_chain0(struct ath_hal *ah) 500{ 501 /* get ctl chain0 RSSI */ 502 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 503} 504#endif 505 506u_int 507ar9300_get_def_antenna(struct ath_hal *ah) 508{ 509 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 510} 511 512/* Setup coverage class */ 513void 514ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 515{ 516} 517 518void 519ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 520{ 521 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 522} 523 524HAL_BOOL 525ar9300_set_antenna_switch(struct ath_hal *ah, 526 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 527 u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 528{ 529 struct ath_hal_9300 *ahp = AH9300(ah); 530 531 /* 532 * Owl does not support diversity or changing antennas. 533 * 534 * Instead this API and function are defined differently for AR9300. 535 * To support Tablet PC's, this interface allows the system 536 * to dramatically reduce the TX power on a particular chain. 537 * 538 * Based on the value of (redefined) diversity_control, the 539 * reset code will decrease power on chain 0 or chain 1/2. 540 * 541 * Based on the value of bit 0 of antenna_switch_swap, 542 * the mapping between OID call and chain is defined as: 543 * 0: map A -> 0, B -> 1; 544 * 1: map A -> 1, B -> 0; 545 * 546 * NOTE: 547 * The devices that use this OID should use a tx_chain_mask and 548 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 549 * used in order to ensure an active transmit antenna. This 550 * API will allow the host to turn off the only transmitting 551 * antenna to ensure the antenna closest to the user's body is 552 * powered-down. 553 */ 554 /* 555 * Set antenna control for use during reset sequence by 556 * ar9300_decrease_chain_power() 557 */ 558 ahp->ah_diversity_control = settings; 559 560 return AH_TRUE; 561} 562 563HAL_BOOL 564ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 565{ 566 return AH_TRUE; 567} 568 569HAL_BOOL 570ar9300_set_slot_time(struct ath_hal *ah, u_int us) 571{ 572 struct ath_hal_9300 *ahp = AH9300(ah); 573 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 574 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 575 ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 576 return AH_FALSE; 577 } else { 578 /* convert to system clocks */ 579 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 580 ahp->ah_slot_time = us; 581 return AH_TRUE; 582 } 583} 584 585HAL_BOOL 586ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 587{ 588 struct ath_hal_9300 *ahp = AH9300(ah); 589 590 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 591 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 592 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 593 return AH_FALSE; 594 } else { 595 /* convert to system clocks */ 596 OS_REG_RMW_FIELD(ah, 597 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 598 ahp->ah_ack_timeout = us; 599 return AH_TRUE; 600 } 601} 602 603u_int 604ar9300_get_ack_timeout(struct ath_hal *ah) 605{ 606 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 607 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 608} 609 610HAL_STATUS 611ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 612 u_int32_t next_start, HAL_QUIET_FLAG flag) 613{ 614#define TU_TO_USEC(_tu) ((_tu) << 10) 615 HAL_STATUS status = HAL_EIO; 616 u_int32_t tsf = 0, j, next_start_us = 0; 617 if (flag & HAL_QUIET_ENABLE) { 618 for (j = 0; j < 2; j++) { 619 next_start_us = TU_TO_USEC(next_start); 620 tsf = OS_REG_READ(ah, AR_TSF_L32); 621 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 622 next_start_us += tsf; 623 } 624 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 625 next_start_us += 626 ah->ah_config.ah_sw_beacon_response_time; 627 } 628 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 629 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 630 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 631 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 632 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 633 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 634 status = HAL_OK; 635 break; 636 } 637 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 638 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 639 /* TSF shouldn't count twice or reg access is taking forever */ 640 HALASSERT(j < 1); 641 } 642 } else { 643 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 644 status = HAL_OK; 645 } 646 647 return status; 648#undef TU_TO_USEC 649} 650#ifdef ATH_SUPPORT_DFS 651void 652ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 653{ 654 u32 reg1, reg2; 655 656 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 657 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 658 AH9300(ah)->ah_cac_quiet_enabled = enable; 659 660 if (enable) { 661 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 662 reg1 | AR_PCU_FORCE_QUIET_COLL); 663 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 664 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 665 } else { 666 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 667 reg1 & ~AR_PCU_FORCE_QUIET_COLL); 668 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 669 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 670 } 671} 672#endif /* ATH_SUPPORT_DFS */ 673 674void 675ar9300_set_pcu_config(struct ath_hal *ah) 676{ 677 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 678} 679 680HAL_STATUS 681ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 682 u_int32_t capability, u_int32_t *result) 683{ 684 struct ath_hal_9300 *ahp = AH9300(ah); 685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 686 struct ar9300_ani_state *ani; 687 688 switch (type) { 689 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 690 switch (capability) { 691 case HAL_CIPHER_AES_CCM: 692 case HAL_CIPHER_AES_OCB: 693 case HAL_CIPHER_TKIP: 694 case HAL_CIPHER_WEP: 695 case HAL_CIPHER_MIC: 696 case HAL_CIPHER_CLR: 697 return HAL_OK; 698 default: 699 return HAL_ENOTSUPP; 700 } 701 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 702 switch (capability) { 703 case 0: /* hardware capability */ 704 return HAL_OK; 705 case 1: 706 return (ahp->ah_sta_id1_defaults & 707 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 708 default: 709 return HAL_ENOTSUPP; 710 } 711 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 712 switch (capability) { 713 case 0: /* hardware capability */ 714 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK; 715 case 1: /* current setting */ 716 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 717 HAL_ENXIO : HAL_OK; 718 default: 719 return HAL_ENOTSUPP; 720 } 721 case HAL_CAP_WME_TKIPMIC: 722 /* hardware can do TKIP MIC when WMM is turned on */ 723 return HAL_OK; 724 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 725 return HAL_OK; 726 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 727 switch (capability) { 728 case 0: /* hardware capability */ 729 return HAL_OK; 730 case 1: /* current setting */ 731 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 732 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 733 HAL_OK : HAL_ENXIO; 734 } 735 return HAL_EINVAL; 736 case HAL_CAP_TPC: 737 switch (capability) { 738 case 0: /* hardware capability */ 739 return HAL_OK; 740 case 1: 741 return ah->ah_config.ath_hal_desc_tpc ? 742 HAL_OK : HAL_ENXIO; 743 } 744 return HAL_OK; 745 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 746 return HAL_OK; 747 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 748 switch (capability) { 749 case 0: /* hardware capability */ 750 return HAL_OK; 751 case 1: 752 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 753 /* 754 * Owl and Merlin have problems in mcast key search. 755 * Disable this cap. in Ad-hoc mode. see Bug 25776 and 756 * 26802 757 */ 758 return HAL_ENXIO; 759 } else { 760 return (ahp->ah_sta_id1_defaults & 761 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 762 } 763 } 764 return HAL_EINVAL; 765 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 766 switch (capability) { 767 case 0: /* hardware capability */ 768 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 769 case 1: 770 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 771 HAL_OK : HAL_ENXIO; 772 } 773 return HAL_EINVAL; 774 case HAL_CAP_RFSILENT: /* rfsilent support */ 775 if (capability == 3) { /* rfkill interrupt */ 776 /* 777 * XXX: Interrupt-based notification of RF Kill state 778 * changes not working yet. Report that this feature 779 * is not supported so that polling is used instead. 780 */ 781 return (HAL_ENOTSUPP); 782 } 783 return ath_hal_getcapability(ah, type, capability, result); 784 case HAL_CAP_4ADDR_AGGR: 785 return HAL_OK; 786 case HAL_CAP_BB_RIFS_HANG: 787 return HAL_ENOTSUPP; 788 case HAL_CAP_BB_DFS_HANG: 789 return HAL_ENOTSUPP; 790 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 791 /* Track chips that are known to have BB hangs related 792 * to rx_clear stuck low. 793 */ 794 return HAL_ENOTSUPP; 795 case HAL_CAP_MAC_HANG: 796 /* Track chips that are known to have MAC hangs. 797 */ 798 return HAL_OK; 799 case HAL_CAP_RIFS_RX_ENABLED: 800 /* Is RIFS RX currently enabled */ 801 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 802#if 0 803 case HAL_CAP_ANT_CFG_2GHZ: 804 *result = p_cap->halNumAntCfg2Ghz; 805 return HAL_OK; 806 case HAL_CAP_ANT_CFG_5GHZ: 807 *result = p_cap->halNumAntCfg5Ghz; 808 return HAL_OK; 809 case HAL_CAP_RX_STBC: 810 *result = p_cap->hal_rx_stbc_support; 811 return HAL_OK; 812 case HAL_CAP_TX_STBC: 813 *result = p_cap->hal_tx_stbc_support; 814 return HAL_OK; 815#endif 816 case HAL_CAP_LDPC: 817 *result = p_cap->halLDPCSupport; 818 return HAL_OK; 819 case HAL_CAP_DYNAMIC_SMPS: 820 return HAL_OK; 821 case HAL_CAP_DS: 822 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 823 (p_cap->halTxChainMask & 0x3) != 0x3 || 824 (p_cap->halRxChainMask & 0x3) != 0x3) ? 825 HAL_ENOTSUPP : HAL_OK; 826 case HAL_CAP_TS: 827 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 828 (p_cap->halTxChainMask & 0x7) != 0x7 || 829 (p_cap->halRxChainMask & 0x7) != 0x7) ? 830 HAL_ENOTSUPP : HAL_OK; 831 case HAL_CAP_OL_PWRCTRL: 832 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 833 HAL_OK : HAL_ENOTSUPP; 834 case HAL_CAP_CRDC: 835#if ATH_SUPPORT_CRDC 836 return (AR_SREV_WASP(ah) && 837 ah->ah_config.ath_hal_crdc_enable) ? 838 HAL_OK : HAL_ENOTSUPP; 839#else 840 return HAL_ENOTSUPP; 841#endif 842#if 0 843 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 844 *result = (u_int32_t)(-1); 845 return HAL_OK; 846 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 847 *result = (u_int32_t)(-1); 848 return HAL_OK; 849#endif 850 case HAL_CAP_BB_PANIC_WATCHDOG: 851 return HAL_OK; 852 case HAL_CAP_PHYRESTART_CLR_WAR: 853 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 854 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 855 { 856 return HAL_OK; 857 } 858 else 859 { 860 return HAL_ENOTSUPP; 861 } 862 case HAL_CAP_ENTERPRISE_MODE: 863 *result = ahp->ah_enterprise_mode >> 16; 864 /* 865 * WAR for EV 77658 - Add delimiters to first sub-frame when using 866 * RTS/CTS with aggregation and non-enterprise Osprey. 867 * 868 * Bug fixed in AR9580/Peacock, Wasp1.1 and later 869 */ 870 if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 871 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 872 AR_SREV_WASP_10(ah))) { 873 *result |= AH_ENT_RTSCTS_DELIM_WAR; 874 } 875 return HAL_OK; 876 case HAL_CAP_LDPCWAR: 877 /* WAR for RIFS+LDPC issue is required for all chips currently 878 * supported by ar9300 HAL. 879 */ 880 return HAL_OK; 881 case HAL_CAP_ENABLE_APM: 882 *result = p_cap->halApmEnable; 883 return HAL_OK; 884 case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 885 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 886 case HAL_CAP_PCIE_LCR_OFFSET: 887 *result = p_cap->hal_pcie_lcr_offset; 888 return HAL_OK; 889 case HAL_CAP_SMARTANTENNA: 890 /* FIXME A request is pending with h/w team to add feature bit in 891 * caldata to detect if board has smart antenna or not, once added 892 * we need to fix his piece of code to read and return value without 893 * any compile flags 894 */ 895#if UMAC_SUPPORT_SMARTANTENNA 896 /* enable smart antenna for Peacock, Wasp and scorpion 897 for future chips need to modify */ 898 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 899 return HAL_OK; 900 } else { 901 return HAL_ENOTSUPP; 902 } 903#else 904 return HAL_ENOTSUPP; 905#endif 906 907#ifdef ATH_TRAFFIC_FAST_RECOVER 908 case HAL_CAP_TRAFFIC_FAST_RECOVER: 909 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 910 return HAL_OK; 911 } else { 912 return HAL_ENOTSUPP; 913 } 914#endif 915 916 /* FreeBSD ANI */ 917 case HAL_CAP_INTMIT: /* interference mitigation */ 918 switch (capability) { 919 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */ 920 return HAL_OK; 921 case HAL_CAP_INTMIT_ENABLE: 922 return (ahp->ah_proc_phy_err & HAL_PROCESS_ANI) ? 923 HAL_OK : HAL_ENXIO; 924 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL: 925 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL: 926// case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR: 927 case HAL_CAP_INTMIT_FIRSTEP_LEVEL: 928 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL: 929 ani = ar9300_ani_get_current_state(ah); 930 if (ani == AH_NULL) 931 return HAL_ENXIO; 932 switch (capability) { 933 /* XXX AR9300 HAL has OFDM/CCK noise immunity level params? */ 934 case 2: *result = ani->ofdm_noise_immunity_level; break; 935 case 3: *result = !ani->ofdm_weak_sig_detect_off; break; 936 // case 4: *result = ani->cck_weak_sig_threshold; break; 937 case 5: *result = ani->firstep_level; break; 938 case 6: *result = ani->spur_immunity_level; break; 939 } 940 return HAL_OK; 941 } 942 return HAL_EINVAL; 943 case HAL_CAP_ENFORCE_TXOP: 944 if (capability == 0) 945 return (HAL_OK); 946 if (capability != 1) 947 return (HAL_ENOTSUPP); 948 (*result) = !! (ahp->ah_misc_mode & AR_PCU_TXOP_TBTT_LIMIT_ENA); 949 return (HAL_OK); 950 default: 951 return ath_hal_getcapability(ah, type, capability, result); 952 } 953} 954 955HAL_BOOL 956ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 957 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 958{ 959 struct ath_hal_9300 *ahp = AH9300(ah); 960 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 961 u_int32_t v; 962 963 switch (type) { 964 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 965 if (! p_cap->halTkipMicTxRxKeySupport) 966 return AH_FALSE; 967 968 if (setting) 969 ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA; 970 else 971 ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 972 973 OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode); 974 return AH_TRUE; 975 976 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 977 if (setting) { 978 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 979 } else { 980 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 981 } 982 return AH_TRUE; 983 case HAL_CAP_DIVERSITY: 984 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 985 if (setting) { 986 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 987 } else { 988 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 989 } 990 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 991 return AH_TRUE; 992 case HAL_CAP_DIAG: /* hardware diagnostic support */ 993 /* 994 * NB: could split this up into virtual capabilities, 995 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 996 * seems worth the additional complexity. 997 */ 998#ifdef AH_DEBUG 999 AH_PRIVATE(ah)->ah_diagreg = setting; 1000#else 1001 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 1002#endif 1003 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 1004 return AH_TRUE; 1005 case HAL_CAP_TPC: 1006 ah->ah_config.ath_hal_desc_tpc = (setting != 0); 1007 return AH_TRUE; 1008 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 1009 if (setting) { 1010 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 1011 } else { 1012 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 1013 } 1014 return AH_TRUE; 1015 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 1016 if (p_cap->halTsfAddSupport) { 1017 if (setting) { 1018 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 1019 } else { 1020 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 1021 } 1022 return AH_TRUE; 1023 } 1024 return AH_FALSE; 1025 1026 /* FreeBSD interrupt mitigation / ANI */ 1027 case HAL_CAP_INTMIT: { /* interference mitigation */ 1028 /* This maps the public ANI commands to the internal ANI commands */ 1029 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */ 1030 static const HAL_ANI_CMD cmds[] = { 1031 HAL_ANI_PRESENT, 1032 HAL_ANI_MODE, 1033 HAL_ANI_NOISE_IMMUNITY_LEVEL, 1034 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, 1035 HAL_ANI_CCK_WEAK_SIGNAL_THR, 1036 HAL_ANI_FIRSTEP_LEVEL, 1037 HAL_ANI_SPUR_IMMUNITY_LEVEL, 1038 }; 1039#define N(a) (sizeof(a) / sizeof(a[0])) 1040 return capability < N(cmds) ? 1041 ar9300_ani_control(ah, cmds[capability], setting) : 1042 AH_FALSE; 1043#undef N 1044 } 1045 1046 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 1047 ahp->rx_buf_size = setting & AR_DATABUF_MASK; 1048 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 1049 return AH_TRUE; 1050 1051 case HAL_CAP_ENFORCE_TXOP: 1052 if (capability != 1) 1053 return AH_FALSE; 1054 if (setting) { 1055 ahp->ah_misc_mode |= AR_PCU_TXOP_TBTT_LIMIT_ENA; 1056 OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1057 } else { 1058 ahp->ah_misc_mode &= ~AR_PCU_TXOP_TBTT_LIMIT_ENA; 1059 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_TXOP_TBTT_LIMIT_ENA); 1060 } 1061 return AH_TRUE; 1062 1063 /* fall thru... */ 1064 default: 1065 return ath_hal_setcapability(ah, type, capability, setting, status); 1066 } 1067} 1068 1069#ifdef AH_DEBUG 1070static void 1071ar9300_print_reg(struct ath_hal *ah, u_int32_t args) 1072{ 1073 u_int32_t i = 0; 1074 1075 /* Read 0x80d0 to trigger pcie analyzer */ 1076 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1077 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 1078 1079 if (args & HAL_DIAG_PRINT_REG_COUNTER) { 1080 struct ath_hal_9300 *ahp = AH9300(ah); 1081 u_int32_t tf, rf, rc, cc; 1082 1083 tf = OS_REG_READ(ah, AR_TFCNT); 1084 rf = OS_REG_READ(ah, AR_RFCNT); 1085 rc = OS_REG_READ(ah, AR_RCCNT); 1086 cc = OS_REG_READ(ah, AR_CCCNT); 1087 1088 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1089 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 1090 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1091 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 1092 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1093 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 1094 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1095 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 1096 1097 ahp->last_tf = tf; 1098 ahp->last_rf = rf; 1099 ahp->last_rc = rc; 1100 ahp->last_cc = cc; 1101 1102 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1103 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1104 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1105 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1106 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1107 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1108 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1109 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1110 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1111 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1112 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1113 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1114 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1115 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1116 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1117 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1118 } 1119 1120 if (args & HAL_DIAG_PRINT_REG_ALL) { 1121 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1122 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1123 i, OS_REG_READ(ah, i)); 1124 } 1125 1126 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1127 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1128 i, OS_REG_READ(ah, i)); 1129 } 1130 1131 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1132 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1133 1134 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1135 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1136 1137 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1138 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1139 i, OS_REG_READ(ah, i)); 1140 } 1141 1142 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1143 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1144 i, OS_REG_READ(ah, i)); 1145 } 1146 1147 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1148 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1149 i, OS_REG_READ(ah, i)); 1150 } 1151 1152 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1153 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1154 i, OS_REG_READ(ah, i)); 1155 } 1156 1157 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1158 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1159 i, OS_REG_READ(ah, i)); 1160 } 1161 1162 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1163 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1164 i, OS_REG_READ(ah, i)); 1165 } 1166 1167 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1168 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1169 i, OS_REG_READ(ah, i)); 1170 } 1171 1172 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1173 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1174 i, OS_REG_READ(ah, i)); 1175 } 1176 1177 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1178 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1179 i, OS_REG_READ(ah, i)); 1180 } 1181 1182 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1183 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1184 i, OS_REG_READ(ah, i)); 1185 } 1186 1187 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1188 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1189 i, OS_REG_READ(ah, i)); 1190 } 1191 } 1192} 1193#endif 1194 1195HAL_BOOL 1196ar9300_get_diag_state(struct ath_hal *ah, int request, 1197 const void *args, u_int32_t argsize, 1198 void **result, u_int32_t *resultsize) 1199{ 1200 struct ath_hal_9300 *ahp = AH9300(ah); 1201 struct ar9300_ani_state *ani; 1202 1203 (void) ahp; 1204 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1205 return AH_TRUE; 1206 } 1207 switch (request) { 1208#ifdef AH_PRIVATE_DIAG 1209 case HAL_DIAG_EEPROM: 1210 *result = &ahp->ah_eeprom; 1211 *resultsize = sizeof(ar9300_eeprom_t); 1212 return AH_TRUE; 1213 1214#if 0 /* XXX - TODO */ 1215 case HAL_DIAG_EEPROM_EXP_11A: 1216 case HAL_DIAG_EEPROM_EXP_11B: 1217 case HAL_DIAG_EEPROM_EXP_11G: 1218 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1219 *result = pe->p_channels; 1220 *resultsize = (*result == AH_NULL) ? 0 : 1221 roundup(sizeof(u_int16_t) * pe->num_channels, 1222 sizeof(u_int32_t)) + 1223 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1224 return AH_TRUE; 1225#endif 1226 case HAL_DIAG_RFGAIN: 1227 *result = &ahp->ah_gain_values; 1228 *resultsize = sizeof(GAIN_VALUES); 1229 return AH_TRUE; 1230 case HAL_DIAG_RFGAIN_CURSTEP: 1231 *result = (void *) ahp->ah_gain_values.curr_step; 1232 *resultsize = (*result == AH_NULL) ? 1233 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1234 return AH_TRUE; 1235#if 0 /* XXX - TODO */ 1236 case HAL_DIAG_PCDAC: 1237 *result = ahp->ah_pcdac_table; 1238 *resultsize = ahp->ah_pcdac_table_size; 1239 return AH_TRUE; 1240#endif 1241 case HAL_DIAG_ANI_CURRENT: 1242 1243 ani = ar9300_ani_get_current_state(ah); 1244 if (ani == AH_NULL) 1245 return AH_FALSE; 1246 /* Convert ar9300 HAL to FreeBSD HAL ANI state */ 1247 /* XXX TODO: add all of these to the HAL ANI state structure */ 1248 bzero(&ahp->ext_ani_state, sizeof(ahp->ext_ani_state)); 1249 /* XXX should this be OFDM or CCK noise immunity level? */ 1250 ahp->ext_ani_state.noiseImmunityLevel = ani->ofdm_noise_immunity_level; 1251 ahp->ext_ani_state.spurImmunityLevel = ani->spur_immunity_level; 1252 ahp->ext_ani_state.firstepLevel = ani->firstep_level; 1253 ahp->ext_ani_state.ofdmWeakSigDetectOff = ani->ofdm_weak_sig_detect_off; 1254 /* mrc_cck_off */ 1255 /* cck_noise_immunity_level */ 1256 1257 ahp->ext_ani_state.listenTime = ani->listen_time; 1258 1259 *result = &ahp->ext_ani_state; 1260 *resultsize = sizeof(ahp->ext_ani_state); 1261#if 0 1262 *result = ar9300_ani_get_current_state(ah); 1263 *resultsize = (*result == AH_NULL) ? 1264 0 : sizeof(struct ar9300_ani_state); 1265#endif 1266 return AH_TRUE; 1267 case HAL_DIAG_ANI_STATS: 1268 *result = ar9300_ani_get_current_stats(ah); 1269 *resultsize = (*result == AH_NULL) ? 1270 0 : sizeof(HAL_ANI_STATS); 1271 return AH_TRUE; 1272 case HAL_DIAG_ANI_CMD: 1273 if (argsize != 2*sizeof(u_int32_t)) { 1274 return AH_FALSE; 1275 } 1276 ar9300_ani_control( 1277 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1278 return AH_TRUE; 1279#if 0 1280 case HAL_DIAG_TXCONT: 1281 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1282 return AH_TRUE; 1283#endif /* 0 */ 1284#endif /* AH_PRIVATE_DIAG */ 1285 case HAL_DIAG_CHANNELS: 1286#if 0 1287 *result = &(ahp->ah_priv.ah_channels[0]); 1288 *resultsize = 1289 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1290#endif 1291 return AH_TRUE; 1292#ifdef AH_DEBUG 1293 case HAL_DIAG_PRINT_REG: 1294 ar9300_print_reg(ah, *((const u_int32_t *)args)); 1295 return AH_TRUE; 1296#endif 1297 default: 1298 break; 1299 } 1300 1301 return AH_FALSE; 1302} 1303 1304void 1305ar9300_dma_reg_dump(struct ath_hal *ah) 1306{ 1307#ifdef AH_DEBUG 1308#define NUM_DMA_DEBUG_REGS 8 1309#define NUM_QUEUES 10 1310 1311 u_int32_t val[NUM_DMA_DEBUG_REGS]; 1312 int qcu_offset = 0, dcu_offset = 0; 1313 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1314 int i, j, k; 1315 int16_t nfarray[HAL_NUM_NF_READINGS]; 1316#ifdef ATH_NF_PER_CHAN 1317 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 1318#endif /* ATH_NF_PER_CHAN */ 1319 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan); 1320 1321 /* selecting DMA OBS 8 */ 1322 OS_REG_WRITE(ah, AR_MACMISC, 1323 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1324 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1325 1326 ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1327 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1328 if (i % 4 == 0) { 1329 ath_hal_printf(ah, "\n"); 1330 } 1331 1332 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1333 ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1334 } 1335 1336 ath_hal_printf(ah, "\n\n"); 1337 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1338 1339 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1340 if (i == 8) { 1341 /* only 8 QCU entries in val[0] */ 1342 qcu_offset = 0; 1343 qcu_base++; 1344 } 1345 1346 if (i == 6) { 1347 /* only 6 DCU entries in val[4] */ 1348 dcu_offset = 0; 1349 dcu_base++; 1350 } 1351 1352 ath_hal_printf(ah, 1353 "%2d %2x %1x %2x %2x\n", 1354 i, 1355 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1356 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1357 val[2] & (0x7 << (i * 3)) >> (i * 3), 1358 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1359 } 1360 1361 ath_hal_printf(ah, "\n"); 1362 ath_hal_printf(ah, 1363 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1364 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1365 ath_hal_printf(ah, 1366 "qcu_complete state: %2x dcu_complete state: %2x\n", 1367 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1368 ath_hal_printf(ah, 1369 "dcu_arb state: %2x dcu_fp state: %2x\n", 1370 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1371 ath_hal_printf(ah, 1372 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1373 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1374 ath_hal_printf(ah, 1375 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1376 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1377 ath_hal_printf(ah, 1378 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1379 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1380 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1381 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1382 1383 ar9300_upload_noise_floor(ah, 1, nfarray); 1384 ath_hal_printf(ah, "2G:\n"); 1385 ath_hal_printf(ah, "Min CCA Out:\n"); 1386 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1387 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1388 nfarray[0], nfarray[1], nfarray[2]); 1389 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1390 nfarray[3], nfarray[4], nfarray[5]); 1391 1392 ar9300_upload_noise_floor(ah, 0, nfarray); 1393 ath_hal_printf(ah, "5G:\n"); 1394 ath_hal_printf(ah, "Min CCA Out:\n"); 1395 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1396 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1397 nfarray[0], nfarray[1], nfarray[2]); 1398 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1399 nfarray[3], nfarray[4], nfarray[5]); 1400 1401 for (i = 0; i < HAL_NUM_NF_READINGS; i++) { 1402 ath_hal_printf(ah, "%s Chain %d NF History:\n", 1403 ((i < 3) ? "Control " : "Extension "), i%3); 1404 for (j = 0, k = h->base.curr_index; 1405 j < HAL_NF_CAL_HIST_LEN_FULL; 1406 j++, k++) { 1407 ath_hal_printf(ah, "Element %d: %d\n", 1408 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1409 } 1410 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1411 } 1412 1413 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1414 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1415 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1416 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1417 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1418 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1419 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1420 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1421 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1422 MS(reg, AR_PHY_DESIRED_SZ_ADC), 1423 MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1424 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1425 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1426 MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1427 MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1428 reg = OS_REG_READ(ah, AR_PHY_AGC); 1429 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1430 MS(reg, AR_PHY_AGC_COARSE_HIGH), 1431 MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1432 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1433 MS(reg, AR_PHY_AGC_COARSE_LOW), 1434 MS(reg, AR_PHY_AGC_COARSE_LOW)); 1435 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1436 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1437 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1438 reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1439 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1440 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1441 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1442 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1443 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1444 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1445 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1446 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1447 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1448 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1449 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1450 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1451 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1452 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1453 1454 1455 /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1456 reg = OS_REG_READ(ah, 0xa360); 1457 reg &= ~0x00800000; 1458 OS_REG_WRITE(ah, 0xa360, reg); 1459 1460 /* Step 2a: Set register 0xa364 to 0x1000 */ 1461 reg = 0x1000; 1462 OS_REG_WRITE(ah, 0xa364, reg); 1463 1464 /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1465 reg = OS_REG_READ(ah, 0x9c20); 1466 reg &= 0x0003ffff; 1467 ath_hal_printf(ah, 1468 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1469 __func__, reg); 1470 1471 /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1472 reg = OS_REG_READ(ah, 0xa360); 1473 reg &= ~0x00800000; 1474 OS_REG_WRITE(ah, 0xa360, reg); 1475 1476 /* Step 2b: Set register 0xa364 to 0x1400 */ 1477 reg = 0x1400; 1478 OS_REG_WRITE(ah, 0xa364, reg); 1479 1480 /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1481 reg = OS_REG_READ(ah, 0x9c20); 1482 reg &= 0x0003ffff; 1483 ath_hal_printf(ah, 1484 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1485 __func__, reg); 1486 1487 /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1488 reg = OS_REG_READ(ah, 0xa360); 1489 reg &= ~0x00800000; 1490 OS_REG_WRITE(ah, 0xa360, reg); 1491 1492 /* Step 2c: Set register 0xa364 to 0x3C00 */ 1493 reg = 0x3c00; 1494 OS_REG_WRITE(ah, 0xa364, reg); 1495 1496 /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1497 reg = OS_REG_READ(ah, 0x9c20); 1498 reg &= 0x0003ffff; 1499 ath_hal_printf(ah, 1500 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1501 __func__, reg); 1502 1503 /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1504 reg = OS_REG_READ(ah, 0xa360); 1505 reg &= ~0x001040000; 1506 OS_REG_WRITE(ah, 0xa360, reg); 1507 1508 /* Step 2d: Set register 0xa364 to 0x5005D */ 1509 reg = 0x5005D; 1510 OS_REG_WRITE(ah, 0xa364, reg); 1511 1512 /* Step 3d: Read bits 17:0 of register 0xa368 */ 1513 reg = OS_REG_READ(ah, 0xa368); 1514 reg &= 0x0003ffff; 1515 ath_hal_printf(ah, 1516 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1517 __func__, reg); 1518 1519 /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1520 reg = OS_REG_READ(ah, 0xa360); 1521 reg &= ~0x001040000; 1522 OS_REG_WRITE(ah, 0xa360, reg); 1523 1524 /* Step 2e: Set register 0xa364 to 0x7005D */ 1525 reg = 0x7005D; 1526 OS_REG_WRITE(ah, 0xa364, reg); 1527 1528 /* Step 3e: Read bits 17:0 of register 0xa368 */ 1529 reg = OS_REG_READ(ah, 0xa368); 1530 reg &= 0x0003ffff; 1531 ath_hal_printf(ah, 1532 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1533 __func__, reg); 1534 1535 /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1536 reg = OS_REG_READ(ah, 0xa360); 1537 reg &= ~0x001000000; 1538 reg |= 0x40000; 1539 OS_REG_WRITE(ah, 0xa360, reg); 1540 1541 /* Step 2f: Set register 0xa364 to 0x3005D */ 1542 reg = 0x3005D; 1543 OS_REG_WRITE(ah, 0xa364, reg); 1544 1545 /* Step 3f: Read bits 17:0 of register 0xa368 */ 1546 reg = OS_REG_READ(ah, 0xa368); 1547 reg &= 0x0003ffff; 1548 ath_hal_printf(ah, 1549 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1550 __func__, reg); 1551 1552 /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1553 reg = OS_REG_READ(ah, 0xa360); 1554 reg &= ~0x001000000; 1555 reg |= 0x40000; 1556 OS_REG_WRITE(ah, 0xa360, reg); 1557 1558 /* Step 2g: Set register 0xa364 to 0x6005D */ 1559 reg = 0x6005D; 1560 OS_REG_WRITE(ah, 0xa364, reg); 1561 1562 /* Step 3g: Read bits 17:0 of register 0xa368 */ 1563 reg = OS_REG_READ(ah, 0xa368); 1564 reg &= 0x0003ffff; 1565 ath_hal_printf(ah, 1566 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1567 __func__, reg); 1568#endif /* AH_DEBUG */ 1569} 1570 1571/* 1572 * Return the busy for rx_frame, rx_clear, and tx_frame 1573 */ 1574u_int32_t 1575ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1576 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1577{ 1578 struct ath_hal_9300 *ahp = AH9300(ah); 1579 u_int32_t good = 1; 1580 1581 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1582 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1583 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1584 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1585 1586 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1587 /* 1588 * Cycle counter wrap (or initial call); it's not possible 1589 * to accurately calculate a value because the registers 1590 * right shift rather than wrap--so punt and return 0. 1591 */ 1592 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1593 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1594 good = 0; 1595 } else { 1596 u_int32_t cc_d = cc - ahp->ah_cycles; 1597 u_int32_t rc_d = rc - ahp->ah_rx_clear; 1598 u_int32_t rf_d = rf - ahp->ah_rx_frame; 1599 u_int32_t tf_d = tf - ahp->ah_tx_frame; 1600 1601 if (cc_d != 0) { 1602 *rxc_pcnt = rc_d * 100 / cc_d; 1603 *rxf_pcnt = rf_d * 100 / cc_d; 1604 *txf_pcnt = tf_d * 100 / cc_d; 1605 } else { 1606 good = 0; 1607 } 1608 } 1609 1610 ahp->ah_cycles = cc; 1611 ahp->ah_rx_frame = rf; 1612 ahp->ah_rx_clear = rc; 1613 ahp->ah_tx_frame = tf; 1614 1615 return good; 1616} 1617 1618/* 1619 * Return approximation of extension channel busy over an time interval 1620 * 0% (clear) -> 100% (busy) 1621 * -1 for invalid estimate 1622 */ 1623uint32_t 1624ar9300_get_11n_ext_busy(struct ath_hal *ah) 1625{ 1626 /* 1627 * Overflow condition to check before multiplying to get % 1628 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1629 */ 1630#define OVERFLOW_LIMIT 0x28F5C28 1631#define ERROR_CODE -1 1632 1633 struct ath_hal_9300 *ahp = AH9300(ah); 1634 u_int32_t busy = 0; /* percentage */ 1635 int8_t busyper = 0; 1636 u_int32_t cycle_count, ctl_busy, ext_busy; 1637 1638 /* cycle_count will always be the first to wrap; therefore, read it last 1639 * This sequence of reads is not atomic, and MIB counter wrap 1640 * could happen during it ? 1641 */ 1642 ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1643 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1644 cycle_count = OS_REG_READ(ah, AR_CCCNT); 1645 1646 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1647 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1648 { 1649 /* 1650 * Cycle counter wrap (or initial call); it's not possible 1651 * to accurately calculate a value because the registers 1652 * right shift rather than wrap--so punt and return 0. 1653 */ 1654 busyper = ERROR_CODE; 1655 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1656 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1657 } else { 1658 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1659 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1660 1661 /* 1662 * Compute extension channel busy percentage 1663 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1664 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1665 * Will never happen, since (ext_busy_delta < cycle_delta) always, 1666 * and shift necessitated by large ext_busy_delta. 1667 * Due to timing difference to read the registers and counter overflow, 1668 * it may still happen that cycle_delta >> 7 = 0. 1669 * 1670 */ 1671 if (cycle_delta) { 1672 if (ext_busy_delta > OVERFLOW_LIMIT) { 1673 if (cycle_delta >> 7) { 1674 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1675 } else { 1676 busyper = ERROR_CODE; 1677 } 1678 } else { 1679 busy = (ext_busy_delta * 100) / cycle_delta; 1680 } 1681 } else { 1682 busyper = ERROR_CODE; 1683 } 1684 1685 if (busy > 100) { 1686 busy = 100; 1687 } 1688 if ( busyper != ERROR_CODE ) { 1689 busyper = busy; 1690 } 1691 } 1692 1693 ahp->ah_cycle_count = cycle_count; 1694 ahp->ah_ctl_busy = ctl_busy; 1695 ahp->ah_ext_busy = ext_busy; 1696 1697 return busyper; 1698#undef OVERFLOW_LIMIT 1699#undef ERROR_CODE 1700} 1701 1702/* BB Panic Watchdog declarations */ 1703#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1704#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1705 1706void 1707ar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1708{ 1709#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1710 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1711 u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms; 1712 u_int32_t val, idle_count; 1713 1714 if (idle_tmo_ms != 0) { 1715 /* enable IRQ, disable chip-reset for BB panic */ 1716 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1717 AR_PHY_BB_PANIC_CNTL2_MASK; 1718 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1719 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1720 /* bound limit to 10 secs */ 1721 if (idle_tmo_ms > 10000) { 1722 idle_tmo_ms = 10000; 1723 } 1724 if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) { 1725 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1726 } else { 1727 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1728 } 1729 /* 1730 * enable panic in non-IDLE mode, 1731 * disable in IDLE mode, 1732 * set idle time-out 1733 */ 1734 1735 // EV92527 : Enable IDLE mode panic 1736 1737 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1738 AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1739 AR_PHY_BB_PANIC_IDLE_ENABLE | 1740 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1741 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1742 } else { 1743 /* disable IRQ, disable chip-reset for BB panic */ 1744 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1745 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1746 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1747 /* disable panic in non-IDLE mode, disable in IDLE mode */ 1748 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1749 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1750 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1751 } 1752 1753 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1754 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1755#undef HAL_BB_PANIC_IDLE_TIME_OUT 1756} 1757 1758 1759void 1760ar9300_handle_bb_panic(struct ath_hal *ah) 1761{ 1762 u_int32_t status; 1763 /* 1764 * we want to avoid printing in ISR context so we save 1765 * panic watchdog status to be printed later in DPC context 1766 */ 1767 AH9300(ah)->ah_bb_panic_last_status = status = 1768 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1769 /* 1770 * panic watchdog timer should reset on status read 1771 * but to make sure we write 0 to the watchdog status bit 1772 */ 1773 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1774} 1775 1776int 1777ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1778{ 1779 bb_panic->status = AH9300(ah)->ah_bb_panic_last_status; 1780 1781 /* 1782 * For signature 04000539 do not print anything. 1783 * This is a very common occurence as a compromise between 1784 * BB Panic and AH_FALSE detects (EV71009). It indicates 1785 * radar hang, which can be cleared by reprogramming 1786 * radar related register and does not requre a chip reset 1787 */ 1788 1789 /* Suppress BB Status mesg following signature */ 1790 switch (bb_panic->status) { 1791 case 0x04000539: 1792 case 0x04008009: 1793 case 0x04000b09: 1794 case 0x1300000a: 1795 return -1; 1796 } 1797 1798 bb_panic->tsf = ar9300_get_tsf32(ah); 1799 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1800 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1801 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1802 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1803 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1804 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1805 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1806 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1807 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1808 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1809 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1810 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1811 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1812 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1813 &bb_panic->rxc_pcnt, 1814 &bb_panic->rxf_pcnt, 1815 &bb_panic->txf_pcnt); 1816 1817 if (ah->ah_config.ath_hal_show_bb_panic) { 1818 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1819 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1820 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1821 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1822 bb_panic->wd, bb_panic->det, bb_panic->rdar, 1823 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1824 bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1825 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1826 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1827 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1828 bb_panic->phy_gen_ctrl); 1829 if (bb_panic->cycles) { 1830 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1831 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1832 bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1833 } 1834 ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1835 } 1836 1837 return 0; //The returned data will be stored for athstats to retrieve it 1838} 1839 1840/* set the reason for HAL reset */ 1841void 1842ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1843{ 1844 AH9300(ah)->ah_reset_reason = resetreason; 1845} 1846 1847/* 1848 * Configure 20/40 operation 1849 * 1850 * 20/40 = joint rx clear (control and extension) 1851 * 20 = rx clear (control) 1852 * 1853 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1854 * when changing from 20/40 => 20 only 1855 */ 1856void 1857ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1858{ 1859 u_int32_t macmode; 1860 1861 /* Configure MAC for 20/40 operation */ 1862 if (mode == HAL_HT_MACMODE_2040 && 1863 !ah->ah_config.ath_hal_cwm_ignore_ext_cca) { 1864 macmode = AR_2040_JOINED_RX_CLEAR; 1865 } else { 1866 macmode = 0; 1867 } 1868 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1869} 1870 1871/* 1872 * Get Rx clear (control/extension channel) 1873 * 1874 * Returns active low (busy) for ctrl/ext channel 1875 * Owl 2.0 1876 */ 1877HAL_HT_RXCLEAR 1878ar9300_get_11n_rx_clear(struct ath_hal *ah) 1879{ 1880 HAL_HT_RXCLEAR rxclear = 0; 1881 u_int32_t val; 1882 1883 val = OS_REG_READ(ah, AR_DIAG_SW); 1884 1885 /* control channel */ 1886 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1887 rxclear |= HAL_RX_CLEAR_CTL_LOW; 1888 } 1889 /* extension channel */ 1890 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1891 rxclear |= HAL_RX_CLEAR_EXT_LOW; 1892 } 1893 return rxclear; 1894} 1895 1896/* 1897 * Set Rx clear (control/extension channel) 1898 * 1899 * Useful for forcing the channel to appear busy for 1900 * debugging/diagnostics 1901 * Owl 2.0 1902 */ 1903void 1904ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1905{ 1906 /* control channel */ 1907 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1908 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1909 } else { 1910 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1911 } 1912 /* extension channel */ 1913 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1914 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1915 } else { 1916 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1917 } 1918} 1919 1920 1921/* 1922 * HAL support code for force ppm tracking workaround. 1923 */ 1924 1925u_int32_t 1926ar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1927{ 1928 u_int32_t retval; 1929 u_int32_t off1; 1930 u_int32_t off2; 1931 1932 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1933 off1 = 0x2000; 1934 off2 = 0x1000; 1935 } else { 1936 off1 = 0x1000; 1937 off2 = 0x2000; 1938 } 1939 1940 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1941 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1942 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1943 1944 return retval; 1945} 1946 1947u_int32_t 1948ar9300_ppm_force(struct ath_hal *ah) 1949{ 1950 u_int32_t data_fine; 1951 u_int32_t data4; 1952 //u_int32_t off1; 1953 //u_int32_t off2; 1954 HAL_BOOL signed_val = AH_FALSE; 1955 1956// if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1957// off1 = 0x2000; 1958// off2 = 0x1000; 1959// } else { 1960// off1 = 0x1000; 1961// off2 = 0x2000; 1962// } 1963 data_fine = 1964 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 1965 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 1966 1967 /* 1968 * bit [11-0] is new ppm value. bit 11 is the signed bit. 1969 * So check value from bit[10:0]. 1970 * Now get the abs val of the ppm value read in bit[0:11]. 1971 * After that do bound check on abs value. 1972 * if value is off limit, CAP the value and and restore signed bit. 1973 */ 1974 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 1975 { 1976 /* get the positive value */ 1977 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1978 signed_val = AH_TRUE; 1979 } 1980 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 1981 { 1982 HALDEBUG(ah, HAL_DEBUG_REGIO, 1983 "%s Correcting ppm out of range %x\n", 1984 __func__, (data_fine & 0x7ff)); 1985 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 1986 } 1987 /* 1988 * Restore signed value if changed above. 1989 * Use typecast to avoid compilation errors 1990 */ 1991 if (signed_val) { 1992 data_fine = (-(int32_t)data_fine) & 1993 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1994 } 1995 1996 /* write value */ 1997 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 1998 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 1999 OS_REG_WRITE(ah, AR_PHY_TIMING2, 2000 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 2001 2002 return data_fine; 2003} 2004 2005void 2006ar9300_ppm_un_force(struct ath_hal *ah) 2007{ 2008 u_int32_t data4; 2009 2010 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 2011 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 2012} 2013 2014u_int32_t 2015ar9300_ppm_arm_trigger(struct ath_hal *ah) 2016{ 2017 u_int32_t val; 2018 u_int32_t ret; 2019 2020 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 2021 ret = OS_REG_READ(ah, AR_TSF_L32); 2022 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 2023 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 2024 2025 /* return low word of TSF at arm time */ 2026 return ret; 2027} 2028 2029int 2030ar9300_ppm_get_trigger(struct ath_hal *ah) 2031{ 2032 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 2033 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 2034 { 2035 /* has not triggered yet, return AH_FALSE */ 2036 return 0; 2037 } 2038 2039 /* else triggered, return AH_TRUE */ 2040 return 1; 2041} 2042 2043void 2044ar9300_mark_phy_inactive(struct ath_hal *ah) 2045{ 2046 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 2047} 2048 2049/* DEBUG */ 2050u_int32_t 2051ar9300_ppm_get_force_state(struct ath_hal *ah) 2052{ 2053 return 2054 OS_REG_READ(ah, AR_PHY_TIMING2) & 2055 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 2056} 2057 2058/* 2059 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 2060 */ 2061HAL_BOOL 2062ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) 2063{ 2064 /* 2065 * XXX FreeBSD todo: reimplement this 2066 */ 2067#if 0 2068 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2069 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2070 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2071 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2072 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 2073 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 2074 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 2075 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 2076#endif 2077 return AH_FALSE; 2078} 2079 2080void 2081ar9300_clear_mib_counters(struct ath_hal *ah) 2082{ 2083 u_int32_t reg_val; 2084 2085 reg_val = OS_REG_READ(ah, AR_MIBC); 2086 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 2087 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 2088} 2089 2090 2091/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 2092HAL_BOOL 2093ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 2094{ 2095 struct ath_hal_9300 *ahp = AH9300(ah); 2096 HAL_CHANNEL_INTERNAL *ichan = 2097 ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 2098 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan); 2099 u_int32_t tmp = 0; 2100 2101 if (enable) { 2102 if (ahp->ah_rifs_enabled == AH_TRUE) { 2103 return AH_TRUE; 2104 } 2105 2106 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 2107 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2108 ahp->ah_rifs_reg[1]); 2109 2110 ahp->ah_rifs_enabled = AH_TRUE; 2111 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 2112 } else { 2113 if (ahp->ah_rifs_enabled == AH_TRUE) { 2114 ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 2115 AR_PHY_SEARCH_START_DELAY); 2116 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 2117 } 2118 /* Change rifs init delay to 0 */ 2119 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2120 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 2121 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 2122 if (is_chan_2g) { 2123 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2124 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 2125 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 2126 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 2127 } 2128 } else { 2129 if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2130 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 2131 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 2132 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 2133 } 2134 } 2135 2136 ahp->ah_rifs_enabled = AH_FALSE; 2137 } 2138 return AH_TRUE; 2139 2140} /* ar9300_set_rifs_delay () */ 2141 2142/* Set the current RIFS Rx setting */ 2143HAL_BOOL 2144ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2145{ 2146 /* Non-Owl 11n chips */ 2147 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2148 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2149 return ar9300_set_rifs_delay(ah, enable); 2150 } 2151 return AH_FALSE; 2152 } 2153 2154 return AH_TRUE; 2155} /* ar9300_set_11n_rx_rifs () */ 2156 2157static hal_mac_hangs_t 2158ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2159 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2160{ 2161 int i = 0; 2162 hal_mac_hangs_t found_hangs = 0; 2163 2164 if (hangs & dcu_chain_state) { 2165 for (i = 0; i < 6; i++) { 2166 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2167 hang_check.dcu_chain_state) 2168 { 2169 found_hangs |= dcu_chain_state; 2170 *dcu_chain = i; 2171 } 2172 } 2173 for (i = 0; i < 4; i++) { 2174 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2175 hang_check.dcu_chain_state) 2176 { 2177 found_hangs |= dcu_chain_state; 2178 *dcu_chain = i + 6; 2179 } 2180 } 2181 } 2182 2183 if (hangs & dcu_complete_state) { 2184 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2185 found_hangs |= dcu_complete_state; 2186 } 2187 } 2188 2189 return found_hangs; 2190 2191} /* end - ar9300_compare_dbg_hang */ 2192 2193#define NUM_STATUS_READS 50 2194HAL_BOOL 2195ar9300_detect_mac_hang(struct ath_hal *ah) 2196{ 2197 struct ath_hal_9300 *ahp = AH9300(ah); 2198 mac_dbg_regs_t mac_dbg; 2199 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2200 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2201 int i = 0; 2202 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2203 2204 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2205 return AH_FALSE; 2206 } 2207 2208 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2209 2210 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2211 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2212 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2213 2214 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2215 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2216 mac_dbg.dma_dbg_6); 2217 2218 if (hang_sig1 != 2219 ar9300_compare_dbg_hang(ah, mac_dbg, 2220 hang_sig1_val, hang_sig1, &dcu_chain)) 2221 { 2222 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2223 return AH_FALSE; 2224 } 2225 2226 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2227 shift_val *= 5; 2228 2229 for (i = 1; i <= NUM_STATUS_READS; i++) { 2230 if (dcu_chain < 6) { 2231 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2232 current_dcu_chain_state = 2233 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2234 } else { 2235 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2236 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2237 } 2238 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2239 2240 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2241 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2242 return AH_FALSE; 2243 } 2244 } 2245 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2246 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2247 ahp->ah_hang[MAC_HANG_SIG1]++; 2248 return AH_TRUE; 2249 2250} /* end - ar9300_detect_mac_hang */ 2251 2252/* Determine if the baseband is hung by reading the Observation Bus Register */ 2253HAL_BOOL 2254ar9300_detect_bb_hang(struct ath_hal *ah) 2255{ 2256#define N(a) (sizeof(a) / sizeof(a[0])) 2257 struct ath_hal_9300 *ahp = AH9300(ah); 2258 u_int32_t hang_sig = 0; 2259 int i = 0; 2260 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2261 * 2262 * 4 known BB hang signatures - 2263 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2264 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2265 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2266 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2267 * Rx State (bits 20-24) is 0x7. 2268 */ 2269 hal_hw_hang_check_t hang_list [] = 2270 { 2271 /* Offset Reg Value Reg Mask Hang Offset */ 2272 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2273 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2274 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2275 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2276 }; 2277 2278 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2279 HAL_DFS_BB_HANG_WAR | 2280 HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2281 return AH_FALSE; 2282 } 2283 2284 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2285 for (i = 1; i <= NUM_STATUS_READS; i++) { 2286 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2287 return AH_FALSE; 2288 } 2289 } 2290 2291 for (i = 0; i < N(hang_list); i++) { 2292 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2293 ahp->ah_hang[hang_list[i].hang_offset]++; 2294 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2295 "sig3count=%d sig4count=%d\n", __func__, 2296 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2297 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2298 return AH_TRUE; 2299 } 2300 } 2301 2302 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2303 "<0x806c>=0x%x\n", __func__, hang_sig); 2304 2305 return AH_FALSE; 2306 2307#undef N 2308} /* end - ar9300_detect_bb_hang () */ 2309 2310#undef NUM_STATUS_READS 2311 2312HAL_STATUS 2313ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2314{ 2315 struct ath_hal_9300 *ahp = AH9300(ah); 2316 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2317 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 2318 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2319 u_int16_t ant_config; 2320 u_int32_t hal_num_ant_config; 2321 2322 hal_num_ant_config = IS_CHAN_2GHZ(ichan) ? 2323 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz; 2324 2325 if (cfg < hal_num_ant_config) { 2326 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2327 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2328 return HAL_OK; 2329 } 2330 } 2331 2332 return HAL_EINVAL; 2333} 2334 2335/* 2336 * Functions to get/set DCS mode 2337 */ 2338void 2339ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2340{ 2341 AH9300(ah)->ah_dcs_enable = mode; 2342} 2343 2344u_int32_t 2345ar9300_get_dcs_mode(struct ath_hal *ah) 2346{ 2347 return AH9300(ah)->ah_dcs_enable; 2348} 2349 2350#if ATH_BT_COEX 2351void 2352ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2353{ 2354 struct ath_hal_9300 *ahp = AH9300(ah); 2355 2356 ahp->ah_bt_module = btinfo->bt_module; 2357 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2358 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2359 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2360 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2361 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2362 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2363 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2364} 2365 2366void 2367ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2368{ 2369 struct ath_hal_9300 *ahp = AH9300(ah); 2370 HAL_BOOL rx_clear_polarity; 2371 2372 /* 2373 * For Kiwi and Osprey, the polarity of rx_clear is active high. 2374 * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2375 */ 2376 rx_clear_polarity = !btconf->bt_rxclear_polarity; 2377 2378 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2379 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2380 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2381 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2382 SM(btconf->bt_mode, AR_BT_MODE) | 2383 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2384 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2385 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2386 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2387 2388 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2389 2390 if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2391 /* Enable ACK to go out even though BT has higher priority. */ 2392 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2393 } 2394} 2395 2396void 2397ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2398{ 2399 struct ath_hal_9300 *ahp = AH9300(ah); 2400 2401 /* clear the old value, then set the new value */ 2402 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2403 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2404} 2405 2406void 2407ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2408{ 2409 struct ath_hal_9300 *ahp = AH9300(ah); 2410 2411 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2412 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2413 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2414 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2415 2416 switch (stomp_type) { 2417 case HAL_BT_COEX_STOMP_ALL: 2418 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2419 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2420 break; 2421 case HAL_BT_COEX_STOMP_LOW: 2422 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2423 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2424 break; 2425 case HAL_BT_COEX_STOMP_ALL_FORCE: 2426 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2427 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2428 break; 2429 case HAL_BT_COEX_STOMP_LOW_FORCE: 2430 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2431 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2432 break; 2433 case HAL_BT_COEX_STOMP_NONE: 2434 case HAL_BT_COEX_NO_STOMP: 2435 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2436 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2437 break; 2438 default: 2439 /* There is a force_weight from registry */ 2440 ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2441 ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2442 break; 2443 } 2444} 2445 2446void 2447ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2448{ 2449 struct ath_hal_9300 *ahp = AH9300(ah); 2450 2451 /* clear the old value, then set the new value */ 2452 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2453 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2454} 2455 2456static void 2457ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2458{ 2459 struct ath_hal_9300 *ahp = AH9300(ah); 2460#if ATH_ANT_DIV_COMB 2461 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2462 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2463#endif 2464 2465 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2466 { 2467 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2468 { 2469 /* Config antenna diversity */ 2470#if ATH_ANT_DIV_COMB 2471 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2472#endif 2473 } 2474 } 2475} 2476 2477 2478void 2479ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2480 u_int32_t value) 2481{ 2482 struct ath_hal_9300 *ahp = AH9300(ah); 2483 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2484 2485 switch (type) { 2486 case HAL_BT_COEX_SET_ACK_PWR: 2487 if (value) { 2488 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2489 } else { 2490 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2491 } 2492 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2493 ahpriv->ah_extraTxPow, 0); 2494 break; 2495 2496 case HAL_BT_COEX_ANTENNA_DIVERSITY: 2497 if (AR_SREV_POSEIDON(ah)) { 2498 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2499 if (value) { 2500 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2501 } 2502 else { 2503 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2504 } 2505 ar9300_bt_coex_antenna_diversity(ah, value); 2506 } 2507 break; 2508 case HAL_BT_COEX_LOWER_TX_PWR: 2509 if (value) { 2510 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2511 } 2512 else { 2513 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2514 } 2515 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2516 ahpriv->ah_extraTxPow, 0); 2517 break; 2518#if ATH_SUPPORT_MCI 2519 case HAL_BT_COEX_MCI_MAX_TX_PWR: 2520 if ((ah->ah_config.ath_hal_mci_config & 2521 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2522 { 2523 if (value) { 2524 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2525 ahp->ah_mci_concur_tx_en = AH_TRUE; 2526 } 2527 else { 2528 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2529 ahp->ah_mci_concur_tx_en = AH_FALSE; 2530 } 2531 ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2532 ahpriv->ah_extraTxPow, 0); 2533 } 2534 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2535 ahp->ah_mci_concur_tx_en); 2536 break; 2537 case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2538 if (value) { 2539 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2540 } 2541 else { 2542 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2543 } 2544 break; 2545#endif 2546 default: 2547 break; 2548 } 2549} 2550 2551void 2552ar9300_bt_coex_disable(struct ath_hal *ah) 2553{ 2554 struct ath_hal_9300 *ahp = AH9300(ah); 2555 2556 /* Always drive rx_clear_external output as 0 */ 2557 ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select, 2558 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2559 2560 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2561 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2562 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2563 } 2564 2565 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2566 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2567 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2568 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2569 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2570 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2571 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2572 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2573 2574 ahp->ah_bt_coex_enabled = AH_FALSE; 2575} 2576 2577int 2578ar9300_bt_coex_enable(struct ath_hal *ah) 2579{ 2580 struct ath_hal_9300 *ahp = AH9300(ah); 2581 2582 /* Program coex mode and weight registers to actually enable coex */ 2583 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2584 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2585 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2586 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2587 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2588 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2589 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2590 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2591 2592 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2593 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2594 } else { 2595 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2596 } 2597 2598 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2599 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2600 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2601 } else { 2602 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2603 } 2604 2605 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2606 /* For 3-wire, configure the desired GPIO port for rx_clear */ 2607 ath_hal_gpioCfgOutput(ah, 2608 ahp->ah_wlan_active_gpio_select, 2609 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2610 } 2611 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2612 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2613 { 2614 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2615 ath_hal_gpioCfgOutput(ah, 2616 ahp->ah_wlan_active_gpio_select, 2617 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2618 } 2619 2620 /* 2621 * Enable a weak pull down on BT_ACTIVE. 2622 * When BT device is disabled, BT_ACTIVE might be floating. 2623 */ 2624 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2625 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2626 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2627 2628 ahp->ah_bt_coex_enabled = AH_TRUE; 2629 2630 return 0; 2631} 2632 2633u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2634{ 2635 return 0; 2636} 2637 2638u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2639{ 2640 return bOn; 2641} 2642 2643void 2644ar9300_init_bt_coex(struct ath_hal *ah) 2645{ 2646 struct ath_hal_9300 *ahp = AH9300(ah); 2647 2648 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2649 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2650 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2651 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2652 2653 /* 2654 * Set input mux for bt_prority_async and 2655 * bt_active_async to GPIO pins 2656 */ 2657 OS_REG_RMW_FIELD(ah, 2658 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2659 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2660 ahp->ah_bt_active_gpio_select); 2661 OS_REG_RMW_FIELD(ah, 2662 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2663 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2664 ahp->ah_bt_priority_gpio_select); 2665 2666 /* Configure the desired GPIO ports for input */ 2667 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2668 ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select); 2669 2670 if (ahp->ah_bt_coex_enabled) { 2671 ar9300_bt_coex_enable(ah); 2672 } else { 2673 ar9300_bt_coex_disable(ah); 2674 } 2675 } 2676 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2677 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2678 { 2679 /* 2-wire */ 2680 if (ahp->ah_bt_coex_enabled) { 2681 /* Connect bt_active_async to baseband */ 2682 OS_REG_CLR_BIT(ah, 2683 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2684 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2685 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2686 OS_REG_SET_BIT(ah, 2687 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2688 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2689 2690 /* 2691 * Set input mux for bt_prority_async and 2692 * bt_active_async to GPIO pins 2693 */ 2694 OS_REG_RMW_FIELD(ah, 2695 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2696 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2697 ahp->ah_bt_active_gpio_select); 2698 2699 /* Configure the desired GPIO ports for input */ 2700 ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2701 2702 /* Enable coexistence on initialization */ 2703 ar9300_bt_coex_enable(ah); 2704 } 2705 } 2706#if ATH_SUPPORT_MCI 2707 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2708 if (ahp->ah_bt_coex_enabled) { 2709 ar9300_mci_bt_coex_enable(ah); 2710 } 2711 else { 2712 ar9300_mci_bt_coex_disable(ah); 2713 } 2714 } 2715#endif /* ATH_SUPPORT_MCI */ 2716} 2717 2718#endif /* ATH_BT_COEX */ 2719 2720HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2721{ 2722 u_int32_t val; 2723 int wasp_mm_rev; 2724 2725#define AR_SOC_RST_REVISION_ID 0xB8060090 2726#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2727 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2728 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2729 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2730#undef AR_SOC_RST_REVISION_ID 2731#undef REG_READ 2732 2733 /* 2734 * Azimuth (ProxySTA) Mode is only supported correctly by 2735 * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2736 * 2737 * Enable this feature for Scorpion at this time. The silicon 2738 * still needs to be validated. 2739 */ 2740 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2741 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2742 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2743 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2744 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2745 wasp_mm_rev >= 0 /* 1 */)))) 2746 { 2747 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2748 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2749 __func__, AH_PRIVATE((ah))->ah_macVersion, 2750 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2751 return HAL_ENOTSUPP; 2752 } 2753 2754 OS_REG_WRITE(ah, 2755 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2756 2757 /* turn on mode bit[24] for proxy sta */ 2758 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2759 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2760 2761 val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2762 if (enable) { 2763 val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2764 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2765 AR_AZIMUTH_BA_USES_AD1; 2766 /* turn off filter pass hold (bit 9) */ 2767 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2768 } else { 2769 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2770 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2771 AR_AZIMUTH_BA_USES_AD1); 2772 } 2773 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2774 2775 /* enable promiscous mode */ 2776 OS_REG_WRITE(ah, AR_RX_FILTER, 2777 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2778 /* enable promiscous in azimuth mode */ 2779 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2780 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2781 2782 /* turn on filter pass hold (bit 9) */ 2783 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2784 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2785 2786 return HAL_OK; 2787} 2788 2789#if 0 2790void ar9300_mat_enable(struct ath_hal *ah, int enable) 2791{ 2792 /* 2793 * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2794 * mitigation and turn on key search always for better performance. 2795 */ 2796 struct ath_hal_9300 *ahp = AH9300(ah); 2797 struct ath_hal_private *ap = AH_PRIVATE(ah); 2798 2799 ahp->ah_intr_mitigation_rx = !enable; 2800 if (ahp->ah_intr_mitigation_rx) { 2801 /* 2802 * Enable Interrupt Mitigation for Rx. 2803 * If no build-specific limits for the rx interrupt mitigation 2804 * timer have been specified, use conservative defaults. 2805 */ 2806 #ifndef AH_RIMT_VAL_LAST 2807 #define AH_RIMT_LAST_MICROSEC 500 2808 #endif 2809 #ifndef AH_RIMT_VAL_FIRST 2810 #define AH_RIMT_FIRST_MICROSEC 2000 2811 #endif 2812 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2813 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2814 } else { 2815 OS_REG_WRITE(ah, AR_RIMT, 0); 2816 } 2817 2818 ahp->ah_enable_keysearch_always = !!enable; 2819 ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always); 2820} 2821#endif 2822 2823void ar9300_enable_tpc(struct ath_hal *ah) 2824{ 2825 u_int32_t val = 0; 2826 2827 ah->ah_config.ath_hal_desc_tpc = 1; 2828 2829 /* Enable TPC */ 2830 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2831 2832 /* 2833 * Disable per chain power reduction since we are already 2834 * accounting for this in our calculations 2835 */ 2836 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2837 if (AR_SREV_WASP(ah)) { 2838 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2839 val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2840 } else { 2841 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2842 val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2843 } 2844} 2845 2846 2847/* 2848 * ar9300_force_tsf_sync 2849 * This function forces the TSF sync to the given bssid, this is implemented 2850 * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2851 * mode of operation, where we sync the TSF to RootAP TSF values 2852 */ 2853void 2854ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2855 u_int16_t assoc_id) 2856{ 2857 ar9300_set_operating_mode(ah, HAL_M_STA); 2858 ar9300_write_associd(ah, bssid, assoc_id); 2859} 2860 2861void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2862{ 2863 struct ath_hal_9300 *ahp = AH9300(ah); 2864 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2865 u_int32_t temp_powertx_rate9_reg_val; 2866 int8_t olpc_power_offset = 0; 2867 int8_t tmp_olpc_val = 0; 2868 HAL_RSSI_TX_POWER old_greentx_status; 2869 u_int8_t target_power_val_t[ar9300_rate_size]; 2870 int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2871 2872 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2873 !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2874 return; 2875 } 2876 2877 old_greentx_status = AH9300(ah)->green_tx_status; 2878 if (ahp->ah_hw_green_tx_enable) { 2879 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2880 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2881 } else { 2882 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2883 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2884 } 2885 2886 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2887 && (rssi > tmp_rss1_thr1)) 2888 { 2889 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2890 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2891 } 2892 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2893 && (rssi > tmp_rss1_thr2)) 2894 { 2895 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2896 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2897 } 2898 } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2899 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2900 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2901 } 2902 } 2903 2904 /* If status is not change, don't do anything */ 2905 if (old_greentx_status == AH9300(ah)->green_tx_status) { 2906 return; 2907 } 2908 2909 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2910 if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2911 && AR_SREV_POSEIDON(ah)) 2912 { 2913 if (ahp->ah_hw_green_tx_enable) { 2914 switch (AH9300(ah)->green_tx_status) { 2915 case HAL_RSSI_TX_POWER_SHORT: 2916 /* 1. TxPower Config */ 2917 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2918 sizeof(target_power_val_t)); 2919 /* 1.1 Store OLPC Delta Calibration Offset*/ 2920 olpc_power_offset = 0; 2921 /* 2. Store OB/DB */ 2922 /* 3. Store TPC settting */ 2923 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2924 SM(14, AR_TPC_CTS) | 2925 SM(14, AR_TPC_CHIRP) | 2926 SM(14, AR_TPC_RPT)); 2927 /* 4. Store BB_powertx_rate9 value */ 2928 temp_powertx_rate9_reg_val = 2929 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2930 break; 2931 case HAL_RSSI_TX_POWER_MIDDLE: 2932 /* 1. TxPower Config */ 2933 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2934 sizeof(target_power_val_t)); 2935 /* 1.1 Store OLPC Delta Calibration Offset*/ 2936 olpc_power_offset = 0; 2937 /* 2. Store OB/DB */ 2938 /* 3. Store TPC settting */ 2939 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2940 SM(18, AR_TPC_CTS) | 2941 SM(18, AR_TPC_CHIRP) | 2942 SM(18, AR_TPC_RPT)); 2943 /* 4. Store BB_powertx_rate9 value */ 2944 temp_powertx_rate9_reg_val = 2945 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2946 break; 2947 case HAL_RSSI_TX_POWER_LONG: 2948 default: 2949 /* 1. TxPower Config */ 2950 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2951 sizeof(target_power_val_t)); 2952 /* 1.1 Store OLPC Delta Calibration Offset*/ 2953 olpc_power_offset = 0; 2954 /* 2. Store OB/DB1/DB2 */ 2955 /* 3. Store TPC settting */ 2956 temp_tcp_reg_val = 2957 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2958 /* 4. Store BB_powertx_rate9 value */ 2959 temp_powertx_rate9_reg_val = 2960 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2961 break; 2962 } 2963 } else { 2964 switch (AH9300(ah)->green_tx_status) { 2965 case HAL_RSSI_TX_POWER_SHORT: 2966 /* 1. TxPower Config */ 2967 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 2968 sizeof(target_power_val_t)); 2969 /* 1.1 Store OLPC Delta Calibration Offset*/ 2970 olpc_power_offset = 2971 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 2972 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2973 /* 2. Store OB/DB */ 2974 temp_obdb_reg_val = 2975 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2976 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2977 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2978 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2979 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2980 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2981 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2982 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2983 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2984 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2985 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2986 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2987 /* 3. Store TPC settting */ 2988 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 2989 SM(6, AR_TPC_CTS) | 2990 SM(6, AR_TPC_CHIRP) | 2991 SM(6, AR_TPC_RPT)); 2992 /* 4. Store BB_powertx_rate9 value */ 2993 temp_powertx_rate9_reg_val = 2994 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 2995 break; 2996 case HAL_RSSI_TX_POWER_MIDDLE: 2997 /* 1. TxPower Config */ 2998 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 2999 sizeof(target_power_val_t)); 3000 /* 1.1 Store OLPC Delta Calibration Offset*/ 3001 olpc_power_offset = 3002 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 3003 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3004 /* 2. Store OB/DB */ 3005 temp_obdb_reg_val = 3006 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3007 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 3008 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 3009 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 3010 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 3011 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 3012 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3013 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 3014 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3015 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 3016 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 3017 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 3018 /* 3. Store TPC settting */ 3019 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 3020 SM(14, AR_TPC_CTS) | 3021 SM(14, AR_TPC_CHIRP) | 3022 SM(14, AR_TPC_RPT)); 3023 /* 4. Store BB_powertx_rate9 value */ 3024 temp_powertx_rate9_reg_val = 3025 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 3026 break; 3027 case HAL_RSSI_TX_POWER_LONG: 3028 default: 3029 /* 1. TxPower Config */ 3030 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 3031 sizeof(target_power_val_t)); 3032 /* 1.1 Store OLPC Delta Calibration Offset*/ 3033 olpc_power_offset = 3034 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 3035 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 3036 /* 2. Store OB/DB1/DB2 */ 3037 temp_obdb_reg_val = 3038 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 3039 /* 3. Store TPC settting */ 3040 temp_tcp_reg_val = 3041 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 3042 /* 4. Store BB_powertx_rate9 value */ 3043 temp_powertx_rate9_reg_val = 3044 AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 3045 break; 3046 } 3047 } 3048 /* 1.1 Do OLPC Delta Calibration Offset */ 3049 tmp_olpc_val = 3050 (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 3051 tmp_olpc_val += olpc_power_offset; 3052 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 3053 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 3054 AR_PHY_TPC_OLPC_GAIN_DELTA); 3055 3056 /* 1.2 TxPower Config */ 3057 ar9300_transmit_power_reg_write(ah, target_power_val_t); 3058 /* 2. Config OB/DB */ 3059 if (!ahp->ah_hw_green_tx_enable) { 3060 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 3061 } 3062 /* 3. config TPC settting */ 3063 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 3064 /* 4. config BB_powertx_rate9 value */ 3065 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 3066 } 3067} 3068 3069#if 0 3070void 3071ar9300_get_vow_stats( 3072 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 3073{ 3074 if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 3075 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 3076 } 3077 if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 3078 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 3079 } 3080 if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 3081 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 3082 } 3083 if (vow_reg_flags & AR_REG_CYCLE_CNT) { 3084 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 3085 } 3086 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 3087 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 3088 } 3089} 3090#endif 3091 3092/* 3093 * ar9300_is_skip_paprd_by_greentx 3094 * 3095 * This function check if we need to skip PAPRD tuning 3096 * when GreenTx in specific state. 3097 */ 3098HAL_BOOL 3099ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 3100{ 3101 if (AR_SREV_POSEIDON(ah) && 3102 ah->ah_config.ath_hal_sta_update_tx_pwr_enable && 3103 ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 3104 (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 3105 { 3106 return AH_TRUE; 3107 } 3108 return AH_FALSE; 3109} 3110 3111void 3112ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 3113{ 3114 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 3115 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 3116 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 3117 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 3118 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 3119 struct ath_hal_9300 *ahp = AH9300(ah); 3120 3121 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3122 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3123 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 3124 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3125 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 3126 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3127 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 3128 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3129 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 3130 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3131 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 3132 } 3133} 3134 3135void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 3136{ 3137 struct ath_hal_9300 *ahp = AH9300(ah); 3138 3139 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3140 if ((value == 0) || (value == 1)) { 3141 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 3142 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3143 } 3144 } 3145} 3146 3147void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3148{ 3149 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3150} 3151 3152int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3153{ 3154 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3155 3156 /* RSSI format is 8.4. Ignore lowest four bits */ 3157 val = val >> 4; 3158 return val; 3159} 3160 3161void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3162 u_int32_t rssi_threshold) 3163{ 3164 struct ath_hal_9300 *ahp = AH9300(ah); 3165 3166 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3167 3168 /* save value for restoring after chip reset */ 3169 ahp->ah_beacon_rssi_threshold = rssi_threshold; 3170} 3171 3172void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3173{ 3174 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3175} 3176 3177void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3178{ 3179 if (on) { 3180 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3181 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3182 } 3183 else { 3184 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3185 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3186 } 3187} 3188/* 3189 * Gets the contents of the specified key cache entry. 3190 */ 3191HAL_BOOL 3192ar9300_print_keycache(struct ath_hal *ah) 3193{ 3194 3195 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3196 u_int32_t key0, key1, key2, key3, key4; 3197 u_int32_t mac_hi, mac_lo; 3198 u_int16_t entry = 0; 3199 u_int32_t valid = 0; 3200 u_int32_t key_type; 3201 3202 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3203 3204 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) { 3205 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3206 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3207 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3208 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3209 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3210 3211 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3212 3213 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3214 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3215 3216 if (mac_hi & AR_KEYTABLE_VALID) { 3217 valid = 1; 3218 } else { 3219 valid = 0; 3220 } 3221 3222 if ((mac_hi != 0) && (mac_lo != 0)) { 3223 mac_hi &= ~0x8000; 3224 mac_hi <<= 1; 3225 mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3226 mac_lo <<= 1; 3227 } 3228 3229 ath_hal_printf(ah, 3230 "%03d " 3231 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3232 " %02d %02d " 3233 "%02x:%02x:%02x:%02x:%02x:%02x \n", 3234 entry, 3235 (key0 << 24) >> 24, (key0 << 16) >> 24, 3236 (key0 << 8) >> 24, key0 >> 24, 3237 (key1 << 24) >> 24, (key1 << 16) >> 24, 3238 //(key1 << 8) >> 24, key1 >> 24, 3239 (key2 << 24) >> 24, (key2 << 16) >> 24, 3240 (key2 << 8) >> 24, key2 >> 24, 3241 (key3 << 24) >> 24, (key3 << 16) >> 24, 3242 //(key3 << 8) >> 24, key3 >> 24, 3243 (key4 << 24) >> 24, (key4 << 16) >> 24, 3244 (key4 << 8) >> 24, key4 >> 24, 3245 valid, key_type, 3246 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3247 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3248 } 3249 3250 return AH_TRUE; 3251} 3252 3253/* enable/disable smart antenna mode */ 3254HAL_BOOL 3255ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3256{ 3257 struct ath_hal_9300 *ahp = AH9300(ah); 3258 3259 if (enable) { 3260 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3261 } else { 3262 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3263 } 3264 3265 /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3266 * and swcom2 with 0 3267 * FIXME Ideally these registers need to be made read from caldata. 3268 * Until the calibration team gets them, keep them along with board 3269 * configuration. 3270 */ 3271 if (enable && AR_SREV_SCORPION(ah) && 3272 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3273 3274 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3275 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3276 } 3277 3278 ahp->ah_smartantenna_enable = enable; 3279 return 1; 3280} 3281 3282#ifdef ATH_TX99_DIAG 3283#ifndef ATH_SUPPORT_HTC 3284void 3285ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3286 u_int32_t txpower) 3287{ 3288#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3289 static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3290 int32_t i; 3291 3292 /* The max power is limited to 63 */ 3293 if (txpower <= AR9300_MAX_RATE_POWER) { 3294 for (i = 0; i < ar9300_rate_size; i++) { 3295 p_pwr_array[i] = txpower; 3296 } 3297 } else { 3298 for (i = 0; i < ar9300_rate_size; i++) { 3299 p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3300 } 3301 } 3302 3303 OS_REG_WRITE(ah, 0xa458, 0); 3304 3305 /* Write the OFDM power per rate set */ 3306 /* 6 (LSB), 9, 12, 18 (MSB) */ 3307 OS_REG_WRITE(ah, 0xa3c0, 3308 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3309 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3310 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3311 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3312 ); 3313 /* 24 (LSB), 36, 48, 54 (MSB) */ 3314 OS_REG_WRITE(ah, 0xa3c4, 3315 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3316 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3317 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3318 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3319 ); 3320 3321 /* Write the CCK power per rate set */ 3322 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3323 OS_REG_WRITE(ah, 0xa3c8, 3324 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3325 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3326 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3327 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3328 ); 3329 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3330 OS_REG_WRITE(ah, 0xa3cc, 3331 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3332 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3333 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3334 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3335 ); 3336 3337 /* Write the HT20 power per rate set */ 3338 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3339 OS_REG_WRITE(ah, 0xa3d0, 3340 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3341 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3342 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3343 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3344 ); 3345 3346 /* 6 (LSB), 7, 12, 13 (MSB) */ 3347 OS_REG_WRITE(ah, 0xa3d4, 3348 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3349 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3350 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3351 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3352 ); 3353 3354 /* 14 (LSB), 15, 20, 21 */ 3355 OS_REG_WRITE(ah, 0xa3e4, 3356 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3357 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3358 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3359 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3360 ); 3361 3362 /* Mixed HT20 and HT40 rates */ 3363 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3364 OS_REG_WRITE(ah, 0xa3e8, 3365 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3366 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3367 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3368 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3369 ); 3370 3371 /* Write the HT40 power per rate set */ 3372 /* correct PAR difference between HT40 and HT20/LEGACY */ 3373 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3374 OS_REG_WRITE(ah, 0xa3d8, 3375 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3376 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3377 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3378 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3379 ); 3380 3381 /* 6 (LSB), 7, 12, 13 (MSB) */ 3382 OS_REG_WRITE(ah, 0xa3dc, 3383 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3384 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3385 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3386 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3387 ); 3388 3389 /* 14 (LSB), 15, 20, 21 */ 3390 OS_REG_WRITE(ah, 0xa3ec, 3391 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3392 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3393 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3394 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3395 ); 3396#undef PWR_MAS 3397} 3398 3399void 3400ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3401{ 3402 if (tx_chainmask == 0x5) { 3403 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3404 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3405 } 3406 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3407 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3408 3409 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3410 if (tx_chainmask == 0x5) { 3411 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3412 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3413 } 3414} 3415 3416void 3417ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3418 int chtype) 3419{ 3420 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3421 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3422 OS_REG_WRITE(ah, 0xa350, 3423 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3424 3425 /* 11G mode */ 3426 if (!chtype) { 3427 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3428 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3429 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3430 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3431 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3432 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3433 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3434 | (0x1 << 26) | (0x7 << 24)) 3435 & ~(0x1 << 22)); 3436 } else { 3437 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3438 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3439 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3440 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3441 | (0x1 << 26) | (0x7 << 24)) 3442 & ~(0x1 << 22)); 3443 } 3444 3445 /* chain zero */ 3446 if ((tx_chain_mask & 0x01) == 0x01) { 3447 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3448 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3449 | (0x1 << 31) | (0x5 << 15) 3450 | (0x3 << 9)) & ~(0x1 << 27) 3451 & ~(0x1 << 12)); 3452 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3453 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3454 | (0x1 << 12) | (0x1 << 10) 3455 | (0x1 << 9) | (0x1 << 8) 3456 | (0x1 << 7)) & ~(0x1 << 11)); 3457 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3458 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3459 | (0x1 << 29) | (0x1 << 25) 3460 | (0x1 << 23) | (0x1 << 19) 3461 | (0x1 << 10) | (0x1 << 9) 3462 | (0x1 << 8) | (0x1 << 3)) 3463 & ~(0x1 << 28)& ~(0x1 << 24) 3464 & ~(0x1 << 22)& ~(0x1 << 7)); 3465 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3466 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3467 | (0x1 << 23))& ~(0x1 << 21)); 3468 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3469 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3470 | (0x1 << 12) | (0x1 << 10) 3471 | (0x1 << 9) | (0x1 << 8) 3472 | (0x1 << 6) | (0x1 << 5) 3473 | (0x1 << 4) | (0x1 << 3) 3474 | (0x1 << 2)); 3475 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3476 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3477 } 3478 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3479 /* chain one */ 3480 if ((tx_chain_mask & 0x02) == 0x02 ) { 3481 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3482 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3483 | (0x1 << 31) | (0x5 << 15) 3484 | (0x3 << 9)) & ~(0x1 << 27) 3485 & ~(0x1 << 12)); 3486 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3487 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3488 | (0x1 << 12) | (0x1 << 10) 3489 | (0x1 << 9) | (0x1 << 8) 3490 | (0x1 << 7)) & ~(0x1 << 11)); 3491 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3492 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3493 | (0x1 << 29) | (0x1 << 25) 3494 | (0x1 << 23) | (0x1 << 19) 3495 | (0x1 << 10) | (0x1 << 9) 3496 | (0x1 << 8) | (0x1 << 3)) 3497 & ~(0x1 << 28)& ~(0x1 << 24) 3498 & ~(0x1 << 22)& ~(0x1 << 7)); 3499 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3500 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3501 | (0x1 << 23))& ~(0x1 << 21)); 3502 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3503 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3504 | (0x1 << 12) | (0x1 << 10) 3505 | (0x1 << 9) | (0x1 << 8) 3506 | (0x1 << 6) | (0x1 << 5) 3507 | (0x1 << 4) | (0x1 << 3) 3508 | (0x1 << 2)); 3509 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3510 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3511 } 3512 } 3513 if (AR_SREV_OSPREY(ah)) { 3514 /* chain two */ 3515 if ((tx_chain_mask & 0x04) == 0x04 ) { 3516 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3517 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3518 | (0x1 << 31) | (0x5 << 15) 3519 | (0x3 << 9)) & ~(0x1 << 27) 3520 & ~(0x1 << 12)); 3521 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3522 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3523 | (0x1 << 12) | (0x1 << 10) 3524 | (0x1 << 9) | (0x1 << 8) 3525 | (0x1 << 7)) & ~(0x1 << 11)); 3526 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3527 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3528 | (0x1 << 29) | (0x1 << 25) 3529 | (0x1 << 23) | (0x1 << 19) 3530 | (0x1 << 10) | (0x1 << 9) 3531 | (0x1 << 8) | (0x1 << 3)) 3532 & ~(0x1 << 28)& ~(0x1 << 24) 3533 & ~(0x1 << 22)& ~(0x1 << 7)); 3534 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3535 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3536 | (0x1 << 23))& ~(0x1 << 21)); 3537 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3538 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3539 | (0x1 << 12) | (0x1 << 10) 3540 | (0x1 << 9) | (0x1 << 8) 3541 | (0x1 << 6) | (0x1 << 5) 3542 | (0x1 << 4) | (0x1 << 3) 3543 | (0x1 << 2)); 3544 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3545 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3546 } 3547 } 3548 3549 OS_REG_WRITE(ah, 0xa28c, 0x11111); 3550 OS_REG_WRITE(ah, 0xa288, 0x111); 3551 } else { 3552 /* chain zero */ 3553 if ((tx_chain_mask & 0x01) == 0x01) { 3554 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3555 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3556 | (0x1 << 31) | (0x1 << 27) 3557 | (0x3 << 23) | (0x1 << 19) 3558 | (0x1 << 15) | (0x3 << 9)) 3559 & ~(0x1 << 12)); 3560 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3561 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3562 | (0x1 << 12) | (0x1 << 10) 3563 | (0x1 << 9) | (0x1 << 8) 3564 | (0x1 << 7) | (0x1 << 3) 3565 | (0x1 << 2) | (0x1 << 1)) 3566 & ~(0x1 << 11)& ~(0x1 << 0)); 3567 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3568 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3569 | (0x1 << 29) | (0x1 << 25) 3570 | (0x1 << 23) | (0x1 << 19) 3571 | (0x1 << 10) | (0x1 << 9) 3572 | (0x1 << 8) | (0x1 << 3)) 3573 & ~(0x1 << 28)& ~(0x1 << 24) 3574 & ~(0x1 << 22)& ~(0x1 << 7)); 3575 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3576 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3577 | (0x1 << 23))& ~(0x1 << 21)); 3578 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3579 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3580 | (0x3 << 3) | (0x3 << 0)); 3581 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3582 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3583 | (0x3 << 29) | (0x3 << 26) 3584 | (0x2 << 23) | (0x2 << 20) 3585 | (0x2 << 17))& ~(0x1 << 14)); 3586 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3587 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3588 | (0x1 << 12) | (0x1 << 10) 3589 | (0x1 << 9) | (0x1 << 8) 3590 | (0x1 << 6) | (0x1 << 5) 3591 | (0x1 << 4) | (0x1 << 3) 3592 | (0x1 << 2)); 3593 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3594 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3595 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3596 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3597 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3598 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3599 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3600 | (0x1 << 26) | (0x7 << 24) 3601 | (0x3 << 22)); 3602 } else { 3603 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3604 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3605 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3606 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3607 | (0x1 << 26) | (0x7 << 24) 3608 | (0x3 << 22)); 3609 } 3610 3611 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3612 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3613 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3614 | (0x1 << 3) | (0x1 << 2) 3615 | (0x1 << 1)) & ~(0x1 << 0)); 3616 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3617 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3618 | (0x1 << 19) | (0x1 << 3)); 3619 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3620 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3621 } 3622 if (AR_SREV_OSPREY(ah)) { 3623 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3624 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3625 | (0x1 << 3) | (0x1 << 2) 3626 | (0x1 << 1)) & ~(0x1 << 0)); 3627 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3628 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3629 | (0x1 << 19) | (0x1 << 3)); 3630 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3631 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3632 } 3633 } 3634 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3635 /* chain one */ 3636 if ((tx_chain_mask & 0x02) == 0x02 ) { 3637 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3638 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3639 | (0x1 << 3) | (0x1 << 2) 3640 | (0x1 << 1)) & ~(0x1 << 0)); 3641 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3642 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3643 | (0x1 << 19) | (0x1 << 3)); 3644 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3645 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3646 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3647 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3648 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3649 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3650 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3651 | (0x1 << 26) | (0x7 << 24) 3652 | (0x3 << 22)); 3653 } else { 3654 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3655 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3656 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3657 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3658 | (0x1 << 26) | (0x7 << 24) 3659 | (0x3 << 22)); 3660 } 3661 3662 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3663 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3664 | (0x1 << 31) | (0x1 << 27) 3665 | (0x3 << 23) | (0x1 << 19) 3666 | (0x1 << 15) | (0x3 << 9)) 3667 & ~(0x1 << 12)); 3668 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3669 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3670 | (0x1 << 12) | (0x1 << 10) 3671 | (0x1 << 9) | (0x1 << 8) 3672 | (0x1 << 7) | (0x1 << 3) 3673 | (0x1 << 2) | (0x1 << 1)) 3674 & ~(0x1 << 11)& ~(0x1 << 0)); 3675 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3676 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3677 | (0x1 << 29) | (0x1 << 25) 3678 | (0x1 << 23) | (0x1 << 19) 3679 | (0x1 << 10) | (0x1 << 9) 3680 | (0x1 << 8) | (0x1 << 3)) 3681 & ~(0x1 << 28)& ~(0x1 << 24) 3682 & ~(0x1 << 22)& ~(0x1 << 7)); 3683 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3684 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3685 | (0x1 << 23))& ~(0x1 << 21)); 3686 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3687 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3688 | (0x3 << 3) | (0x3 << 0)); 3689 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3690 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3691 | (0x3 << 29) | (0x3 << 26) 3692 | (0x2 << 23) | (0x2 << 20) 3693 | (0x2 << 17))& ~(0x1 << 14)); 3694 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3695 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3696 | (0x1 << 12) | (0x1 << 10) 3697 | (0x1 << 9) | (0x1 << 8) 3698 | (0x1 << 6) | (0x1 << 5) 3699 | (0x1 << 4) | (0x1 << 3) 3700 | (0x1 << 2)); 3701 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3702 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3703 3704 if (AR_SREV_OSPREY(ah)) { 3705 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3706 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3707 | (0x1 << 3) | (0x1 << 2) 3708 | (0x1 << 1)) & ~(0x1 << 0)); 3709 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3710 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3711 | (0x1 << 19) | (0x1 << 3)); 3712 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3713 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3714 } 3715 } 3716 } 3717 if (AR_SREV_OSPREY(ah)) { 3718 /* chain two */ 3719 if ((tx_chain_mask & 0x04) == 0x04 ) { 3720 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3721 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3722 | (0x1 << 3) | (0x1 << 2) 3723 | (0x1 << 1)) & ~(0x1 << 0)); 3724 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3725 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3726 | (0x1 << 19) | (0x1 << 3)); 3727 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3728 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3729 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3730 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3731 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3732 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3733 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3734 | (0x1 << 26) | (0x7 << 24) 3735 | (0x3 << 22)); 3736 } else { 3737 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3738 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3739 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3740 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3741 | (0x1 << 26) | (0x7 << 24) 3742 | (0x3 << 22)); 3743 } 3744 3745 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3746 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3747 | (0x1 << 3) | (0x1 << 2) 3748 | (0x1 << 1)) & ~(0x1 << 0)); 3749 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3750 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3751 | (0x1 << 19) | (0x1 << 3)); 3752 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3753 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3754 3755 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3756 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3757 | (0x1 << 31) | (0x1 << 27) 3758 | (0x3 << 23) | (0x1 << 19) 3759 | (0x1 << 15) | (0x3 << 9)) 3760 & ~(0x1 << 12)); 3761 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3762 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3763 | (0x1 << 12) | (0x1 << 10) 3764 | (0x1 << 9) | (0x1 << 8) 3765 | (0x1 << 7) | (0x1 << 3) 3766 | (0x1 << 2) | (0x1 << 1)) 3767 & ~(0x1 << 11)& ~(0x1 << 0)); 3768 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3769 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3770 | (0x1 << 29) | (0x1 << 25) 3771 | (0x1 << 23) | (0x1 << 19) 3772 | (0x1 << 10) | (0x1 << 9) 3773 | (0x1 << 8) | (0x1 << 3)) 3774 & ~(0x1 << 28)& ~(0x1 << 24) 3775 & ~(0x1 << 22)& ~(0x1 << 7)); 3776 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3777 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3778 | (0x1 << 23))& ~(0x1 << 21)); 3779 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3780 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3781 | (0x3 << 3) | (0x3 << 0)); 3782 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3783 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3784 | (0x3 << 29) | (0x3 << 26) 3785 | (0x2 << 23) | (0x2 << 20) 3786 | (0x2 << 17))& ~(0x1 << 14)); 3787 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3788 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3789 | (0x1 << 12) | (0x1 << 10) 3790 | (0x1 << 9) | (0x1 << 8) 3791 | (0x1 << 6) | (0x1 << 5) 3792 | (0x1 << 4) | (0x1 << 3) 3793 | (0x1 << 2)); 3794 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3795 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3796 } 3797 } 3798 3799 OS_REG_WRITE(ah, 0xa28c, 0x22222); 3800 OS_REG_WRITE(ah, 0xa288, 0x222); 3801 } 3802} 3803 3804void 3805ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3806{ 3807 u_int32_t val; 3808 u_int32_t qnum = (u_int32_t)data; 3809 3810 /* Disable AGC to A2 */ 3811 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3812 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3813 3814 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3815 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3816 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3817 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3818 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3819 /* 200 ok for HT20, 400 ok for HT40 */ 3820 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3821 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3822 3823 /* set QCU modes to early termination */ 3824 val = OS_REG_READ(ah, AR_QMISC(qnum)); 3825 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3826} 3827 3828void 3829ar9300_tx99_stop(struct ath_hal *ah) 3830{ 3831 /* this should follow the setting of start */ 3832 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3833 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3834} 3835#endif /* ATH_TX99_DIAG */ 3836#endif /* ATH_SUPPORT_HTC */ 3837 3838HAL_BOOL 3839ar9300Get3StreamSignature(struct ath_hal *ah) 3840{ 3841 return AH_FALSE; 3842} 3843 3844HAL_BOOL 3845ar9300ForceVCS(struct ath_hal *ah) 3846{ 3847 return AH_FALSE; 3848} 3849 3850HAL_BOOL 3851ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3852{ 3853 return AH_FALSE; 3854} 3855 3856HAL_BOOL 3857ar9300_set_ctl_pwr(struct ath_hal *ah, u_int8_t *ctl_array) 3858{ 3859 struct ath_hal_9300 *ahp = AH9300(ah); 3860 ar9300_eeprom_t *p_eep_data = &ahp->ah_eeprom; 3861 u_int8_t *ctl_index; 3862 u_int32_t offset = 0; 3863 3864 if (!ctl_array) 3865 return AH_FALSE; 3866 3867 /* copy 2G ctl freqbin and power data */ 3868 ctl_index = p_eep_data->ctl_index_2g; 3869 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_2G, ctl_array, 3870 OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G + /* ctl_freqbin_2G */ 3871 OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); /* ctl_power_data_2g */ 3872 offset = (OSPREY_NUM_CTLS_2G * OSPREY_NUM_BAND_EDGES_2G) + 3873 ( OSPREY_NUM_CTLS_2G * sizeof(OSP_CAL_CTL_DATA_2G)); 3874 3875 3876 /* copy 2G ctl freqbin and power data */ 3877 ctl_index = p_eep_data->ctl_index_5g; 3878 OS_MEMCPY(ctl_index + OSPREY_NUM_CTLS_5G, ctl_array + offset, 3879 OSPREY_NUM_CTLS_5G * OSPREY_NUM_BAND_EDGES_5G + /* ctl_freqbin_5G */ 3880 OSPREY_NUM_CTLS_5G * sizeof(OSP_CAL_CTL_DATA_5G)); /* ctl_power_data_5g */ 3881 3882 return AH_FALSE; 3883} 3884 3885void 3886ar9300_set_txchainmaskopt(struct ath_hal *ah, u_int8_t mask) 3887{ 3888 struct ath_hal_9300 *ahp = AH9300(ah); 3889 3890 /* optional txchainmask should be subset of primary txchainmask */ 3891 if ((mask & ahp->ah_tx_chainmask) != mask) { 3892 ahp->ah_tx_chainmaskopt = 0; 3893 ath_hal_printf(ah, "Error: ah_tx_chainmask=%d, mask=%d\n", ahp->ah_tx_chainmask, mask); 3894 return; 3895 } 3896 3897 ahp->ah_tx_chainmaskopt = mask; 3898} 3899