ar9300_freebsd_inc.h revision 278741
1#ifndef __AR9300_FREEBSD_INC_H__ 2#define __AR9300_FREEBSD_INC_H__ 3 4/* 5 * Define some configuration entries for the AR9300 HAL, so #if entries 6 * don't have to be removed. 7 */ 8#define ATH_DRIVER_SIM 0 /* SIM */ 9#define ATH_WOW 0 /* Wake on Wireless */ 10#define ATH_SUPPORT_MCI 1 /* MCI btcoex */ 11#define ATH_SUPPORT_AIC 0 /* XXX to do with btcoex? */ 12#define AH_NEED_TX_DATA_SWAP 0 /* TX descriptor swap? */ 13#define AH_NEED_RX_DATA_SWAP 0 /* TX descriptor swap? */ 14#define ATH_SUPPORT_WIRESHARK 0 /* Radiotap HAL code */ 15#define AH_SUPPORT_WRITE_EEPROM 0 /* EEPROM write support */ 16#define ATH_SUPPORT_WAPI 0 /* China WAPI support */ 17#define ATH_ANT_DIV_COMB 1 /* Antenna combining */ 18#define ATH_SUPPORT_RAW_ADC_CAPTURE 0 /* Raw ADC capture support */ 19#define ATH_TRAFFIC_FAST_RECOVER 0 /* XXX not sure yet */ 20#define ATH_SUPPORT_SPECTRAL 0 /* Spectral scan support */ 21#define ATH_BT_COEX 1 /* Enable BT Coex code */ 22#define ATH_PCIE_ERROR_MONITOR 0 /* ??? */ 23#define ATH_SUPPORT_CRDC 0 /* ??? */ 24#define ATH_LOW_POWER_ENABLE 0 /* ??? */ 25#define ATH_SUPPORT_VOW_DCS 0 /* Video over wireless dynamic channel select */ 26#define REMOVE_PKT_LOG 1 27#define ATH_VC_MODE_PROXY_STA 0 /* Azimuth + proxysta? */ 28#define ATH_GEN_RANDOMNESS 0 29#define __PKT_SERIOUS_ERRORS__ 0 30#define HAL_INTR_REFCOUNT_DISABLE 1 /* XXX wha? And atomics in the HAL!? */ 31#define UMAC_SUPPORT_SMARTANTENNA 0 /* sigh.. */ 32#define ATH_SMARTANTENNA_DISABLE_JTAG 0 33#define ATH_SUPPORT_WIRESHARK 0 34#define ATH_SUPPORT_WIFIPOS 0 35#define ATH_SUPPORT_PAPRD 1 36#define ATH_SUPPORT_TxBF 0 37#define AH_PRIVATE_DIAG 1 38#define ATH_SUPPORT_KEYPLUMB_WAR 0 39 40/* XXX need to reverify these; they came in with qcamain */ 41#define ATH_SUPPORT_FAST_CC 0 42#define ATH_SUPPORT_RADIO_RETENTION 0 43#define ATH_SUPPORT_CAL_REUSE 0 44 45#define ATH_WOW_OFFLOAD 0 46 47#define HAL_NO_INTERSPERSED_READS 48 49/* Required or things will probe/attach, but not work right */ 50#define AH_SUPPORT_OSPREY 1 51#define AH_SUPPORT_POSEIDON 1 52#define AH_SUPPORT_AR9300 1 53 54/* These are the embedded boards; we don't currently support these */ 55#ifdef AH_SUPPORT_AR9330 56#define AH_SUPPORT_HORNET 1 57#endif /* AH_SUPPORT_AR9330 */ 58#ifdef AH_SUPPORT_AR9340 59#define AH_SUPPORT_WASP 1 60#endif /* AH_SUPPORT_AR9340 */ 61#ifdef AH_SUPPORT_QCA9550 62#define AH_SUPPORT_SCORPION 1 63#endif /* AH_SUPPORT_QCA9550 */ 64#define FIX_NOISE_FLOOR 1 65 66/* XXX this needs to be removed! No atomics in the HAL! */ 67typedef int os_atomic_t; /* XXX shouldn't do atomics here! */ 68#define OS_ATOMIC_INC(a) (*a)++ 69#define OS_ATOMIC_DEC(a) (*a)-- 70 71/* 72 * HAL definitions which aren't necessarily for public consumption (yet). 73 */ 74 75enum { 76 HAL_TRUE_CHIP = 1, 77 HAL_MAC_TO_MAC_EMU, 78 HAL_MAC_BB_EMU, 79}; 80 81/* HAL_KEY_TYPE */ 82enum { 83 HAL_KEY_PROXY_STA_MASK = 0x10, 84}; 85 86typedef enum { 87 HAL_SMPS_DEFAULT = 0, 88 HAL_SMPS_SW_CTRL_LOW_PWR, /* Software control, low power setting */ 89 HAL_SMPS_SW_CTRL_HIGH_PWR, /* Software control, high power setting */ 90 HAL_SMPS_HW_CTRL /* Hardware Control */ 91} HAL_SMPS_MODE; 92 93/* 94 * Green Tx, Based on different RSSI of Received Beacon thresholds, 95 * using different tx power by modified register tx power related values. 96 * The thresholds are decided by system team. 97 */ 98#define GreenTX_thres1 56 /* in dB */ 99#define GreenTX_thres2 36 /* in dB */ 100 101typedef enum { 102 HAL_RSSI_TX_POWER_NONE = 0, 103 HAL_RSSI_TX_POWER_SHORT = 1, /* short range, reduce OB/DB bias current and disable PAL */ 104 HAL_RSSI_TX_POWER_MIDDLE = 2, /* middle range, reduce OB/DB bias current and PAL is enabled */ 105 HAL_RSSI_TX_POWER_LONG = 3, /* long range, orig. OB/DB bias current and PAL is enabled */ 106} HAL_RSSI_TX_POWER; 107 108struct dfs_pulse { 109 u_int32_t rp_numpulses ; /* Num of pulses in radar burst */ 110 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */ 111 u_int32_t rp_pulsefreq; /* Frequency of pulses in burst */ 112 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */ 113 u_int32_t rp_patterntype; /* fixed or variable pattern type*/ 114 u_int32_t rp_pulsevar; /* Time variation of pulse duration for 115 matched filter (single-sided) in usecs */ 116 u_int32_t rp_threshold; /* Threshold for MF output to indicate 117 radar match */ 118 u_int32_t rp_mindur; /* Min pulse duration to be considered for 119 this pulse type */ 120 u_int32_t rp_maxdur; /* Max pusle duration to be considered for 121 this pulse type */ 122 u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */ 123 u_int32_t rp_meanoffset; /* Offset for timing adjustment */ 124 int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */ 125 /* lower than in non TURBO mode. 126 This will be used to offset that diff.*/ 127 u_int32_t rp_ignore_pri_window; 128 u_int32_t rp_pulseid; /* Unique ID for identifying filter */ 129}; 130 131struct dfs_staggered_pulse { 132 u_int32_t rp_numpulses; /* Num of pulses in radar burst */ 133 u_int32_t rp_pulsedur; /* Duration of each pulse in usecs */ 134 u_int32_t rp_min_pulsefreq; /* Frequency of pulses in burst */ 135 u_int32_t rp_max_pulsefreq; /* Frequency of pulses in burst */ 136 u_int32_t rp_patterntype; /* fixed or variable pattern type*/ 137 u_int32_t rp_pulsevar; /* Time variation of pulse duration for 138 matched filter (single-sided) in usecs */ 139 u_int32_t rp_threshold; /* Thershold for MF output to indicateC 140 radar match */ 141 u_int32_t rp_mindur; /* Min pulse duration to be considered for 142 this pulse type */ 143 u_int32_t rp_maxdur; /* Max pusle duration to be considered for 144 this pulse type */ 145 u_int32_t rp_rssithresh; /* Minimum rssi to be considered a radar pulse */ 146 u_int32_t rp_meanoffset; /* Offset for timing adjustment */ 147 int32_t rp_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */ 148 /* lower than in non TURBO mode. This will be used to offset that diff.*/ 149 u_int32_t rp_pulseid; /* Unique ID for identifying filter */ 150 }; 151 152struct dfs_bin5pulse { 153 u_int32_t b5_threshold; /* Number of bin5 pulses to indicate detection */ 154 u_int32_t b5_mindur; /* Min duration for a bin5 pulse */ 155 u_int32_t b5_maxdur; /* Max duration for a bin5 pulse */ 156 u_int32_t b5_timewindow; /* Window over which to count bin5 pulses */ 157 u_int32_t b5_rssithresh; /* Min rssi to be considered a pulse */ 158 u_int32_t b5_rssimargin; /* rssi threshold margin. In Turbo Mode HW reports rssi 3dB */ 159}; 160 161#if 0 162/* SPECTRAL SCAN defines begin */ 163typedef struct { 164 u_int16_t ss_fft_period; /* Skip interval for FFT reports */ 165 u_int16_t ss_period; /* Spectral scan period */ 166 u_int16_t ss_count; /* # of reports to return from ss_active */ 167 u_int16_t ss_short_report;/* Set to report ony 1 set of FFT results */ 168 u_int8_t radar_bin_thresh_sel; 169 u_int16_t ss_spectral_pri; /* are we doing a noise power cal ? */ 170 int8_t ss_nf_cal[AH_MAX_CHAINS*2]; /* nf calibrated values for ctl+ext from eeprom */ 171 int8_t ss_nf_pwr[AH_MAX_CHAINS*2]; /* nf pwr values for ctl+ext from eeprom */ 172 int32_t ss_nf_temp_data; /* temperature data taken during nf scan */ 173} HAL_SPECTRAL_PARAM; 174#define HAL_SPECTRAL_PARAM_NOVAL 0xFFFF 175#define HAL_SPECTRAL_PARAM_ENABLE 0x8000 /* Enable/Disable if applicable */ 176#endif 177 178/* 179 * Noise power data definitions 180 * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET (e.g. -25 = (-25/4 - 90) = -96.25 dBm) 181 * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm 182 * resolution (2 bits) is 0.25dBm 183 */ 184#define NOISE_PWR_DATA_OFFSET -90 /* dbm - all pwr report data is represented offset by this */ 185#define INT_2_NOISE_PWR_DBM(_p) (((_p) - NOISE_PWR_DATA_OFFSET) << 2) 186#define NOISE_PWR_DBM_2_INT(_p) ((((_p) + 3) >> 2) + NOISE_PWR_DATA_OFFSET) 187#define NOISE_PWR_DBM_2_DEC(_p) (((-(_p)) & 3) * 25) 188#define N2DBM(_x,_y) ((((_x) - NOISE_PWR_DATA_OFFSET) << 2) - (_y)/25) 189/* SPECTRAL SCAN defines end */ 190 191typedef struct halvowstats { 192 u_int32_t tx_frame_count; 193 u_int32_t rx_frame_count; 194 u_int32_t rx_clear_count; 195 u_int32_t cycle_count; 196 u_int32_t ext_cycle_count; 197} HAL_VOWSTATS; 198 199#define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001 200#define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002 201#define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */ 202#define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */ 203#define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010 204#define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020 205 206/* 207 * Weight table configurations. 208 */ 209#define AR9300_BT_WGHT 0xcccc4444 210#define AR9300_STOMP_ALL_WLAN_WGHT0 0xfffffff0 211#define AR9300_STOMP_ALL_WLAN_WGHT1 0xfffffff0 212#define AR9300_STOMP_LOW_WLAN_WGHT0 0x88888880 213#define AR9300_STOMP_LOW_WLAN_WGHT1 0x88888880 214#define AR9300_STOMP_NONE_WLAN_WGHT0 0x00000000 215#define AR9300_STOMP_NONE_WLAN_WGHT1 0x00000000 216#define AR9300_STOMP_ALL_FORCE_WLAN_WGHT0 0xffffffff // Stomp BT even when WLAN is idle 217#define AR9300_STOMP_ALL_FORCE_WLAN_WGHT1 0xffffffff 218#define AR9300_STOMP_LOW_FORCE_WLAN_WGHT0 0x88888888 // Stomp BT even when WLAN is idle 219#define AR9300_STOMP_LOW_FORCE_WLAN_WGHT1 0x88888888 220 221#define JUPITER_STOMP_ALL_WLAN_WGHT0 0x01017d01 222#define JUPITER_STOMP_ALL_WLAN_WGHT1 0x41414101 223#define JUPITER_STOMP_ALL_WLAN_WGHT2 0x41414101 224#define JUPITER_STOMP_ALL_WLAN_WGHT3 0x41414141 225#define JUPITER_STOMP_LOW_WLAN_WGHT0 0x01017d01 226#define JUPITER_STOMP_LOW_WLAN_WGHT1 0x3b3b3b01 227#define JUPITER_STOMP_LOW_WLAN_WGHT2 0x3b3b3b01 228#define JUPITER_STOMP_LOW_WLAN_WGHT3 0x3b3b3b3b 229#define JUPITER_STOMP_LOW_FTP_WLAN_WGHT0 0x01017d01 230#define JUPITER_STOMP_LOW_FTP_WLAN_WGHT1 0x013b0101 231#define JUPITER_STOMP_LOW_FTP_WLAN_WGHT2 0x3b3b0101 232#define JUPITER_STOMP_LOW_FTP_WLAN_WGHT3 0x3b3b013b 233#define JUPITER_STOMP_NONE_WLAN_WGHT0 0x01017d01 234#define JUPITER_STOMP_NONE_WLAN_WGHT1 0x01010101 235#define JUPITER_STOMP_NONE_WLAN_WGHT2 0x01010101 236#define JUPITER_STOMP_NONE_WLAN_WGHT3 0x01010101 237#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0 0x01017d7d 238#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1 0x7d7d7d01 239#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT2 0x7d7d7d7d 240#define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT3 0x7d7d7d7d 241#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT0 0x01013b3b 242#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT1 0x3b3b3b01 243#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT2 0x3b3b3b3b 244#define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT3 0x3b3b3b3b 245 246#define MCI_CONCUR_TX_WLAN_WGHT1_MASK 0xff000000 247#define MCI_CONCUR_TX_WLAN_WGHT1_MASK_S 24 248#define MCI_CONCUR_TX_WLAN_WGHT2_MASK 0x00ff0000 249#define MCI_CONCUR_TX_WLAN_WGHT2_MASK_S 16 250#define MCI_CONCUR_TX_WLAN_WGHT3_MASK 0x000000ff 251#define MCI_CONCUR_TX_WLAN_WGHT3_MASK_S 0 252#define MCI_CONCUR_TX_WLAN_WGHT3_MASK2 0x00ff0000 253#define MCI_CONCUR_TX_WLAN_WGHT3_MASK2_S 16 254 255#define MCI_QUERY_BT_VERSION_VERBOSE 0 256#define MCI_LINKID_INDEX_MGMT_PENDING 1 257 258#define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */ 259 260typedef enum mci_message_header { 261 MCI_LNA_CTRL = 0x10, /* len = 0 */ 262 MCI_CONT_NACK = 0x20, /* len = 0 */ 263 MCI_CONT_INFO = 0x30, /* len = 4 */ 264 MCI_CONT_RST = 0x40, /* len = 0 */ 265 MCI_SCHD_INFO = 0x50, /* len = 16 */ 266 MCI_CPU_INT = 0x60, /* len = 4 */ 267 MCI_SYS_WAKING = 0x70, /* len = 0 */ 268 MCI_GPM = 0x80, /* len = 16 */ 269 MCI_LNA_INFO = 0x90, /* len = 1 */ 270 MCI_LNA_STATE = 0x94, 271 MCI_LNA_TAKE = 0x98, 272 MCI_LNA_TRANS = 0x9c, 273 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */ 274 MCI_REQ_WAKE = 0xc0, /* len = 0 */ 275 MCI_DEBUG_16 = 0xfe, /* len = 2 */ 276 MCI_REMOTE_RESET = 0xff /* len = 16 */ 277} MCI_MESSAGE_HEADER; 278 279/* Default remote BT device MCI COEX version */ 280#define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3 281#define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0 282/* Local WLAN MCI COEX version */ 283#define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3 284#define MCI_GPM_COEX_MINOR_VERSION_WLAN 0 285 286typedef enum mci_gpm_subtype { 287 MCI_GPM_BT_CAL_REQ = 0, 288 MCI_GPM_BT_CAL_GRANT = 1, 289 MCI_GPM_BT_CAL_DONE = 2, 290 MCI_GPM_WLAN_CAL_REQ = 3, 291 MCI_GPM_WLAN_CAL_GRANT = 4, 292 MCI_GPM_WLAN_CAL_DONE = 5, 293 MCI_GPM_COEX_AGENT = 0x0C, 294 MCI_GPM_RSVD_PATTERN = 0xFE, 295 MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE, 296 MCI_GPM_BT_DEBUG = 0xFF 297} MCI_GPM_SUBTYPE_T; 298 299typedef enum mci_gpm_coex_opcode { 300 MCI_GPM_COEX_VERSION_QUERY = 0, 301 MCI_GPM_COEX_VERSION_RESPONSE = 1, 302 MCI_GPM_COEX_STATUS_QUERY = 2, 303 MCI_GPM_COEX_HALT_BT_GPM = 3, 304 MCI_GPM_COEX_WLAN_CHANNELS = 4, 305 MCI_GPM_COEX_BT_PROFILE_INFO = 5, 306 MCI_GPM_COEX_BT_STATUS_UPDATE = 6, 307 MCI_GPM_COEX_BT_UPDATE_FLAGS = 7 308} MCI_GPM_COEX_OPCODE_T; 309 310typedef enum mci_gpm_coex_query_type { 311 /* WLAN information */ 312 MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01, 313 /* BT information */ 314 MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01, 315 MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02, 316 MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04 317} MCI_GPM_COEX_QUERY_TYPE_T; 318 319typedef enum mci_gpm_coex_halt_bt_gpm { 320 MCI_GPM_COEX_BT_GPM_UNHALT = 0, 321 MCI_GPM_COEX_BT_GPM_HALT = 1 322} MCI_GPM_COEX_HALT_BT_GPM_T; 323 324typedef enum mci_gpm_coex_profile_type { 325 MCI_GPM_COEX_PROFILE_UNKNOWN = 0, 326 MCI_GPM_COEX_PROFILE_RFCOMM = 1, 327 MCI_GPM_COEX_PROFILE_A2DP = 2, 328 MCI_GPM_COEX_PROFILE_HID = 3, 329 MCI_GPM_COEX_PROFILE_BNEP = 4, 330 MCI_GPM_COEX_PROFILE_VOICE = 5, 331 MCI_GPM_COEX_PROFILE_MAX 332} MCI_GPM_COEX_PROFILE_TYPE_T; 333 334typedef enum mci_gpm_coex_profile_state { 335 MCI_GPM_COEX_PROFILE_STATE_END = 0, 336 MCI_GPM_COEX_PROFILE_STATE_START = 1 337} MCI_GPM_COEX_PROFILE_STATE_T; 338 339typedef enum mci_gpm_coex_profile_role { 340 MCI_GPM_COEX_PROFILE_SLAVE = 0, 341 MCI_GPM_COEX_PROFILE_MASTER = 1 342} MCI_GPM_COEX_PROFILE_ROLE_T; 343 344typedef enum mci_gpm_coex_bt_status_type { 345 MCI_GPM_COEX_BT_NONLINK_STATUS = 0, 346 MCI_GPM_COEX_BT_LINK_STATUS = 1 347} MCI_GPM_COEX_BT_STATUS_TYPE_T; 348 349typedef enum mci_gpm_coex_bt_status_state { 350 MCI_GPM_COEX_BT_NORMAL_STATUS = 0, 351 MCI_GPM_COEX_BT_CRITICAL_STATUS = 1 352} MCI_GPM_COEX_BT_STATUS_STATE_T; 353 354#define MCI_GPM_INVALID_PROFILE_HANDLE 0xff 355 356typedef enum mci_gpm_coex_bt_updata_flags_op { 357 MCI_GPM_COEX_BT_FLAGS_READ = 0x00, 358 MCI_GPM_COEX_BT_FLAGS_SET = 0x01, 359 MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02 360} MCI_GPM_COEX_BT_FLAGS_OP_T; 361 362/* MCI GPM/Coex opcode/type definitions */ 363enum { 364 MCI_GPM_COEX_W_GPM_PAYLOAD = 1, 365 MCI_GPM_COEX_B_GPM_TYPE = 4, 366 MCI_GPM_COEX_B_GPM_OPCODE = 5, 367 /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */ 368 MCI_GPM_WLAN_CAL_W_SEQUENCE = 2, 369 /* MCI_GPM_COEX_VERSION_QUERY */ 370 /* MCI_GPM_COEX_VERSION_RESPONSE */ 371 MCI_GPM_COEX_B_MAJOR_VERSION = 6, 372 MCI_GPM_COEX_B_MINOR_VERSION = 7, 373 /* MCI_GPM_COEX_STATUS_QUERY */ 374 MCI_GPM_COEX_B_BT_BITMAP = 6, 375 MCI_GPM_COEX_B_WLAN_BITMAP = 7, 376 /* MCI_GPM_COEX_HALT_BT_GPM */ 377 MCI_GPM_COEX_B_HALT_STATE = 6, 378 /* MCI_GPM_COEX_WLAN_CHANNELS */ 379 MCI_GPM_COEX_B_CHANNEL_MAP = 6, 380 /* MCI_GPM_COEX_BT_PROFILE_INFO */ 381 MCI_GPM_COEX_B_PROFILE_TYPE = 6, 382 MCI_GPM_COEX_B_PROFILE_LINKID = 7, 383 MCI_GPM_COEX_B_PROFILE_STATE = 8, 384 MCI_GPM_COEX_B_PROFILE_ROLE = 9, 385 MCI_GPM_COEX_B_PROFILE_RATE = 10, 386 MCI_GPM_COEX_B_PROFILE_VOTYPE = 11, 387 MCI_GPM_COEX_H_PROFILE_T = 12, 388 MCI_GPM_COEX_B_PROFILE_W = 14, 389 MCI_GPM_COEX_B_PROFILE_A = 15, 390 /* MCI_GPM_COEX_BT_STATUS_UPDATE */ 391 MCI_GPM_COEX_B_STATUS_TYPE = 6, 392 MCI_GPM_COEX_B_STATUS_LINKID = 7, 393 MCI_GPM_COEX_B_STATUS_STATE = 8, 394 /* MCI_GPM_COEX_BT_UPDATE_FLAGS */ 395 MCI_GPM_COEX_B_BT_FLAGS_OP = 10, 396 MCI_GPM_COEX_W_BT_FLAGS = 6 397}; 398 399#define MCI_GPM_RECYCLE(_p_gpm) \ 400 { \ 401 *(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \ 402 } 403#define MCI_GPM_TYPE(_p_gpm) \ 404 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff) 405#define MCI_GPM_OPCODE(_p_gpm) \ 406 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff) 407 408#define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \ 409 { \ 410 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \ 411 } 412#define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \ 413 { \ 414 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \ 415 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \ 416 } 417#define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE) 418 419#define MCI_NUM_BT_CHANNELS 79 420 421#define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \ 422 { \ 423 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 424 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 425 (_bt_chan / 8)) |= 1 << (_bt_chan & 7); \ 426 } \ 427 } 428 429#define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \ 430 { \ 431 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \ 432 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \ 433 (_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \ 434 } \ 435 } 436 437#define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001 438#define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002 439#define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004 440#define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008 441#define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010 442#define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020 443#define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080 444#define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100 445#define HAL_MCI_INTERRUPT_RX_MSG 0x00000200 446#define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400 447#define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000 448#define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \ 449 HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \ 450 HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \ 451 HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL ) 452 453#define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001 454#define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002 455#define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004 456#define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008 457#define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010 458#define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020 459#define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040 460#define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100 461#define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200 462#define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400 463#define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800 464#define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000 465#define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \ 466 HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \ 467 HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \ 468 HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \ 469 HAL_MCI_INTERRUPT_RX_MSG_CONT_RST) 470 471typedef enum mci_bt_state { 472 MCI_BT_SLEEP, 473 MCI_BT_AWAKE, 474 MCI_BT_CAL_START, 475 MCI_BT_CAL 476} MCI_BT_STATE_T; 477 478/* Type of state query */ 479typedef enum mci_state_type { 480 HAL_MCI_STATE_ENABLE, 481 HAL_MCI_STATE_INIT_GPM_OFFSET, 482 HAL_MCI_STATE_NEXT_GPM_OFFSET, 483 HAL_MCI_STATE_LAST_GPM_OFFSET, 484 HAL_MCI_STATE_BT, 485 HAL_MCI_STATE_SET_BT_SLEEP, 486 HAL_MCI_STATE_SET_BT_AWAKE, 487 HAL_MCI_STATE_SET_BT_CAL_START, 488 HAL_MCI_STATE_SET_BT_CAL, 489 HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET, 490 HAL_MCI_STATE_REMOTE_SLEEP, 491 HAL_MCI_STATE_CONT_RSSI_POWER, 492 HAL_MCI_STATE_CONT_PRIORITY, 493 HAL_MCI_STATE_CONT_TXRX, 494 HAL_MCI_STATE_RESET_REQ_WAKE, 495 HAL_MCI_STATE_SEND_WLAN_COEX_VERSION, 496 HAL_MCI_STATE_SET_BT_COEX_VERSION, 497 HAL_MCI_STATE_SEND_WLAN_CHANNELS, 498 HAL_MCI_STATE_SEND_VERSION_QUERY, 499 HAL_MCI_STATE_SEND_STATUS_QUERY, 500 HAL_MCI_STATE_NEED_FLUSH_BT_INFO, 501 HAL_MCI_STATE_SET_CONCUR_TX_PRI, 502 HAL_MCI_STATE_RECOVER_RX, 503 HAL_MCI_STATE_NEED_FTP_STOMP, 504 HAL_MCI_STATE_NEED_TUNING, 505 HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX, 506 HAL_MCI_STATE_DEBUG, 507 HAL_MCI_STATE_MAX 508} HAL_MCI_STATE_TYPE; 509 510#define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1 511 512#define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002 513#define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004 514#define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008 515#define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010 516#define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020 517#define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040 518#define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080 519#define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100 520#define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200 521#define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400 522#define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800 523#define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000 524#define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000 525 526#define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde 527/* 528 HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR = 1 529 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR = 1 530 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD = 1 531 HAL_MCI_BT_MCI_FLAGS_LNA_CTRL = 1 532 HAL_MCI_BT_MCI_FLAGS_DEBUG = 0 533 HAL_MCI_BT_MCI_FLAGS_SCHED_MSG = 1 534 HAL_MCI_BT_MCI_FLAGS_CONT_MSG = 1 535 HAL_MCI_BT_MCI_FLAGS_COEX_GPM = 1 536 HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0 537 HAL_MCI_BT_MCI_FLAGS_MCI_MODE = 1 538 HAL_MCI_BT_MCI_FLAGS_EGRET_MODE = 1 539 HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1 540 HAL_MCI_BT_MCI_FLAGS_OTHER = 1 541*/ 542 543#define HAL_MCI_TOGGLE_BT_MCI_FLAGS \ 544 ( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \ 545 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \ 546 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \ 547 HAL_MCI_BT_MCI_FLAGS_MCI_MODE ) 548 549#define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000 550#define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 551#define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS 552 553#define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS 554#define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000 555#define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \ 556 ~HAL_MCI_TOGGLE_BT_MCI_FLAGS) 557 558#define HAL_MCI_GPM_NOMORE 0 559#define HAL_MCI_GPM_MORE 1 560#define HAL_MCI_GPM_INVALID 0xffffffff 561 562#define ATH_AIC_MAX_BT_CHANNEL 79 563 564/* 565 * Default value for Jupiter is 0x00002201 566 * Default value for Aphrodite is 0x00002282 567 */ 568#define ATH_MCI_CONFIG_CONCUR_TX 0x00000003 569#define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004 570#define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008 571#define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010 572#define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020 573#define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040 574#define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080 575#define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700 576#define ATH_MCI_CONFIG_AGGR_THRESH_S 8 577#define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800 578#define ATH_MCI_CONFIG_CLK_DIV 0x00003000 579#define ATH_MCI_CONFIG_CLK_DIV_S 12 580#define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000 581#define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000 582#define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000 583 584#define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \ 585 ATH_MCI_CONFIG_MCI_OBS_TXRX | \ 586 ATH_MCI_CONFIG_MCI_OBS_BT ) 587#define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F 588 589#define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01 590#define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02 591#define ATH_MCI_CONCUR_TX_DEBUG 0x03 592 593/* 594 * The values below come from the system team test result. 595 * For Jupiter, BT tx power level is from 0(-20dBm) to 6(4dBm). 596 * Lowest WLAN tx power would be in bit[23:16] of dword 1. 597 */ 598static const u_int32_t mci_concur_tx_max_pwr[4][8] = 599 { /* No limit */ 600 {0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 601 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f}, 602 /* 11G */ 603 {0x16161616, 0x12121516, 0x12121212, 0x12121212, 604 0x12121212, 0x12121212, 0x12121212, 0x7f121212}, 605 /* HT20 */ 606 {0x15151515, 0x14141515, 0x14141414, 0x14141414, 607 0x14141414, 0x14141414, 0x14141414, 0x7f141414}, 608 /* HT40 */ 609 {0x10101010, 0x10101010, 0x10101010, 0x10101010, 610 0x10101010, 0x10101010, 0x10101010, 0x7f101010}}; 611#define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK 0x00ff0000 612#define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK_S 16 613 614#endif /* __AR9300_FREEBSD_INC_H__ */ 615