ar9300.h revision 250008
1/* 2 * Copyright (c) 2013 Qualcomm Atheros, Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9 * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10 * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11 * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12 * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14 * PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef _ATH_AR9300_H_ 18#define _ATH_AR9300_H_ 19 20#include "ar9300_freebsd_inc.h" 21 22#define AH_BIG_ENDIAN 4321 23#define AH_LITTLE_ENDIAN 1234 24 25#if _BYTE_ORDER == _BIG_ENDIAN 26#define AH_BYTE_ORDER AH_BIG_ENDIAN 27#else 28#define AH_BYTE_ORDER AH_LITTLE_ENDIAN 29#endif 30 31/* XXX doesn't belong here */ 32#define AR_EEPROM_MODAL_SPURS 5 33 34/* 35 * (a) this should be N(a), 36 * (b) FreeBSD does define nitems, 37 * (c) it doesn't have an AH_ prefix, sigh. 38 */ 39#define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0])) 40 41#include "ah_internal.h" 42#include "ah_eeprom.h" 43#include "ah_devid.h" 44#include "ar9300eep.h" /* For Eeprom definitions */ 45 46 47#define AR9300_MAGIC 0x19741014 48 49 50/* MAC register values */ 51 52#define INIT_CONFIG_STATUS 0x00000000 53#define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 54#define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */ 55 56/* 57 * Various fifo fill before Tx start, in 64-byte units 58 * i.e. put the frame in the air while still DMAing 59 */ 60#define MIN_TX_FIFO_THRESHOLD 0x1 61#define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) 62#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 63 64 #define CHANSEL_DIV 15 65 #define FCLK 40 66 67#define COEFF ((FCLK * 5) / 2) 68#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) 69#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) 70#define CHANSEL_5G_DOT5MHZ 2188 71 72/* 73 * Receive Queue Fifo depth. 74 */ 75enum RX_FIFO_DEPTH { 76 HAL_HP_RXFIFO_DEPTH = 16, 77 HAL_LP_RXFIFO_DEPTH = 128, 78}; 79 80/* 81 * Gain support. 82 */ 83#define NUM_CORNER_FIX_BITS_2133 7 84#define CCK_OFDM_GAIN_DELTA 15 85 86enum GAIN_PARAMS { 87 GP_TXCLIP, 88 GP_PD90, 89 GP_PD84, 90 GP_GSEL 91}; 92 93enum GAIN_PARAMS_2133 { 94 GP_MIXGAIN_OVR, 95 GP_PWD_138, 96 GP_PWD_137, 97 GP_PWD_136, 98 GP_PWD_132, 99 GP_PWD_131, 100 GP_PWD_130, 101}; 102 103enum { 104 HAL_RESET_POWER_ON, 105 HAL_RESET_WARM, 106 HAL_RESET_COLD, 107}; 108 109typedef struct _gain_opt_step { 110 int16_t paramVal[NUM_CORNER_FIX_BITS_2133]; 111 int32_t stepGain; 112 int8_t stepName[16]; 113} GAIN_OPTIMIZATION_STEP; 114 115typedef struct { 116 u_int32_t numStepsInLadder; 117 u_int32_t defaultStepNum; 118 GAIN_OPTIMIZATION_STEP optStep[10]; 119} GAIN_OPTIMIZATION_LADDER; 120 121typedef struct { 122 u_int32_t currStepNum; 123 u_int32_t currGain; 124 u_int32_t targetGain; 125 u_int32_t loTrig; 126 u_int32_t hiTrig; 127 u_int32_t gainFCorrection; 128 u_int32_t active; 129 GAIN_OPTIMIZATION_STEP *curr_step; 130} GAIN_VALUES; 131 132typedef struct { 133 u_int16_t synth_center; 134 u_int16_t ctl_center; 135 u_int16_t ext_center; 136} CHAN_CENTERS; 137 138/* RF HAL structures */ 139typedef struct rf_hal_funcs { 140 HAL_BOOL (*set_channel)(struct ath_hal *, struct ieee80211_channel *); 141 HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, 142 struct ieee80211_channel *chan); 143} RF_HAL_FUNCS; 144 145struct ar9300_ani_default { 146 u_int16_t m1_thresh_low; 147 u_int16_t m2_thresh_low; 148 u_int16_t m1_thresh; 149 u_int16_t m2_thresh; 150 u_int16_t m2_count_thr; 151 u_int16_t m2_count_thr_low; 152 u_int16_t m1_thresh_low_ext; 153 u_int16_t m2_thresh_low_ext; 154 u_int16_t m1_thresh_ext; 155 u_int16_t m2_thresh_ext; 156 u_int16_t firstep; 157 u_int16_t firstep_low; 158 u_int16_t cycpwr_thr1; 159 u_int16_t cycpwr_thr1_ext; 160}; 161 162/* 163 * Per-channel ANI state private to the driver. 164 */ 165struct ar9300_ani_state { 166 struct ieee80211_channel c; /* XXX ew? */ 167 HAL_BOOL must_restore; 168 HAL_BOOL ofdms_turn; 169 u_int8_t ofdm_noise_immunity_level; 170 u_int8_t cck_noise_immunity_level; 171 u_int8_t spur_immunity_level; 172 u_int8_t firstep_level; 173 u_int8_t ofdm_weak_sig_detect_off; 174 u_int8_t mrc_cck_off; 175 176 /* Thresholds */ 177 u_int32_t listen_time; 178 u_int32_t ofdm_trig_high; 179 u_int32_t ofdm_trig_low; 180 int32_t cck_trig_high; 181 int32_t cck_trig_low; 182 int32_t rssi_thr_low; 183 int32_t rssi_thr_high; 184 185 int32_t rssi; /* The current RSSI */ 186 u_int32_t tx_frame_count; /* Last tx_frame_count */ 187 u_int32_t rx_frame_count; /* Last rx Frame count */ 188 u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */ 189 u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */ 190 u_int32_t cck_phy_err_count; /* CCK err count since last reset */ 191 192 struct ar9300_ani_default ini_def; /* INI default values for ANI registers */ 193 HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */ 194}; 195 196#define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */ 197 198#define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */ 199 200#define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ 201#define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */ 202#define HAL_AR_EN 0x40000000 /* AR detect is capable */ 203 204#define DO_ANI(ah) \ 205 ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI)) 206 207struct ar9300_stats { 208 u_int32_t ast_ani_niup; /* ANI increased noise immunity */ 209 u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */ 210 u_int32_t ast_ani_spurup; /* ANI increased spur immunity */ 211 u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 212 u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 213 u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 214 u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 215 u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 216 u_int32_t ast_ani_stepup; /* ANI increased first step level */ 217 u_int32_t ast_ani_stepdown;/* ANI decreased first step level */ 218 u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 219 u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 220 u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 221 u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */ 222 u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 223 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 224 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 225}; 226 227struct ar9300_rad_reader { 228 u_int16_t rd_index; 229 u_int16_t rd_expSeq; 230 u_int32_t rd_resetVal; 231 u_int8_t rd_start; 232}; 233 234struct ar9300_rad_writer { 235 u_int16_t wr_index; 236 u_int16_t wr_seq; 237}; 238 239struct ar9300_radar_event { 240 u_int32_t re_ts; /* 32 bit time stamp */ 241 u_int8_t re_rssi; /* rssi of radar event */ 242 u_int8_t re_dur; /* duration of radar pulse */ 243 u_int8_t re_chanIndex; /* Channel of event */ 244}; 245 246struct ar9300_radar_q_elem { 247 u_int32_t rq_seqNum; 248 u_int32_t rq_busy; /* 32 bit to insure atomic read/write */ 249 struct ar9300_radar_event rq_event; /* Radar event */ 250}; 251 252struct ar9300_radar_q_info { 253 u_int16_t ri_qsize; /* q size */ 254 u_int16_t ri_seqSize; /* Size of sequence ring */ 255 struct ar9300_rad_reader ri_reader; /* State for the q reader */ 256 struct ar9300_rad_writer ri_writer; /* state for the q writer */ 257}; 258 259#define HAL_MAX_ACK_RADAR_DUR 511 260#define HAL_MAX_NUM_PEAKS 3 261#define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */ 262#define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */ 263#define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */ 264#define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */ 265#define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */ 266 267struct ar9300_ar_state { 268 u_int16_t ar_prev_time_stamp; 269 u_int32_t ar_prev_width; 270 u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR]; 271 u_int32_t ar_ack_sum; 272 u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS]; 273 u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */ 274 u_int32_t ar_par_threshold; /* Thresh to determine peak */ 275 u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */ 276}; 277 278struct ar9300_radar_state { 279 struct ieee80211_channel *rs_chan; /* Channel info */ 280 u_int8_t rs_chan_index; /* Channel index in radar structure */ 281 u_int32_t rs_num_radar_events; /* Number of radar events */ 282 int32_t rs_firpwr; /* Thresh to check radar sig is gone */ 283 u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */ 284 u_int32_t rs_height; /* Thresh for pulse height (dB)*/ 285 u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */ 286 u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */ 287}; 288typedef struct { 289 u_int8_t uc_receiver_errors; 290 u_int8_t uc_bad_tlp_errors; 291 u_int8_t uc_bad_dllp_errors; 292 u_int8_t uc_replay_timeout_errors; 293 u_int8_t uc_replay_number_rollover_errors; 294} ar_pcie_error_moniter_counters; 295 296#define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */ 297#define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */ 298#define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */ 299#define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */ 300#define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */ 301#define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */ 302 303/* 304 * For Kite and later chipsets, the following bits are not being programmed in EEPROM 305 * and so need to be enabled always. 306 * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40 307 * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40 308 */ 309#define AR9300_RDEXT_DEFAULT 0x1F 310 311#define AR9300_MAX_CHAINS 3 312#define AR9300_NUM_CHAINS(chainmask) \ 313 (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1)) 314#define AR9300_CHAIN0_MASK 0x1 315#define AR9300_CHAIN1_MASK 0x2 316#define AR9300_CHAIN2_MASK 0x4 317 318/* Support for multiple INIs */ 319struct ar9300_ini_array { 320 u_int32_t *ia_array; 321 u_int32_t ia_rows; 322 u_int32_t ia_columns; 323}; 324#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 325 (iniarray)->ia_array = (u_int32_t *)(array); \ 326 (iniarray)->ia_rows = (rows); \ 327 (iniarray)->ia_columns = (columns); \ 328} while (0) 329#define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) 330 331#define INIT_CAL(_perCal) \ 332 (_perCal)->cal_state = CAL_WAITING; \ 333 (_perCal)->cal_next = AH_NULL; 334 335#define INSERT_CAL(_ahp, _perCal) \ 336do { \ 337 if ((_ahp)->ah_cal_list_last == AH_NULL) { \ 338 (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \ 339 ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 340 } else { \ 341 ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 342 (_ahp)->ah_cal_list_last = (_perCal); \ 343 (_perCal)->cal_next = (_ahp)->ah_cal_list; \ 344 } \ 345} while (0) 346 347typedef enum cal_types { 348 IQ_MISMATCH_CAL = 0x1, 349 TEMP_COMP_CAL = 0x2, 350} HAL_CAL_TYPES; 351 352typedef enum cal_state { 353 CAL_INACTIVE, 354 CAL_WAITING, 355 CAL_RUNNING, 356 CAL_DONE 357} HAL_CAL_STATE; /* Calibrate state */ 358 359#define MIN_CAL_SAMPLES 1 360#define MAX_CAL_SAMPLES 64 361#define INIT_LOG_COUNT 5 362#define PER_MIN_LOG_COUNT 2 363#define PER_MAX_LOG_COUNT 10 364 365#define AR9300_NUM_BT_WEIGHTS 4 366#define AR9300_NUM_WLAN_WEIGHTS 4 367 368/* Per Calibration data structure */ 369typedef struct per_cal_data { 370 HAL_CAL_TYPES cal_type; // Type of calibration 371 u_int32_t cal_num_samples; // Number of SW samples to collect 372 u_int32_t cal_count_max; // Number of HW samples to collect 373 void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func 374 void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func 375} HAL_PERCAL_DATA; 376 377/* List structure for calibration data */ 378typedef struct cal_list { 379 const HAL_PERCAL_DATA *cal_data; 380 HAL_CAL_STATE cal_state; 381 struct cal_list *cal_next; 382} HAL_CAL_LIST; 383 384#define AR9300_NUM_CAL_TYPES 2 385#define AR9300_PAPRD_TABLE_SZ 24 386#define AR9300_PAPRD_GAIN_TABLE_SZ 32 387#define AR9382_MAX_GPIO_PIN_NUM (16) 388#define AR9382_GPIO_PIN_8_RESERVED (8) 389#define AR9382_GPIO_9_INPUT_ONLY (9) 390#define AR9382_MAX_GPIO_INPUT_PIN_NUM (13) 391#define AR9382_GPIO_PIN_11_RESERVED (11) 392#define AR9382_MAX_JTAG_GPIO_PIN_NUM (3) 393 394/* Paprd tx power adjust data structure */ 395struct ar9300_paprd_pwr_adjust { 396 u_int32_t target_rate; // rate index 397 u_int32_t reg_addr; // register offset 398 u_int32_t reg_mask; // mask of register 399 u_int32_t reg_mask_offset; // mask offset of register 400 u_int32_t sub_db; // offset value unit of dB 401}; 402 403struct ar9300NfLimits { 404 int16_t max; 405 int16_t min; 406 int16_t nominal; 407}; 408 409#define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ 410struct ath_hal_9300 { 411 struct ath_hal_private ah_priv; /* base class */ 412 413 /* 414 * Information retrieved from EEPROM. 415 */ 416 ar9300_eeprom_t ah_eeprom; 417 418 GAIN_VALUES ah_gain_values; 419 420 u_int8_t ah_macaddr[IEEE80211_ADDR_LEN]; 421 u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; 422 u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN]; 423 u_int16_t ah_assoc_id; 424 425 /* 426 * Runtime state. 427 */ 428 u_int32_t ah_mask_reg; /* copy of AR_IMR */ 429 u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */ 430 u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */ 431 os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */ 432 struct ar9300_stats ah_stats; /* various statistics */ 433 RF_HAL_FUNCS ah_rf_hal; 434 u_int32_t ah_tx_desc_mask; /* mask for TXDESC */ 435 u_int32_t ah_tx_ok_interrupt_mask; 436 u_int32_t ah_tx_err_interrupt_mask; 437 u_int32_t ah_tx_desc_interrupt_mask; 438 u_int32_t ah_tx_eol_interrupt_mask; 439 u_int32_t ah_tx_urn_interrupt_mask; 440 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 441 HAL_SMPS_MODE ah_sm_power_mode; 442 HAL_BOOL ah_chip_full_sleep; 443 u_int32_t ah_atim_window; 444 HAL_ANT_SETTING ah_diversity_control; /* antenna setting */ 445 u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */ 446 u_int8_t ah_tx_chainmask_cfg; /* chain mask config */ 447 u_int8_t ah_rx_chainmask_cfg; 448 u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */ 449 /* Calibration related fields */ 450 HAL_CAL_TYPES ah_supp_cals; 451 HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */ 452 HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */ 453 HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */ 454 HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */ 455 HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */ 456// IQ Cal aliases 457#define ah_total_power_meas_i ah_meas0.unsign 458#define ah_total_power_meas_q ah_meas1.unsign 459#define ah_total_iq_corr_meas ah_meas2.sign 460 union { 461 u_int32_t unsign[AR9300_MAX_CHAINS]; 462 int32_t sign[AR9300_MAX_CHAINS]; 463 } ah_meas0; 464 union { 465 u_int32_t unsign[AR9300_MAX_CHAINS]; 466 int32_t sign[AR9300_MAX_CHAINS]; 467 } ah_meas1; 468 union { 469 u_int32_t unsign[AR9300_MAX_CHAINS]; 470 int32_t sign[AR9300_MAX_CHAINS]; 471 } ah_meas2; 472 union { 473 u_int32_t unsign[AR9300_MAX_CHAINS]; 474 int32_t sign[AR9300_MAX_CHAINS]; 475 } ah_meas3; 476 u_int16_t ah_cal_samples; 477 /* end - Calibration related fields */ 478 u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */ 479 u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */ 480 u_int32_t ah_misc_mode; /* MISC_MODE settings */ 481 HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */ 482 enum { 483 AUTO_32KHZ, /* use it if 32kHz crystal present */ 484 USE_32KHZ, /* do it regardless */ 485 DONT_USE_32KHZ, /* don't use it regardless */ 486 } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */ 487 488 u_int32_t ah_ofdm_tx_power; 489 int16_t ah_tx_power_index_offset; 490 491 u_int ah_slot_time; /* user-specified slot time */ 492 u_int ah_ack_timeout; /* user-specified ack timeout */ 493 /* 494 * XXX 495 * 11g-specific stuff; belongs in the driver. 496 */ 497 u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */ 498 u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */ 499 u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */ 500 /* 501 * RF Silent handling; setup according to the EEPROM. 502 */ 503 u_int32_t ah_gpio_select; /* GPIO pin to use */ 504 u_int32_t ah_polarity; /* polarity to disable RF */ 505 u_int32_t ah_gpio_bit; /* after init, prev value */ 506 HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */ 507 508#ifdef ATH_BT_COEX 509 /* 510 * Bluetooth coexistence static setup according to the registry 511 */ 512 HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */ 513 u_int8_t ah_bt_coex_config_type; /* BT coex configuration */ 514 u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */ 515 u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */ 516 u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */ 517 u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */ 518 HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */ 519 u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */ 520 /* 521 * Bluetooth coexistence runtime settings 522 */ 523 HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */ 524 u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ 525 u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 526 u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 527 u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ 528 u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */ 529#endif 530 531 /* 532 * Generic timer support 533 */ 534 u_int32_t ah_avail_gen_timers; /* mask of available timers */ 535 u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */ 536 u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */ 537 HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */ 538 539 /* 540 * ANI & Radar support. 541 */ 542 u_int32_t ah_proc_phy_err; /* Process Phy errs */ 543 u_int32_t ah_ani_period; /* ani update list period */ 544 struct ar9300_ani_state *ah_curani; /* cached last reference */ 545 struct ar9300_ani_state ah_ani[255]; /* per-channel state */ 546 struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */ 547 struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */ 548 struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */ 549 struct ar9300_ar_state ah_ar; /* AR detector state */ 550 struct ar9300_radar_q_elem *ah_arq; /* AR event queue */ 551 struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */ 552 553 /* 554 * Transmit power state. Note these are maintained 555 * here so they can be retrieved by diagnostic tools. 556 */ 557 u_int16_t ah_rates_array[16]; 558 559 /* 560 * Tx queue interrupt state. 561 */ 562 u_int32_t ah_intr_txqs; 563 564 HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */ 565 HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */ 566 567 /* 568 * Extension Channel Rx Clear State 569 */ 570 u_int32_t ah_cycle_count; 571 u_int32_t ah_ctl_busy; 572 u_int32_t ah_ext_busy; 573 574 /* HT CWM state */ 575 HAL_HT_EXTPROTSPACING ah_ext_prot_spacing; 576 u_int8_t ah_tx_chainmask; /* tx chain mask */ 577 u_int8_t ah_rx_chainmask; /* rx chain mask */ 578 579 u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */ 580 u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */ 581 582 int ah_hwp; 583 void *ah_cal_mem; 584 HAL_BOOL ah_emu_eeprom; 585 586 HAL_ANI_CMD ah_ani_function; 587 HAL_BOOL ah_rifs_enabled; 588 u_int32_t ah_rifs_reg[11]; 589 u_int32_t ah_rifs_sec_cnt; 590 591 /* open-loop power control */ 592 u_int32_t original_gain[22]; 593 int32_t init_pdadc; 594 int32_t pdadc_delta; 595 596 /* cycle counts for beacon stuck diagnostics */ 597 u_int32_t ah_cycles; 598 u_int32_t ah_rx_clear; 599 u_int32_t ah_rx_frame; 600 u_int32_t ah_tx_frame; 601 602#define BB_HANG_SIG1 0 603#define BB_HANG_SIG2 1 604#define BB_HANG_SIG3 2 605#define BB_HANG_SIG4 3 606#define MAC_HANG_SIG1 4 607#define MAC_HANG_SIG2 5 608 /* bb hang detection */ 609 int ah_hang[6]; 610 hal_hw_hangs_t ah_hang_wars; 611 612 /* 613 * Keytable type table 614 */ 615#define AR_KEYTABLE_SIZE 128 /* XXX! */ 616 uint8_t ah_keytype[AR_KEYTABLE_SIZE]; 617#undef AR_KEYTABLE_SIZE 618 /* 619 * Support for ar9300 multiple INIs 620 */ 621 struct ar9300_ini_array ah_ini_pcie_serdes; 622 struct ar9300_ini_array ah_ini_pcie_serdes_low_power; 623 struct ar9300_ini_array ah_ini_modes_additional; 624 struct ar9300_ini_array ah_ini_modes_additional_40mhz; 625 struct ar9300_ini_array ah_ini_modes_rxgain; 626 struct ar9300_ini_array ah_ini_modes_rxgain_bounds; 627 struct ar9300_ini_array ah_ini_modes_txgain; 628 struct ar9300_ini_array ah_ini_japan2484; 629 struct ar9300_ini_array ah_ini_radio_post_sys2ant; 630 struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR; 631 /* 632 * New INI format starting with Osprey 2.0 INI. 633 * Pre, core, post arrays for each sub-system (mac, bb, radio, soc) 634 */ 635 #define ATH_INI_PRE 0 636 #define ATH_INI_CORE 1 637 #define ATH_INI_POST 2 638 #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1) 639 struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */ 640 struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */ 641 struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */ 642 struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */ 643 644 /* 645 * Added to support DFS postamble array in INI that we need to apply 646 * in DFS channels 647 */ 648 649 struct ar9300_ini_array ah_ini_dfs; 650 651#if ATH_WOW 652 struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */ 653#endif 654 655 /* To indicate EEPROM mapping used */ 656 u_int32_t ah_immunity_vals[6]; 657 HAL_BOOL ah_immunity_on; 658 /* 659 * snap shot of counter register for debug purposes 660 */ 661#ifdef AH_DEBUG 662 u_int32_t last_tf; 663 u_int32_t last_rf; 664 u_int32_t last_rc; 665 u_int32_t last_cc; 666#endif 667 HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */ 668 u_int32_t nf_tsf32; /* timestamp for NF calibration duration */ 669 670 u_int32_t reg_dmn; /* Regulatory Domain */ 671 int16_t twice_antenna_gain; /* Antenna Gain */ 672 u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */ 673 674 /* 675 * Upper limit after factoring in the regulatory max, antenna gain and 676 * multichain factor. No TxBF, CDD or STBC gain factored 677 */ 678 int16_t upper_limit[AR9300_MAX_CHAINS]; 679 680 /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ 681 int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 682 683 /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ 684 int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 685 686 /* Transmit Status ring support */ 687 struct ar9300_txs *ts_ring; 688 u_int16_t ts_tail; 689 u_int16_t ts_size; 690 u_int32_t ts_paddr_start; 691 u_int32_t ts_paddr_end; 692 693 /* Receive Buffer size */ 694#define HAL_RXBUFSIZE_DEFAULT 0xfff 695 u_int16_t rx_buf_size; 696 697 u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states). 698 699 /* Indicate the PLL source clock rate is 25Mhz or not. 700 * clk_25mhz = 0 by default. 701 */ 702 u_int8_t clk_25mhz; 703 /* For PAPRD uses */ 704 u_int16_t small_signal_gain[AH_MAX_CHAINS]; 705 u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ]; 706 u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ]; 707 u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ]; 708 u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */ 709 u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */ 710 u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */ 711 u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */ 712 u_int32_t paprd_training_power; 713 /* For GreenTx use to store the default tx power */ 714 u_int8_t ah_default_tx_power[ar9300_rate_size]; 715 HAL_BOOL ah_paprd_broken; 716 717 /* To store offsets of host interface registers */ 718 struct { 719 u_int32_t AR_RC; 720 u_int32_t AR_WA; 721 u_int32_t AR_PM_STATE; 722 u_int32_t AR_H_INFOL; 723 u_int32_t AR_H_INFOH; 724 u_int32_t AR_PCIE_PM_CTRL; 725 u_int32_t AR_HOST_TIMEOUT; 726 u_int32_t AR_EEPROM; 727 u_int32_t AR_SREV; 728 u_int32_t AR_INTR_SYNC_CAUSE; 729 u_int32_t AR_INTR_SYNC_CAUSE_CLR; 730 u_int32_t AR_INTR_SYNC_ENABLE; 731 u_int32_t AR_INTR_ASYNC_MASK; 732 u_int32_t AR_INTR_SYNC_MASK; 733 u_int32_t AR_INTR_ASYNC_CAUSE_CLR; 734 u_int32_t AR_INTR_ASYNC_CAUSE; 735 u_int32_t AR_INTR_ASYNC_ENABLE; 736 u_int32_t AR_PCIE_SERDES; 737 u_int32_t AR_PCIE_SERDES2; 738 u_int32_t AR_GPIO_OUT; 739 u_int32_t AR_GPIO_IN; 740 u_int32_t AR_GPIO_OE_OUT; 741 u_int32_t AR_GPIO_OE1_OUT; 742 u_int32_t AR_GPIO_INTR_POL; 743 u_int32_t AR_GPIO_INPUT_EN_VAL; 744 u_int32_t AR_GPIO_INPUT_MUX1; 745 u_int32_t AR_GPIO_INPUT_MUX2; 746 u_int32_t AR_GPIO_OUTPUT_MUX1; 747 u_int32_t AR_GPIO_OUTPUT_MUX2; 748 u_int32_t AR_GPIO_OUTPUT_MUX3; 749 u_int32_t AR_INPUT_STATE; 750 u_int32_t AR_SPARE; 751 u_int32_t AR_PCIE_CORE_RESET_EN; 752 u_int32_t AR_CLKRUN; 753 u_int32_t AR_EEPROM_STATUS_DATA; 754 u_int32_t AR_OBS; 755 u_int32_t AR_RFSILENT; 756 u_int32_t AR_GPIO_PDPU; 757 u_int32_t AR_GPIO_DS; 758 u_int32_t AR_MISC; 759 u_int32_t AR_PCIE_MSI; 760 u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE; 761 u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY; 762 u_int32_t AR_TSF_SNAPSHOT_BT_CNTL; 763 u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ; 764 u_int32_t AR_TDMA_CCA_CNTL; 765 u_int32_t AR_TXAPSYNC; 766 u_int32_t AR_TXSYNC_INIT_SYNC_TMR; 767 u_int32_t AR_INTR_PRIO_SYNC_CAUSE; 768 u_int32_t AR_INTR_PRIO_SYNC_ENABLE; 769 u_int32_t AR_INTR_PRIO_ASYNC_MASK; 770 u_int32_t AR_INTR_PRIO_SYNC_MASK; 771 u_int32_t AR_INTR_PRIO_ASYNC_CAUSE; 772 u_int32_t AR_INTR_PRIO_ASYNC_ENABLE; 773 } ah_hostifregs; 774 775 u_int32_t ah_enterprise_mode; 776 u_int32_t ah_radar1; 777 u_int32_t ah_dc_offset; 778 HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */ 779 HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */ 780 u_int32_t ah_disable_cck; 781 HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */ 782 783 784 /* 785 * Different types of memory where the calibration data might be stored. 786 * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp. 787 * To disable searching a type, set its parameter to 0. 788 */ 789 int try_dram; 790 int try_flash; 791 int try_eeprom; 792 int try_otp; 793#ifdef ATH_CAL_NAND_FLASH 794 int try_nand; 795#endif 796 /* 797 * This is where we found the calibration data. 798 */ 799 int calibration_data_source; 800 int calibration_data_source_address; 801 /* 802 * This is where we look for the calibration data. must be set before ath_attach() is called 803 */ 804 int calibration_data_try; 805 int calibration_data_try_address; 806 u_int8_t 807 tx_iq_cal_enable : 1, 808 tx_iq_cal_during_agc_cal : 1, 809 tx_cl_cal_enable : 1; 810 811#if ATH_SUPPORT_MCI 812 /* For MCI */ 813 HAL_BOOL ah_mci_ready; 814 u_int32_t ah_mci_int_raw; 815 u_int32_t ah_mci_int_rx_msg; 816 u_int32_t ah_mci_rx_status; 817 u_int32_t ah_mci_cont_status; 818 u_int8_t ah_mci_bt_state; 819 u_int32_t ah_mci_gpm_addr; 820 u_int8_t *ah_mci_gpm_buf; 821 u_int32_t ah_mci_gpm_len; 822 u_int32_t ah_mci_gpm_idx; 823 u_int32_t ah_mci_sched_addr; 824 u_int8_t *ah_mci_sched_buf; 825 u_int8_t ah_mci_coex_major_version_wlan; 826 u_int8_t ah_mci_coex_minor_version_wlan; 827 u_int8_t ah_mci_coex_major_version_bt; 828 u_int8_t ah_mci_coex_minor_version_bt; 829 HAL_BOOL ah_mci_coex_bt_version_known; 830 HAL_BOOL ah_mci_coex_wlan_channels_update; 831 u_int32_t ah_mci_coex_wlan_channels[4]; 832 HAL_BOOL ah_mci_coex_2g5g_update; 833 HAL_BOOL ah_mci_coex_is_2g; 834 HAL_BOOL ah_mci_query_bt; 835 HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */ 836 HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */ 837 HAL_BOOL ah_mci_need_flush_btinfo; 838 HAL_BOOL ah_mci_concur_tx_en; 839 u_int8_t ah_mci_stomp_low_tx_pri; 840 u_int8_t ah_mci_stomp_all_tx_pri; 841 u_int8_t ah_mci_stomp_none_tx_pri; 842 u_int32_t ah_mci_wlan_cal_seq; 843 u_int32_t ah_mci_wlan_cal_done; 844#if ATH_SUPPORT_AIC 845 HAL_BOOL ah_aic_enabled; 846 u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL]; 847#endif 848#endif /* ATH_SUPPORT_MCI */ 849 u_int8_t ah_cac_quiet_enabled; 850#if ATH_WOW_OFFLOAD 851 u_int32_t ah_mcast_filter_l32_set; 852 u_int32_t ah_mcast_filter_u32_set; 853#endif 854 HAL_BOOL ah_reduced_self_gen_mask; 855 856 /* Local additions for FreeBSD */ 857 /* 858 * These fields are in the top level HAL in the atheros 859 * codebase; here we place them in the AR9300 HAL and 860 * access them via accessor methods if the driver requires them. 861 */ 862 u_int32_t ah_ob_db1[3]; 863 u_int32_t ah_db2[3]; 864 u_int32_t ah_bb_panic_timeout_ms; 865 u_int32_t ah_bb_panic_last_status; 866 u_int32_t ah_tx_trig_level; 867 u_int16_t ath_hal_spur_chans[AR_EEPROM_MODAL_SPURS][2]; 868 int16_t nf_cw_int_delta; /* diff btwn nominal NF and CW interf threshold */ 869 int ah_phyrestart_disabled; 870 HAL_RSSI_TX_POWER green_tx_status; 871 int green_ap_ps_on; 872 int ah_enable_keysearch_always; 873 int ah_fccaifs; 874 int ah_reset_reason; 875 int ah_dcs_enable; 876 877 struct ar9300NfLimits nf_2GHz; 878 struct ar9300NfLimits nf_5GHz; 879 struct ar9300NfLimits *nfp; 880 881}; 882 883#define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) 884 885#define IS_9300_EMU(ah) \ 886 (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE) 887 888#define ar9300_eep_data_in_flash(_ah) \ 889 (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) 890 891#ifdef notyet 892// Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. 893&& \ 894 ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ 895 (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G)))) 896#endif 897 898/* 899 * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows 900 * other cards' DMA reads to complete in the middle of our reset. 901 */ 902#define WAR_6773(x) do { \ 903 if ((++(x) % 64) == 0) \ 904 OS_DELAY(1); \ 905} while (0) 906 907#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 908 int r; \ 909 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 910 OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\ 911 WAR_6773(regWr); \ 912 } \ 913} while (0) 914 915#define UPPER_5G_SUB_BANDSTART 5700 916#define MID_5G_SUB_BANDSTART 5400 917#define TRAINPOWER_DB_OFFSET 6 918 919#define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \ 920 } else { \ 921 if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \ 922 else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \ 923 { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \ 924 else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0) 925 926#ifdef AH_ASSERT 927 #define ar9300FeatureNotSupported(feature, ah, func) \ 928 ath_hal_printf(ah, # feature \ 929 " not supported but called from %s\n", (func)), \ 930 hal_assert(0) 931#else 932 #define ar9300FeatureNotSupported(feature, ah, func) \ 933 ath_hal_printf(ah, # feature \ 934 " not supported but called from %s\n", (func)) 935#endif /* AH_ASSERT */ 936 937/* 938 * Green Tx, Based on different RSSI of Received Beacon thresholds, 939 * using different tx power by modified register tx power related values. 940 * The thresholds are decided by system team. 941 */ 942#define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */ 943#define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */ 944#define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta 945 Calibration Offset */ 946#define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value 947 in short distance*/ 948#define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value 949 in middle distance */ 950#define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value 951 in long distance */ 952#define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen Tx 953 BB_powertx_rate9 reg 954 value in short 955 distance */ 956#define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen Tx 957 BB_powertx_rate9 reg 958 value in middle 959 distance */ 960 961 962/* Tx power for short distacnce in SwGreenTx.*/ 963static const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = { 964 6, /*ALL_TARGET_LEGACY_6_24*/ 965 6, /*ALL_TARGET_LEGACY_36*/ 966 6, /*ALL_TARGET_LEGACY_48*/ 967 4, /*ALL_TARGET_LEGACY_54*/ 968 6, /*ALL_TARGET_LEGACY_1L_5L*/ 969 6, /*ALL_TARGET_LEGACY_5S*/ 970 6, /*ALL_TARGET_LEGACY_11L*/ 971 6, /*ALL_TARGET_LEGACY_11S*/ 972 6, /*ALL_TARGET_HT20_0_8_16*/ 973 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 974 4, /*ALL_TARGET_HT20_4*/ 975 4, /*ALL_TARGET_HT20_5*/ 976 4, /*ALL_TARGET_HT20_6*/ 977 2, /*ALL_TARGET_HT20_7*/ 978 0, /*ALL_TARGET_HT20_12*/ 979 0, /*ALL_TARGET_HT20_13*/ 980 0, /*ALL_TARGET_HT20_14*/ 981 0, /*ALL_TARGET_HT20_15*/ 982 0, /*ALL_TARGET_HT20_20*/ 983 0, /*ALL_TARGET_HT20_21*/ 984 0, /*ALL_TARGET_HT20_22*/ 985 0, /*ALL_TARGET_HT20_23*/ 986 6, /*ALL_TARGET_HT40_0_8_16*/ 987 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 988 4, /*ALL_TARGET_HT40_4*/ 989 4, /*ALL_TARGET_HT40_5*/ 990 4, /*ALL_TARGET_HT40_6*/ 991 2, /*ALL_TARGET_HT40_7*/ 992 0, /*ALL_TARGET_HT40_12*/ 993 0, /*ALL_TARGET_HT40_13*/ 994 0, /*ALL_TARGET_HT40_14*/ 995 0, /*ALL_TARGET_HT40_15*/ 996 0, /*ALL_TARGET_HT40_20*/ 997 0, /*ALL_TARGET_HT40_21*/ 998 0, /*ALL_TARGET_HT40_22*/ 999 0 /*ALL_TARGET_HT40_23*/ 1000}; 1001 1002/* Tx power for middle distacnce in SwGreenTx.*/ 1003static const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = { 1004 14, /*ALL_TARGET_LEGACY_6_24*/ 1005 14, /*ALL_TARGET_LEGACY_36*/ 1006 14, /*ALL_TARGET_LEGACY_48*/ 1007 12, /*ALL_TARGET_LEGACY_54*/ 1008 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1009 14, /*ALL_TARGET_LEGACY_5S*/ 1010 14, /*ALL_TARGET_LEGACY_11L*/ 1011 14, /*ALL_TARGET_LEGACY_11S*/ 1012 14, /*ALL_TARGET_HT20_0_8_16*/ 1013 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1014 14, /*ALL_TARGET_HT20_4*/ 1015 14, /*ALL_TARGET_HT20_5*/ 1016 12, /*ALL_TARGET_HT20_6*/ 1017 10, /*ALL_TARGET_HT20_7*/ 1018 0, /*ALL_TARGET_HT20_12*/ 1019 0, /*ALL_TARGET_HT20_13*/ 1020 0, /*ALL_TARGET_HT20_14*/ 1021 0, /*ALL_TARGET_HT20_15*/ 1022 0, /*ALL_TARGET_HT20_20*/ 1023 0, /*ALL_TARGET_HT20_21*/ 1024 0, /*ALL_TARGET_HT20_22*/ 1025 0, /*ALL_TARGET_HT20_23*/ 1026 14, /*ALL_TARGET_HT40_0_8_16*/ 1027 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1028 14, /*ALL_TARGET_HT40_4*/ 1029 14, /*ALL_TARGET_HT40_5*/ 1030 12, /*ALL_TARGET_HT40_6*/ 1031 10, /*ALL_TARGET_HT40_7*/ 1032 0, /*ALL_TARGET_HT40_12*/ 1033 0, /*ALL_TARGET_HT40_13*/ 1034 0, /*ALL_TARGET_HT40_14*/ 1035 0, /*ALL_TARGET_HT40_15*/ 1036 0, /*ALL_TARGET_HT40_20*/ 1037 0, /*ALL_TARGET_HT40_21*/ 1038 0, /*ALL_TARGET_HT40_22*/ 1039 0 /*ALL_TARGET_HT40_23*/ 1040}; 1041 1042/* OLPC DeltaCalibration Offset unit in half dB.*/ 1043static const u_int8_t wb225_gtx_olpc_cal_offset[6] = { 1044 0, /* OB0*/ 1045 16, /* OB1*/ 1046 9, /* OB2*/ 1047 5, /* OB3*/ 1048 2, /* OB4*/ 1049 0, /* OB5*/ 1050}; 1051 1052/* 1053 * Definitions for HwGreenTx 1054 */ 1055#define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */ 1056#define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */ 1057#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen Tx 1058 BB_powertx_rate9 reg 1059 value in short 1060 distance */ 1061#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For HwGreenTx 1062 BB_powertx_rate9 reg 1063 value in middle 1064 distance */ 1065 1066/* Tx power for short distacnce in HwGreenTx.*/ 1067static const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = { 1068 14, /*ALL_TARGET_LEGACY_6_24*/ 1069 14, /*ALL_TARGET_LEGACY_36*/ 1070 8, /*ALL_TARGET_LEGACY_48*/ 1071 2, /*ALL_TARGET_LEGACY_54*/ 1072 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1073 14, /*ALL_TARGET_LEGACY_5S*/ 1074 14, /*ALL_TARGET_LEGACY_11L*/ 1075 14, /*ALL_TARGET_LEGACY_11S*/ 1076 12, /*ALL_TARGET_HT20_0_8_16*/ 1077 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1078 12, /*ALL_TARGET_HT20_4*/ 1079 12, /*ALL_TARGET_HT20_5*/ 1080 8, /*ALL_TARGET_HT20_6*/ 1081 2, /*ALL_TARGET_HT20_7*/ 1082 0, /*ALL_TARGET_HT20_12*/ 1083 0, /*ALL_TARGET_HT20_13*/ 1084 0, /*ALL_TARGET_HT20_14*/ 1085 0, /*ALL_TARGET_HT20_15*/ 1086 0, /*ALL_TARGET_HT20_20*/ 1087 0, /*ALL_TARGET_HT20_21*/ 1088 0, /*ALL_TARGET_HT20_22*/ 1089 0, /*ALL_TARGET_HT20_23*/ 1090 10, /*ALL_TARGET_HT40_0_8_16*/ 1091 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1092 10, /*ALL_TARGET_HT40_4*/ 1093 10, /*ALL_TARGET_HT40_5*/ 1094 6, /*ALL_TARGET_HT40_6*/ 1095 2, /*ALL_TARGET_HT40_7*/ 1096 0, /*ALL_TARGET_HT40_12*/ 1097 0, /*ALL_TARGET_HT40_13*/ 1098 0, /*ALL_TARGET_HT40_14*/ 1099 0, /*ALL_TARGET_HT40_15*/ 1100 0, /*ALL_TARGET_HT40_20*/ 1101 0, /*ALL_TARGET_HT40_21*/ 1102 0, /*ALL_TARGET_HT40_22*/ 1103 0 /*ALL_TARGET_HT40_23*/ 1104}; 1105 1106/* Tx power for middle distacnce in HwGreenTx.*/ 1107static const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = { 1108 18, /*ALL_TARGET_LEGACY_6_24*/ 1109 18, /*ALL_TARGET_LEGACY_36*/ 1110 14, /*ALL_TARGET_LEGACY_48*/ 1111 12, /*ALL_TARGET_LEGACY_54*/ 1112 18, /*ALL_TARGET_LEGACY_1L_5L*/ 1113 18, /*ALL_TARGET_LEGACY_5S*/ 1114 18, /*ALL_TARGET_LEGACY_11L*/ 1115 18, /*ALL_TARGET_LEGACY_11S*/ 1116 16, /*ALL_TARGET_HT20_0_8_16*/ 1117 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1118 16, /*ALL_TARGET_HT20_4*/ 1119 16, /*ALL_TARGET_HT20_5*/ 1120 14, /*ALL_TARGET_HT20_6*/ 1121 12, /*ALL_TARGET_HT20_7*/ 1122 0, /*ALL_TARGET_HT20_12*/ 1123 0, /*ALL_TARGET_HT20_13*/ 1124 0, /*ALL_TARGET_HT20_14*/ 1125 0, /*ALL_TARGET_HT20_15*/ 1126 0, /*ALL_TARGET_HT20_20*/ 1127 0, /*ALL_TARGET_HT20_21*/ 1128 0, /*ALL_TARGET_HT20_22*/ 1129 0, /*ALL_TARGET_HT20_23*/ 1130 14, /*ALL_TARGET_HT40_0_8_16*/ 1131 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1132 14, /*ALL_TARGET_HT40_4*/ 1133 14, /*ALL_TARGET_HT40_5*/ 1134 14, /*ALL_TARGET_HT40_6*/ 1135 12, /*ALL_TARGET_HT40_7*/ 1136 0, /*ALL_TARGET_HT40_12*/ 1137 0, /*ALL_TARGET_HT40_13*/ 1138 0, /*ALL_TARGET_HT40_14*/ 1139 0, /*ALL_TARGET_HT40_15*/ 1140 0, /*ALL_TARGET_HT40_20*/ 1141 0, /*ALL_TARGET_HT40_21*/ 1142 0, /*ALL_TARGET_HT40_22*/ 1143 0 /*ALL_TARGET_HT40_23*/ 1144}; 1145 1146/* MIMO Modes used in TPC calculations */ 1147typedef enum { 1148 AR9300_DEF_MODE = 0, /* Could be CDD or Direct */ 1149 AR9300_TXBF_MODE, 1150 AR9300_STBC_MODE 1151} AR9300_TXMODES; 1152typedef enum { 1153 POSEIDON_STORED_REG_OBDB = 0, /* default OB/DB setting from ini */ 1154 POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */ 1155 POSEIDON_STORED_REG_BB_PWRTX_RATE9 = 2, /* default txpower value in 1156 * BB_powertx_rate9 reg 1157 */ 1158 POSEIDON_STORED_REG_SZ /* Can not add anymore */ 1159} POSEIDON_STORED_REGS; 1160 1161typedef enum { 1162 POSEIDON_STORED_REG_G2_OLPC_OFFSET = 0,/* default OB/DB setting from ini */ 1163 POSEIDON_STORED_REG_G2_SZ /* should not exceed 3 */ 1164} POSEIDON_STORED_REGS_G2; 1165 1166#if AH_NEED_TX_DATA_SWAP 1167#if AH_NEED_RX_DATA_SWAP 1168#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0) 1169#else 1170#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0) 1171#endif 1172#elif AH_NEED_RX_DATA_SWAP 1173#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0) 1174#else 1175#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0) 1176#endif 1177 1178extern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *); 1179 1180struct ath_hal; 1181 1182extern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, 1183 HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1184 HAL_STATUS *status); 1185extern struct ath_hal * ar9300_attach(u_int16_t devid, 1186 HAL_SOFTC sc, HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1187 HAL_STATUS *status); 1188extern void ar9300_detach(struct ath_hal *ah); 1189extern void ar9300_read_revisions(struct ath_hal *ah); 1190extern HAL_BOOL ar9300_chip_test(struct ath_hal *ah); 1191extern HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah, 1192 u_int16_t flags, u_int16_t *low, u_int16_t *high); 1193extern HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah); 1194 1195extern void ar9300_beacon_init(struct ath_hal *ah, 1196 u_int32_t next_beacon, u_int32_t beacon_period, HAL_OPMODE opmode); 1197extern void ar9300_set_sta_beacon_timers(struct ath_hal *ah, 1198 const HAL_BEACON_STATE *); 1199 1200extern HAL_BOOL ar9300_is_interrupt_pending(struct ath_hal *ah); 1201extern HAL_BOOL ar9300_get_pending_interrupts(struct ath_hal *ah, HAL_INT *, HAL_INT_TYPE, u_int8_t, HAL_BOOL); 1202extern HAL_INT ar9300_get_interrupts(struct ath_hal *ah); 1203extern HAL_INT ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL); 1204extern void ar9300_set_intr_mitigation_timer(struct ath_hal* ah, 1205 HAL_INT_MITIGATION reg, u_int32_t value); 1206extern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah, 1207 HAL_INT_MITIGATION reg); 1208extern u_int32_t ar9300_get_key_cache_size(struct ath_hal *); 1209extern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry); 1210extern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry); 1211extern HAL_CHANNEL_INTERNAL * ar9300_check_chan(struct ath_hal *ah, 1212 const struct ieee80211_channel *chan); 1213 1214extern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *, 1215 u_int16_t entry, const u_int8_t *mac); 1216extern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, 1217 const HAL_KEYVAL *k, const u_int8_t *mac, int xor_key); 1218extern HAL_BOOL ar9300_print_keycache(struct ath_hal *ah); 1219 1220extern void ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac); 1221extern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *); 1222extern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac); 1223extern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *); 1224extern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg); 1225extern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah, 1226 u_int16_t reg_domain, HAL_STATUS *stats); 1227extern u_int ar9300_get_wireless_modes(struct ath_hal *ah); 1228extern void ar9300_enable_rf_kill(struct ath_hal *); 1229extern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); 1230extern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_MUX_TYPE signalType); 1231extern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio); 1232extern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val); 1233extern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio); 1234extern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah); 1235extern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel); 1236extern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah); 1237extern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t); 1238extern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah); 1239extern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map); 1240extern void ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state); 1241extern void ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enable); 1242extern void ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enable); 1243extern void ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 1244 u_int16_t assoc_id); 1245extern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *); 1246extern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *); 1247extern int ar9300_ppm_get_trigger(struct ath_hal *); 1248extern u_int32_t ar9300_ppm_force(struct ath_hal *); 1249extern void ar9300_ppm_un_force(struct ath_hal *); 1250extern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); 1251extern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t); 1252extern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah); 1253extern u_int32_t ar9300_get_tsf32(struct ath_hal *ah); 1254extern u_int64_t ar9300_get_tsf64(struct ath_hal *ah); 1255extern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah); 1256extern void ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf); 1257extern void ar9300_reset_tsf(struct ath_hal *ah); 1258extern void ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *pSet); 1259extern u_int32_t ar9300_get_random_seed(struct ath_hal *ah); 1260extern HAL_BOOL ar9300_detect_card_present(struct ath_hal *ah); 1261extern void ar9300_update_mib_mac_stats(struct ath_hal *ah); 1262extern void ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats); 1263extern HAL_BOOL ar9300_is_japan_channel_spread_supported(struct ath_hal *ah); 1264extern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah); 1265extern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah); 1266extern u_int ar9300_get_def_antenna(struct ath_hal *ah); 1267extern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna); 1268extern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah, 1269 HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 1270 u_int8_t *, u_int8_t *, u_int8_t *); 1271extern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah); 1272extern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int); 1273extern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int); 1274extern u_int ar9300_get_ack_timeout(struct ath_hal *); 1275extern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 1276 u_int32_t next_start, HAL_QUIET_FLAG flag); 1277extern void ar9300_set_pcu_config(struct ath_hal *); 1278extern HAL_STATUS ar9300_get_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1279 u_int32_t, u_int32_t *); 1280extern HAL_BOOL ar9300_set_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1281 u_int32_t, u_int32_t, HAL_STATUS *); 1282extern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request, 1283 const void *args, u_int32_t argsize, 1284 void **result, u_int32_t *resultsize); 1285extern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); 1286extern uint32_t ar9300_get_11n_ext_busy(struct ath_hal *ah); 1287extern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); 1288extern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah); 1289extern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); 1290extern HAL_BOOL ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, 1291 int set_chip); 1292extern HAL_POWER_MODE ar9300_get_power_mode(struct ath_hal *ah); 1293extern HAL_BOOL ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip); 1294extern void ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode); 1295 1296extern void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off); 1297 1298extern void ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 1299 u_int16_t assoc_id); 1300 1301 1302#if ATH_WOW 1303extern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_pattern, 1304 u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len); 1305//extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes); 1306extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable); 1307extern bool ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, 1308 HAL_BOOL offloadEnable); 1309#if ATH_WOW_OFFLOAD 1310/* ARP offload */ 1311#define WOW_OFFLOAD_ARP_INFO_MAX 2 1312 1313struct hal_wow_offload_arp_info { 1314 u_int32_t valid; 1315 u_int32_t id; 1316 1317 u_int32_t Flags; 1318 union { 1319 u_int8_t u8[4]; 1320 u_int32_t u32; 1321 } RemoteIPv4Address; 1322 union { 1323 u_int8_t u8[4]; 1324 u_int32_t u32; 1325 } HostIPv4Address; 1326 union { 1327 u_int8_t u8[6]; 1328 u_int32_t u32[2]; 1329 } MacAddress; 1330}; 1331 1332/* NS offload */ 1333#define WOW_OFFLOAD_NS_INFO_MAX 2 1334 1335struct hal_wow_offload_ns_info { 1336 u_int32_t valid; 1337 u_int32_t id; 1338 1339 u_int32_t Flags; 1340 union { 1341 u_int8_t u8[16]; 1342 u_int32_t u32[4]; 1343 } RemoteIPv6Address; 1344 union { 1345 u_int8_t u8[16]; 1346 u_int32_t u32[4]; 1347 } SolicitedNodeIPv6Address; 1348 union { 1349 u_int8_t u8[6]; 1350 u_int32_t u32[2]; 1351 } MacAddress; 1352 union { 1353 u_int8_t u8[16]; 1354 u_int32_t u32[4]; 1355 } TargetIPv6Addresses[2]; 1356}; 1357 1358extern void ar9300_wowoffload_prep(struct ath_hal *ah); 1359extern void ar9300_wowoffload_post(struct ath_hal *ah); 1360extern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size); 1361extern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param); 1362extern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes); 1363extern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap); 1364extern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1365extern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1366#endif /* ATH_WOW_OFFLOAD */ 1367#endif 1368 1369extern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, 1370 struct ieee80211_channel *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, 1371 u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing, 1372 HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan); 1373extern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan, 1374 HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask); 1375extern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type); 1376extern void ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan); 1377extern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask); 1378extern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah); 1379extern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode); 1380extern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah); 1381extern HAL_BOOL ar9300_disable(struct ath_hal *ah); 1382extern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *); 1383extern HAL_BOOL ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, 1384 u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals); 1385extern void ar9300_reset_cal_valid(struct ath_hal *ah, 1386 const struct ieee80211_channel *chan, 1387 HAL_BOOL *isIQdone, u_int32_t cal_type); 1388extern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains); 1389extern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains); 1390extern void ar9300_temp_comp_cal_collect(struct ath_hal *ah); 1391extern void ar9300_temp_comp_calibration(struct ath_hal *ah, u_int8_t num_chains); 1392extern int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah); 1393extern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfarray[]); 1394 1395extern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, 1396 u_int16_t extra_txpow, u_int16_t tpc_in_db); 1397extern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, 1398 struct ieee80211_channel *chan, int is_scan); 1399extern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]); 1400 1401extern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah); 1402extern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode); 1403extern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, 1404 u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode); 1405extern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, 1406 const struct ieee80211_channel *chan, 1407 u_int8_t powerPerRate[], 1408 u_int8_t chainmask); 1409extern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, 1410 u_int8_t powerPerRate[]); 1411extern HAL_STATUS ath_hal_get_rate_power_limit_from_eeprom(struct ath_hal *ah, 1412 u_int16_t freq, int8_t *max_rate_power, int8_t *min_rate_power); 1413 1414extern void ar9300_reset_tx_status_ring(struct ath_hal *ah); 1415extern void ar9300_enable_mib_counters(struct ath_hal *); 1416extern void ar9300_disable_mib_counters(struct ath_hal *); 1417extern void ar9300_ani_attach(struct ath_hal *); 1418extern void ar9300_ani_detach(struct ath_hal *); 1419extern struct ar9300_ani_state *ar9300_ani_get_current_state(struct ath_hal *); 1420extern struct ar9300_stats *ar9300_ani_get_current_stats(struct ath_hal *); 1421extern HAL_BOOL ar9300_ani_control(struct ath_hal *, HAL_ANI_CMD cmd, int param); 1422struct ath_rx_status; 1423 1424extern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *); 1425extern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *, 1426 const struct ieee80211_channel *, HAL_ANISTATS *); 1427extern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning); 1428extern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode); 1429extern void ar9300_enable_tpc(struct ath_hal *); 1430 1431extern HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is2GHz); 1432extern void ar9300_rx_gain_table_apply(struct ath_hal *ah); 1433extern void ar9300_tx_gain_table_apply(struct ath_hal *ah); 1434extern void ar9300_mat_enable(struct ath_hal *ah, int enable); 1435extern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry); 1436extern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, const struct ieee80211_channel * chan); 1437 1438/* BB Panic Watchdog declarations */ 1439#define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */ 1440#define HAL_BB_PANIC_WD_TMO_HORNET 85 1441extern void ar9300_config_bb_panic_watchdog(struct ath_hal *); 1442extern void ar9300_handle_bb_panic(struct ath_hal *); 1443extern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic); 1444extern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah); 1445extern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason); 1446 1447/* DFS declarations */ 1448extern void ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan); 1449extern void ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, 1450 u_int64_t nolTime); 1451extern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1452extern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1453extern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan); 1454extern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah, 1455 u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, 1456 int *numb5radars, HAL_PHYERR_PARAM *pe); 1457extern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val); 1458extern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable); 1459extern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable); 1460extern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start); 1461 1462extern struct ieee80211_channel * ar9300_get_extension_channel(struct ath_hal *ah); 1463extern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah); 1464 1465 1466extern void ar9300_mark_phy_inactive(struct ath_hal *ah); 1467 1468/* Spectral scan declarations */ 1469extern void ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1470extern void ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62); 1471extern void ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1472extern HAL_BOOL ar9300_is_spectral_active(struct ath_hal *ah); 1473extern HAL_BOOL ar9300_is_spectral_enabled(struct ath_hal *ah); 1474extern void ar9300_start_spectral_scan(struct ath_hal *ah); 1475extern void ar9300_stop_spectral_scan(struct ath_hal *ah); 1476extern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah); 1477extern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval); 1478int16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah); 1479int16_t ar9300_get_ext_chan_nf(struct ath_hal *ah); 1480/* End spectral scan declarations */ 1481 1482/* Raw ADC capture functions */ 1483extern void ar9300_enable_test_addac_mode(struct ath_hal *ah); 1484extern void ar9300_disable_test_addac_mode(struct ath_hal *ah); 1485extern void ar9300_begin_adc_capture(struct ath_hal *ah, int auto_agc_gain); 1486extern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples); 1487extern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, int16_t *sample_min, int16_t *sample_max, int32_t *chain_ref_pwr, int num_chain_ref_pwr); 1488extern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain); 1489 1490extern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode, 1491 struct ieee80211_channel *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); 1492extern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now); 1493 1494extern void ar9300_get_channel_centers(struct ath_hal *ah, 1495 const struct ieee80211_channel *chan, 1496 CHAN_CENTERS *centers); 1497extern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah, 1498 const struct ieee80211_channel *chan); 1499extern u_int16_t ar9300_get_ext_center(struct ath_hal *ah, 1500 const struct ieee80211_channel *chan); 1501extern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*); 1502 1503extern void ar9300_dma_reg_dump(struct ath_hal *); 1504extern HAL_BOOL ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable); 1505extern HAL_BOOL ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable); 1506extern HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable); 1507extern HAL_BOOL ar9300_detect_bb_hang(struct ath_hal *ah); 1508extern HAL_BOOL ar9300_detect_mac_hang(struct ath_hal *ah); 1509 1510#ifdef ATH_BT_COEX 1511extern void ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo); 1512extern void ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf); 1513extern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum); 1514extern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1515extern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh); 1516extern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value); 1517extern void ar9300_bt_coex_disable(struct ath_hal *ah); 1518extern int ar9300_bt_coex_enable(struct ath_hal *ah); 1519extern void ar9300_init_bt_coex(struct ath_hal *ah); 1520extern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg); 1521extern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn); 1522#endif 1523extern int ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf); 1524extern void ar9300_free_generic_timer(struct ath_hal *ah, int index); 1525extern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next, 1526 u_int32_t timer_period); 1527extern void ar9300_stop_generic_timer(struct ath_hal *ah, int index); 1528extern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger, 1529 u_int32_t *thresh); 1530extern void ar9300_start_tsf2(struct ath_hal *ah); 1531 1532extern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi); 1533extern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah); 1534extern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah); 1535extern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value); 1536extern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); 1537extern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah); 1538extern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah); 1539extern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 1540 u_int32_t rssi_threshold); 1541extern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah); 1542extern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on); 1543extern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats, 1544 u_int8_t); 1545 1546extern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq); 1547extern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq); 1548extern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah); 1549extern HAL_BOOL ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_SURVEY_SAMPLE *); 1550extern void ar9300_clear_mib_counters(struct ath_hal *ah); 1551 1552/* EEPROM interface functions */ 1553/* Common Interface functions */ 1554extern HAL_STATUS ar9300_eeprom_attach(struct ath_hal *); 1555extern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param); 1556 1557extern u_int32_t ar9300_ini_fixup(struct ath_hal *ah, 1558 ar9300_eeprom_t *p_eep_data, 1559 u_int32_t reg, 1560 u_int32_t val); 1561 1562extern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah, 1563 ar9300_eeprom_t *p_eep_data, const struct ieee80211_channel *chan, 1564 u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction, 1565 u_int16_t twice_max_regulatory_power, u_int16_t power_limit); 1566extern void ar9300_eeprom_set_addac(struct ath_hal *, struct ieee80211_channel *); 1567extern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value); 1568extern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, const struct ieee80211_channel *); 1569extern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data); 1570extern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 1571extern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi); 1572 1573extern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data); 1574extern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data); 1575extern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e); 1576extern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band); 1577extern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, const struct ieee80211_channel *chan, 1578 u_int8_t index, u_int16_t *config); 1579extern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp); 1580extern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz); 1581extern HAL_BOOL ar9300_interference_is_present(struct ath_hal *ah); 1582extern HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah); 1583extern void ar9300_disp_tpc_tables(struct ath_hal *ah); 1584extern u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah); 1585extern u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, int *tx_gain_max); 1586extern u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel); 1587 1588/* Common EEPROM Help function */ 1589extern void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable); 1590extern void ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs); 1591 1592extern u_int ar9300_mac_to_clks(struct ath_hal *ah, u_int clks); 1593 1594/* tx_bf interface */ 1595#define ar9300_init_txbf(ah) 1596#define ar9300_set_11n_txbf_sounding(ah, ds, series, cec, opt) 1597#define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 1598#define ar9300_txbf_save_cv_from_compress( \ 1599 ah, key_idx, mimo_control, compress_rpt) \ 1600 false 1601#define ar9300_txbf_save_cv_from_non_compress( \ 1602 ah, key_idx, mimo_control, non_compress_rpt) \ 1603 false 1604#define ar9300_txbf_rc_update( \ 1605 ah, rx_status, local_h, csi_frame, ness_a, ness_b, bw) \ 1606 false 1607#define ar9300_fill_csi_frame( \ 1608 ah, rx_status, bandwidth, local_h, csi_frame_body) \ 1609 0 1610#define ar9300_fill_txbf_capabilities(ah) 1611#define ar9300_get_txbf_capabilities(ah) NULL 1612#define ar9300_txbf_set_key( \ 1613 ah, entry, rx_staggered_sounding, channel_estimation_cap, mmss) 1614#define ar9300_read_key_cache_mac(ah, entry, mac) false 1615#define ar9300_txbf_get_cv_cache_nr(ah, key_idx, nr) 1616#define ar9300_set_selfgenrate_limit(ah, ts_ratecode) 1617#define ar9300_reset_lowest_txrate(ah) 1618#define ar9300_txbf_set_basic_set(ah) 1619 1620extern void ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs); 1621extern void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah); 1622 1623 1624 1625#if ATH_SUPPORT_MCI 1626extern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1627extern void ar9300_mci_bt_coex_disable(struct ath_hal *ah); 1628extern int ar9300_mci_bt_coex_enable(struct ath_hal *ah); 1629extern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr, 1630 void *gpm_buf, u_int16_t len, 1631 u_int32_t sched_addr); 1632extern void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done); 1633extern void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done); 1634extern void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done); 1635extern HAL_BOOL ar9300_mci_send_message (struct ath_hal *ah, u_int8_t header, 1636 u_int32_t flag, u_int32_t *payload, u_int8_t len, 1637 HAL_BOOL wait_done, HAL_BOOL check_bt); 1638extern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah, 1639 u_int32_t *mci_int, 1640 u_int32_t *mci_int_rx_msg); 1641extern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data); 1642extern void ar9300_mci_reset (struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, HAL_BOOL is_full_sleep); 1643extern void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, HAL_BOOL halt, HAL_BOOL wait_done); 1644extern void ar9300_mci_mute_bt(struct ath_hal *ah); 1645extern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out); 1646extern void ar9300_mci_enable_interrupt(struct ath_hal *ah); 1647extern void ar9300_mci_disable_interrupt(struct ath_hal *ah); 1648extern void ar9300_mci_detach (struct ath_hal *ah); 1649extern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints); 1650extern void ar9300_mci_sync_bt_state (struct ath_hal *ah); 1651extern void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g); 1652extern void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done); 1653#if ATH_SUPPORT_AIC 1654extern u_int32_t ar9300_aic_calibration (struct ath_hal *ah); 1655extern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah); 1656#endif 1657#endif 1658 1659extern HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable); 1660 1661extern HAL_BOOL ar9300_regulatory_domain_override( 1662 struct ath_hal *ah, u_int16_t regdmn); 1663#if ATH_ANT_DIV_COMB 1664extern void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1665extern void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1666#endif /* ATH_ANT_DIV_COMB */ 1667extern void ar9300_disable_phy_restart(struct ath_hal *ah, 1668 int disable_phy_restart); 1669extern void ar9300_enable_keysearch_always(struct ath_hal *ah, int enable); 1670extern HAL_BOOL ar9300ForceVCS( struct ath_hal *ah); 1671extern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val); 1672extern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah); 1673 1674#ifdef ATH_TX99_DIAG 1675#ifndef ATH_SUPPORT_HTC 1676extern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, struct ieee80211_channel *c, u_int32_t txpower); 1677extern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask); 1678extern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype); 1679extern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data); 1680extern void ar9300_tx99_stop(struct ath_hal *ah); 1681#endif /* ATH_SUPPORT_HTC */ 1682#endif /* ATH_TX99_DIAG */ 1683 1684enum { 1685 AR9300_COEFF_TX_TYPE = 0, 1686 AR9300_COEFF_RX_TYPE 1687}; 1688 1689#endif /* _ATH_AR9300_H_ */ 1690