ar9300.h revision 250003
1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#ifndef _ATH_AR9300_H_ 18250003Sadrian#define _ATH_AR9300_H_ 19250003Sadrian 20250003Sadrian#include "ah_internal.h" 21250003Sadrian#include "ah_eeprom.h" 22250003Sadrian#include "ah_devid.h" 23250003Sadrian#include "ar9300eep.h" /* For Eeprom definitions */ 24250003Sadrian#include "asf_amem.h" 25250003Sadrian 26250003Sadrian 27250003Sadrian#define AR9300_MAGIC 0x19741014 28250003Sadrian 29250003Sadrian 30250003Sadrian/* MAC register values */ 31250003Sadrian 32250003Sadrian#define INIT_CONFIG_STATUS 0x00000000 33250003Sadrian#define INIT_RSSI_THR 0x7 /* Missed beacon counter initialized to 0x7 (max is 0xff) */ 34250003Sadrian#define INIT_RSSI_BEACON_WEIGHT 8 /* ave beacon rssi weight (0-16) */ 35250003Sadrian 36250003Sadrian/* 37250003Sadrian * Various fifo fill before Tx start, in 64-byte units 38250003Sadrian * i.e. put the frame in the air while still DMAing 39250003Sadrian */ 40250003Sadrian#define MIN_TX_FIFO_THRESHOLD 0x1 41250003Sadrian#define MAX_TX_FIFO_THRESHOLD (( 4096 / 64) - 1) 42250003Sadrian#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 43250003Sadrian 44250003Sadrian #define CHANSEL_DIV 15 45250003Sadrian #define FCLK 40 46250003Sadrian 47250003Sadrian#define COEFF ((FCLK * 5) / 2) 48250003Sadrian#define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) 49250003Sadrian#define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) 50250003Sadrian#define CHANSEL_5G_DOT5MHZ 2188 51250003Sadrian 52250003Sadrian/* 53250003Sadrian * Receive Queue Fifo depth. 54250003Sadrian */ 55250003Sadrianenum RX_FIFO_DEPTH { 56250003Sadrian HAL_HP_RXFIFO_DEPTH = 16, 57250003Sadrian HAL_LP_RXFIFO_DEPTH = 128, 58250003Sadrian}; 59250003Sadrian 60250003Sadrian/* 61250003Sadrian * Gain support. 62250003Sadrian */ 63250003Sadrian#define NUM_CORNER_FIX_BITS_2133 7 64250003Sadrian#define CCK_OFDM_GAIN_DELTA 15 65250003Sadrian 66250003Sadrianenum GAIN_PARAMS { 67250003Sadrian GP_TXCLIP, 68250003Sadrian GP_PD90, 69250003Sadrian GP_PD84, 70250003Sadrian GP_GSEL 71250003Sadrian}; 72250003Sadrian 73250003Sadrianenum GAIN_PARAMS_2133 { 74250003Sadrian GP_MIXGAIN_OVR, 75250003Sadrian GP_PWD_138, 76250003Sadrian GP_PWD_137, 77250003Sadrian GP_PWD_136, 78250003Sadrian GP_PWD_132, 79250003Sadrian GP_PWD_131, 80250003Sadrian GP_PWD_130, 81250003Sadrian}; 82250003Sadrian 83250003Sadrianenum { 84250003Sadrian HAL_RESET_POWER_ON, 85250003Sadrian HAL_RESET_WARM, 86250003Sadrian HAL_RESET_COLD, 87250003Sadrian}; 88250003Sadrian 89250003Sadriantypedef struct _gain_opt_step { 90250003Sadrian int16_t paramVal[NUM_CORNER_FIX_BITS_2133]; 91250003Sadrian int32_t stepGain; 92250003Sadrian int8_t stepName[16]; 93250003Sadrian} GAIN_OPTIMIZATION_STEP; 94250003Sadrian 95250003Sadriantypedef struct { 96250003Sadrian u_int32_t numStepsInLadder; 97250003Sadrian u_int32_t defaultStepNum; 98250003Sadrian GAIN_OPTIMIZATION_STEP optStep[10]; 99250003Sadrian} GAIN_OPTIMIZATION_LADDER; 100250003Sadrian 101250003Sadriantypedef struct { 102250003Sadrian u_int32_t currStepNum; 103250003Sadrian u_int32_t currGain; 104250003Sadrian u_int32_t targetGain; 105250003Sadrian u_int32_t loTrig; 106250003Sadrian u_int32_t hiTrig; 107250003Sadrian u_int32_t gainFCorrection; 108250003Sadrian u_int32_t active; 109250003Sadrian GAIN_OPTIMIZATION_STEP *curr_step; 110250003Sadrian} GAIN_VALUES; 111250003Sadrian 112250003Sadriantypedef struct { 113250003Sadrian u_int16_t synth_center; 114250003Sadrian u_int16_t ctl_center; 115250003Sadrian u_int16_t ext_center; 116250003Sadrian} CHAN_CENTERS; 117250003Sadrian 118250003Sadrian/* RF HAL structures */ 119250003Sadriantypedef struct rf_hal_funcs { 120250003Sadrian HAL_BOOL (*set_channel)(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 121250003Sadrian HAL_BOOL (*get_chip_power_lim)(struct ath_hal *ah, HAL_CHANNEL *chans, 122250003Sadrian u_int32_t nchancs); 123250003Sadrian} RF_HAL_FUNCS; 124250003Sadrian 125250003Sadrianstruct ar9300_ani_default { 126250003Sadrian u_int16_t m1_thresh_low; 127250003Sadrian u_int16_t m2_thresh_low; 128250003Sadrian u_int16_t m1_thresh; 129250003Sadrian u_int16_t m2_thresh; 130250003Sadrian u_int16_t m2_count_thr; 131250003Sadrian u_int16_t m2_count_thr_low; 132250003Sadrian u_int16_t m1_thresh_low_ext; 133250003Sadrian u_int16_t m2_thresh_low_ext; 134250003Sadrian u_int16_t m1_thresh_ext; 135250003Sadrian u_int16_t m2_thresh_ext; 136250003Sadrian u_int16_t firstep; 137250003Sadrian u_int16_t firstep_low; 138250003Sadrian u_int16_t cycpwr_thr1; 139250003Sadrian u_int16_t cycpwr_thr1_ext; 140250003Sadrian}; 141250003Sadrian 142250003Sadrian/* 143250003Sadrian * Per-channel ANI state private to the driver. 144250003Sadrian */ 145250003Sadrianstruct ar9300_ani_state { 146250003Sadrian HAL_CHANNEL c; 147250003Sadrian HAL_BOOL must_restore; 148250003Sadrian HAL_BOOL ofdms_turn; 149250003Sadrian u_int8_t ofdm_noise_immunity_level; 150250003Sadrian u_int8_t cck_noise_immunity_level; 151250003Sadrian u_int8_t spur_immunity_level; 152250003Sadrian u_int8_t firstep_level; 153250003Sadrian u_int8_t ofdm_weak_sig_detect_off; 154250003Sadrian u_int8_t mrc_cck_off; 155250003Sadrian 156250003Sadrian /* Thresholds */ 157250003Sadrian u_int32_t listen_time; 158250003Sadrian u_int32_t ofdm_trig_high; 159250003Sadrian u_int32_t ofdm_trig_low; 160250003Sadrian int32_t cck_trig_high; 161250003Sadrian int32_t cck_trig_low; 162250003Sadrian int32_t rssi_thr_low; 163250003Sadrian int32_t rssi_thr_high; 164250003Sadrian 165250003Sadrian int32_t rssi; /* The current RSSI */ 166250003Sadrian u_int32_t tx_frame_count; /* Last tx_frame_count */ 167250003Sadrian u_int32_t rx_frame_count; /* Last rx Frame count */ 168250003Sadrian u_int32_t cycle_count; /* Last cycle_count (can detect wrap-around) */ 169250003Sadrian u_int32_t ofdm_phy_err_count;/* OFDM err count since last reset */ 170250003Sadrian u_int32_t cck_phy_err_count; /* CCK err count since last reset */ 171250003Sadrian 172250003Sadrian struct ar9300_ani_default ini_def; /* INI default values for ANI registers */ 173250003Sadrian HAL_BOOL phy_noise_spur; /* based on OFDM/CCK Phy errors */ 174250003Sadrian}; 175250003Sadrian 176250003Sadrian#define AR9300_ANI_POLLINTERVAL 1000 /* 1000 milliseconds between ANI poll */ 177250003Sadrian 178250003Sadrian#define AR9300_CHANNEL_SWITCH_TIME_USEC 1000 /* 1 millisecond needed to change channels */ 179250003Sadrian 180250003Sadrian#define HAL_PROCESS_ANI 0x00000001 /* ANI state setup */ 181250003Sadrian#define HAL_RADAR_EN 0x80000000 /* Radar detect is capable */ 182250003Sadrian#define HAL_AR_EN 0x40000000 /* AR detect is capable */ 183250003Sadrian 184250003Sadrian#define DO_ANI(ah) \ 185250003Sadrian ((AH9300(ah)->ah_proc_phy_err & HAL_PROCESS_ANI)) 186250003Sadrian 187250003Sadrianstruct ar9300_stats { 188250003Sadrian u_int32_t ast_ani_niup; /* ANI increased noise immunity */ 189250003Sadrian u_int32_t ast_ani_nidown; /* ANI decreased noise immunity */ 190250003Sadrian u_int32_t ast_ani_spurup; /* ANI increased spur immunity */ 191250003Sadrian u_int32_t ast_ani_spurdown;/* ANI descreased spur immunity */ 192250003Sadrian u_int32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */ 193250003Sadrian u_int32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */ 194250003Sadrian u_int32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */ 195250003Sadrian u_int32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */ 196250003Sadrian u_int32_t ast_ani_stepup; /* ANI increased first step level */ 197250003Sadrian u_int32_t ast_ani_stepdown;/* ANI decreased first step level */ 198250003Sadrian u_int32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */ 199250003Sadrian u_int32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */ 200250003Sadrian u_int32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */ 201250003Sadrian u_int32_t ast_ani_lzero; /* ANI listen time forced to zero */ 202250003Sadrian u_int32_t ast_ani_lneg; /* ANI listen time calculated < 0 */ 203250003Sadrian HAL_MIB_STATS ast_mibstats; /* MIB counter stats */ 204250003Sadrian HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */ 205250003Sadrian}; 206250003Sadrian 207250003Sadrianstruct ar9300_rad_reader { 208250003Sadrian u_int16_t rd_index; 209250003Sadrian u_int16_t rd_expSeq; 210250003Sadrian u_int32_t rd_resetVal; 211250003Sadrian u_int8_t rd_start; 212250003Sadrian}; 213250003Sadrian 214250003Sadrianstruct ar9300_rad_writer { 215250003Sadrian u_int16_t wr_index; 216250003Sadrian u_int16_t wr_seq; 217250003Sadrian}; 218250003Sadrian 219250003Sadrianstruct ar9300_radar_event { 220250003Sadrian u_int32_t re_ts; /* 32 bit time stamp */ 221250003Sadrian u_int8_t re_rssi; /* rssi of radar event */ 222250003Sadrian u_int8_t re_dur; /* duration of radar pulse */ 223250003Sadrian u_int8_t re_chanIndex; /* Channel of event */ 224250003Sadrian}; 225250003Sadrian 226250003Sadrianstruct ar9300_radar_q_elem { 227250003Sadrian u_int32_t rq_seqNum; 228250003Sadrian u_int32_t rq_busy; /* 32 bit to insure atomic read/write */ 229250003Sadrian struct ar9300_radar_event rq_event; /* Radar event */ 230250003Sadrian}; 231250003Sadrian 232250003Sadrianstruct ar9300_radar_q_info { 233250003Sadrian u_int16_t ri_qsize; /* q size */ 234250003Sadrian u_int16_t ri_seqSize; /* Size of sequence ring */ 235250003Sadrian struct ar9300_rad_reader ri_reader; /* State for the q reader */ 236250003Sadrian struct ar9300_rad_writer ri_writer; /* state for the q writer */ 237250003Sadrian}; 238250003Sadrian 239250003Sadrian#define HAL_MAX_ACK_RADAR_DUR 511 240250003Sadrian#define HAL_MAX_NUM_PEAKS 3 241250003Sadrian#define HAL_ARQ_SIZE 4096 /* 8K AR events for buffer size */ 242250003Sadrian#define HAL_ARQ_SEQSIZE 4097 /* Sequence counter wrap for AR */ 243250003Sadrian#define HAL_RADARQ_SIZE 1024 /* 1K radar events for buffer size */ 244250003Sadrian#define HAL_RADARQ_SEQSIZE 1025 /* Sequence counter wrap for radar */ 245250003Sadrian#define HAL_NUMRADAR_STATES 64 /* Number of radar channels we keep state for */ 246250003Sadrian 247250003Sadrianstruct ar9300_ar_state { 248250003Sadrian u_int16_t ar_prev_time_stamp; 249250003Sadrian u_int32_t ar_prev_width; 250250003Sadrian u_int32_t ar_phy_err_count[HAL_MAX_ACK_RADAR_DUR]; 251250003Sadrian u_int32_t ar_ack_sum; 252250003Sadrian u_int16_t ar_peak_list[HAL_MAX_NUM_PEAKS]; 253250003Sadrian u_int32_t ar_packet_threshold; /* Thresh to determine traffic load */ 254250003Sadrian u_int32_t ar_par_threshold; /* Thresh to determine peak */ 255250003Sadrian u_int32_t ar_radar_rssi; /* Rssi threshold for AR event */ 256250003Sadrian}; 257250003Sadrian 258250003Sadrianstruct ar9300_radar_state { 259250003Sadrian HAL_CHANNEL_INTERNAL *rs_chan; /* Channel info */ 260250003Sadrian u_int8_t rs_chan_index; /* Channel index in radar structure */ 261250003Sadrian u_int32_t rs_num_radar_events; /* Number of radar events */ 262250003Sadrian int32_t rs_firpwr; /* Thresh to check radar sig is gone */ 263250003Sadrian u_int32_t rs_radar_rssi; /* Thresh to start radar det (dB) */ 264250003Sadrian u_int32_t rs_height; /* Thresh for pulse height (dB)*/ 265250003Sadrian u_int32_t rs_pulse_rssi; /* Thresh to check if pulse is gone (dB) */ 266250003Sadrian u_int32_t rs_inband; /* Thresh to check if pusle is inband (0.5 dB) */ 267250003Sadrian}; 268250003Sadriantypedef struct { 269250003Sadrian u_int8_t uc_receiver_errors; 270250003Sadrian u_int8_t uc_bad_tlp_errors; 271250003Sadrian u_int8_t uc_bad_dllp_errors; 272250003Sadrian u_int8_t uc_replay_timeout_errors; 273250003Sadrian u_int8_t uc_replay_number_rollover_errors; 274250003Sadrian} ar_pcie_error_moniter_counters; 275250003Sadrian 276250003Sadrian#define AR9300_OPFLAGS_11A 0x01 /* if set, allow 11a */ 277250003Sadrian#define AR9300_OPFLAGS_11G 0x02 /* if set, allow 11g */ 278250003Sadrian#define AR9300_OPFLAGS_N_5G_HT40 0x04 /* if set, disable 5G HT40 */ 279250003Sadrian#define AR9300_OPFLAGS_N_2G_HT40 0x08 /* if set, disable 2G HT40 */ 280250003Sadrian#define AR9300_OPFLAGS_N_5G_HT20 0x10 /* if set, disable 5G HT20 */ 281250003Sadrian#define AR9300_OPFLAGS_N_2G_HT20 0x20 /* if set, disable 2G HT20 */ 282250003Sadrian 283250003Sadrian/* 284250003Sadrian * For Kite and later chipsets, the following bits are not being programmed in EEPROM 285250003Sadrian * and so need to be enabled always. 286250003Sadrian * Bit 0: en_fcc_mid, Bit 1: en_jap_mid, Bit 2: en_fcc_dfs_ht40 287250003Sadrian * Bit 3: en_jap_ht40, Bit 4: en_jap_dfs_ht40 288250003Sadrian */ 289250003Sadrian#define AR9300_RDEXT_DEFAULT 0x1F 290250003Sadrian 291250003Sadrian#define AR9300_MAX_CHAINS 3 292250003Sadrian#define AR9300_NUM_CHAINS(chainmask) \ 293250003Sadrian (((chainmask >> 2) & 1) + ((chainmask >> 1) & 1) + (chainmask & 1)) 294250003Sadrian#define AR9300_CHAIN0_MASK 0x1 295250003Sadrian#define AR9300_CHAIN1_MASK 0x2 296250003Sadrian#define AR9300_CHAIN2_MASK 0x4 297250003Sadrian 298250003Sadrian/* Support for multiple INIs */ 299250003Sadrianstruct ar9300_ini_array { 300250003Sadrian u_int32_t *ia_array; 301250003Sadrian u_int32_t ia_rows; 302250003Sadrian u_int32_t ia_columns; 303250003Sadrian}; 304250003Sadrian#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 305250003Sadrian (iniarray)->ia_array = (u_int32_t *)(array); \ 306250003Sadrian (iniarray)->ia_rows = (rows); \ 307250003Sadrian (iniarray)->ia_columns = (columns); \ 308250003Sadrian} while (0) 309250003Sadrian#define INI_RA(iniarray, row, column) (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)]) 310250003Sadrian 311250003Sadrian#define INIT_CAL(_perCal) \ 312250003Sadrian (_perCal)->cal_state = CAL_WAITING; \ 313250003Sadrian (_perCal)->cal_next = AH_NULL; 314250003Sadrian 315250003Sadrian#define INSERT_CAL(_ahp, _perCal) \ 316250003Sadriando { \ 317250003Sadrian if ((_ahp)->ah_cal_list_last == AH_NULL) { \ 318250003Sadrian (_ahp)->ah_cal_list = (_ahp)->ah_cal_list_last = (_perCal); \ 319250003Sadrian ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 320250003Sadrian } else { \ 321250003Sadrian ((_ahp)->ah_cal_list_last)->cal_next = (_perCal); \ 322250003Sadrian (_ahp)->ah_cal_list_last = (_perCal); \ 323250003Sadrian (_perCal)->cal_next = (_ahp)->ah_cal_list; \ 324250003Sadrian } \ 325250003Sadrian} while (0) 326250003Sadrian 327250003Sadriantypedef enum cal_types { 328250003Sadrian IQ_MISMATCH_CAL = 0x1, 329250003Sadrian TEMP_COMP_CAL = 0x2, 330250003Sadrian} HAL_CAL_TYPES; 331250003Sadrian 332250003Sadriantypedef enum cal_state { 333250003Sadrian CAL_INACTIVE, 334250003Sadrian CAL_WAITING, 335250003Sadrian CAL_RUNNING, 336250003Sadrian CAL_DONE 337250003Sadrian} HAL_CAL_STATE; /* Calibrate state */ 338250003Sadrian 339250003Sadrian#define MIN_CAL_SAMPLES 1 340250003Sadrian#define MAX_CAL_SAMPLES 64 341250003Sadrian#define INIT_LOG_COUNT 5 342250003Sadrian#define PER_MIN_LOG_COUNT 2 343250003Sadrian#define PER_MAX_LOG_COUNT 10 344250003Sadrian 345250003Sadrian#define AR9300_NUM_BT_WEIGHTS 4 346250003Sadrian#define AR9300_NUM_WLAN_WEIGHTS 4 347250003Sadrian 348250003Sadrian/* Per Calibration data structure */ 349250003Sadriantypedef struct per_cal_data { 350250003Sadrian HAL_CAL_TYPES cal_type; // Type of calibration 351250003Sadrian u_int32_t cal_num_samples; // Number of SW samples to collect 352250003Sadrian u_int32_t cal_count_max; // Number of HW samples to collect 353250003Sadrian void (*cal_collect)(struct ath_hal *, u_int8_t); // Accumulator func 354250003Sadrian void (*cal_post_proc)(struct ath_hal *, u_int8_t); // Post-processing func 355250003Sadrian} HAL_PERCAL_DATA; 356250003Sadrian 357250003Sadrian/* List structure for calibration data */ 358250003Sadriantypedef struct cal_list { 359250003Sadrian const HAL_PERCAL_DATA *cal_data; 360250003Sadrian HAL_CAL_STATE cal_state; 361250003Sadrian struct cal_list *cal_next; 362250003Sadrian} HAL_CAL_LIST; 363250003Sadrian 364250003Sadrian#define AR9300_NUM_CAL_TYPES 2 365250003Sadrian#define AR9300_PAPRD_TABLE_SZ 24 366250003Sadrian#define AR9300_PAPRD_GAIN_TABLE_SZ 32 367250003Sadrian#define AR9382_MAX_GPIO_PIN_NUM (16) 368250003Sadrian#define AR9382_GPIO_PIN_8_RESERVED (8) 369250003Sadrian#define AR9382_GPIO_9_INPUT_ONLY (9) 370250003Sadrian#define AR9382_MAX_GPIO_INPUT_PIN_NUM (13) 371250003Sadrian#define AR9382_GPIO_PIN_11_RESERVED (11) 372250003Sadrian#define AR9382_MAX_JTAG_GPIO_PIN_NUM (3) 373250003Sadrian 374250003Sadrian/* Paprd tx power adjust data structure */ 375250003Sadrianstruct ar9300_paprd_pwr_adjust { 376250003Sadrian u_int32_t target_rate; // rate index 377250003Sadrian u_int32_t reg_addr; // register offset 378250003Sadrian u_int32_t reg_mask; // mask of register 379250003Sadrian u_int32_t reg_mask_offset; // mask offset of register 380250003Sadrian u_int32_t sub_db; // offset value unit of dB 381250003Sadrian}; 382250003Sadrian 383250003Sadrian#define AR9300_MAX_RATES 36 /* legacy(4) + ofdm(8) + HTSS(8) + HTDS(8) + HTTS(8)*/ 384250003Sadrianstruct ath_hal_9300 { 385250003Sadrian struct ath_hal_private_tables ah_priv; /* base class */ 386250003Sadrian 387250003Sadrian /* 388250003Sadrian * Information retrieved from EEPROM. 389250003Sadrian */ 390250003Sadrian ar9300_eeprom_t ah_eeprom; 391250003Sadrian 392250003Sadrian GAIN_VALUES ah_gain_values; 393250003Sadrian 394250003Sadrian u_int8_t ah_macaddr[IEEE80211_ADDR_LEN]; 395250003Sadrian u_int8_t ah_bssid[IEEE80211_ADDR_LEN]; 396250003Sadrian u_int8_t ah_bssid_mask[IEEE80211_ADDR_LEN]; 397250003Sadrian u_int16_t ah_assoc_id; 398250003Sadrian 399250003Sadrian /* 400250003Sadrian * Runtime state. 401250003Sadrian */ 402250003Sadrian u_int32_t ah_mask_reg; /* copy of AR_IMR */ 403250003Sadrian u_int32_t ah_mask2Reg; /* copy of AR_IMR_S2 */ 404250003Sadrian u_int32_t ah_msi_reg; /* copy of AR_PCIE_MSI */ 405250003Sadrian os_atomic_t ah_ier_ref_count; /* reference count for enabling interrupts */ 406250003Sadrian struct ar9300_stats ah_stats; /* various statistics */ 407250003Sadrian RF_HAL_FUNCS ah_rf_hal; 408250003Sadrian u_int32_t ah_tx_desc_mask; /* mask for TXDESC */ 409250003Sadrian u_int32_t ah_tx_ok_interrupt_mask; 410250003Sadrian u_int32_t ah_tx_err_interrupt_mask; 411250003Sadrian u_int32_t ah_tx_desc_interrupt_mask; 412250003Sadrian u_int32_t ah_tx_eol_interrupt_mask; 413250003Sadrian u_int32_t ah_tx_urn_interrupt_mask; 414250003Sadrian HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; 415250003Sadrian HAL_SMPS_MODE ah_sm_power_mode; 416250003Sadrian HAL_BOOL ah_chip_full_sleep; 417250003Sadrian u_int32_t ah_atim_window; 418250003Sadrian HAL_ANT_SETTING ah_diversity_control; /* antenna setting */ 419250003Sadrian u_int16_t ah_antenna_switch_swap; /* Controls mapping of OID request */ 420250003Sadrian u_int8_t ah_tx_chainmask_cfg; /* chain mask config */ 421250003Sadrian u_int8_t ah_rx_chainmask_cfg; 422250003Sadrian u_int32_t ah_beacon_rssi_threshold; /* cache beacon rssi threshold */ 423250003Sadrian /* Calibration related fields */ 424250003Sadrian HAL_CAL_TYPES ah_supp_cals; 425250003Sadrian HAL_CAL_LIST ah_iq_cal_data; /* IQ Cal Data */ 426250003Sadrian HAL_CAL_LIST ah_temp_comp_cal_data; /* Temperature Compensation Cal Data */ 427250003Sadrian HAL_CAL_LIST *ah_cal_list; /* ptr to first cal in list */ 428250003Sadrian HAL_CAL_LIST *ah_cal_list_last; /* ptr to last cal in list */ 429250003Sadrian HAL_CAL_LIST *ah_cal_list_curr; /* ptr to current cal */ 430250003Sadrian// IQ Cal aliases 431250003Sadrian#define ah_total_power_meas_i ah_meas0.unsign 432250003Sadrian#define ah_total_power_meas_q ah_meas1.unsign 433250003Sadrian#define ah_total_iq_corr_meas ah_meas2.sign 434250003Sadrian union { 435250003Sadrian u_int32_t unsign[AR9300_MAX_CHAINS]; 436250003Sadrian int32_t sign[AR9300_MAX_CHAINS]; 437250003Sadrian } ah_meas0; 438250003Sadrian union { 439250003Sadrian u_int32_t unsign[AR9300_MAX_CHAINS]; 440250003Sadrian int32_t sign[AR9300_MAX_CHAINS]; 441250003Sadrian } ah_meas1; 442250003Sadrian union { 443250003Sadrian u_int32_t unsign[AR9300_MAX_CHAINS]; 444250003Sadrian int32_t sign[AR9300_MAX_CHAINS]; 445250003Sadrian } ah_meas2; 446250003Sadrian union { 447250003Sadrian u_int32_t unsign[AR9300_MAX_CHAINS]; 448250003Sadrian int32_t sign[AR9300_MAX_CHAINS]; 449250003Sadrian } ah_meas3; 450250003Sadrian u_int16_t ah_cal_samples; 451250003Sadrian /* end - Calibration related fields */ 452250003Sadrian u_int32_t ah_tx6_power_in_half_dbm; /* power output for 6Mb tx */ 453250003Sadrian u_int32_t ah_sta_id1_defaults; /* STA_ID1 default settings */ 454250003Sadrian u_int32_t ah_misc_mode; /* MISC_MODE settings */ 455250003Sadrian HAL_BOOL ah_get_plcp_hdr; /* setting about MISC_SEL_EVM */ 456250003Sadrian enum { 457250003Sadrian AUTO_32KHZ, /* use it if 32kHz crystal present */ 458250003Sadrian USE_32KHZ, /* do it regardless */ 459250003Sadrian DONT_USE_32KHZ, /* don't use it regardless */ 460250003Sadrian } ah_enable32k_hz_clock; /* whether to sleep at 32kHz */ 461250003Sadrian 462250003Sadrian u_int32_t ah_ofdm_tx_power; 463250003Sadrian int16_t ah_tx_power_index_offset; 464250003Sadrian 465250003Sadrian u_int ah_slot_time; /* user-specified slot time */ 466250003Sadrian u_int ah_ack_timeout; /* user-specified ack timeout */ 467250003Sadrian /* 468250003Sadrian * XXX 469250003Sadrian * 11g-specific stuff; belongs in the driver. 470250003Sadrian */ 471250003Sadrian u_int8_t ah_g_beacon_rate; /* fixed rate for G beacons */ 472250003Sadrian u_int32_t ah_gpio_mask; /* copy of enabled GPIO mask */ 473250003Sadrian u_int32_t ah_gpio_cause; /* copy of GPIO cause (sync and async) */ 474250003Sadrian /* 475250003Sadrian * RF Silent handling; setup according to the EEPROM. 476250003Sadrian */ 477250003Sadrian u_int32_t ah_gpio_select; /* GPIO pin to use */ 478250003Sadrian u_int32_t ah_polarity; /* polarity to disable RF */ 479250003Sadrian u_int32_t ah_gpio_bit; /* after init, prev value */ 480250003Sadrian HAL_BOOL ah_eep_enabled; /* EEPROM bit for capability */ 481250003Sadrian 482250003Sadrian#ifdef ATH_BT_COEX 483250003Sadrian /* 484250003Sadrian * Bluetooth coexistence static setup according to the registry 485250003Sadrian */ 486250003Sadrian HAL_BT_MODULE ah_bt_module; /* Bluetooth module identifier */ 487250003Sadrian u_int8_t ah_bt_coex_config_type; /* BT coex configuration */ 488250003Sadrian u_int8_t ah_bt_active_gpio_select; /* GPIO pin for BT_ACTIVE */ 489250003Sadrian u_int8_t ah_bt_priority_gpio_select; /* GPIO pin for BT_PRIORITY */ 490250003Sadrian u_int8_t ah_wlan_active_gpio_select; /* GPIO pin for WLAN_ACTIVE */ 491250003Sadrian u_int8_t ah_bt_active_polarity; /* Polarity of BT_ACTIVE */ 492250003Sadrian HAL_BOOL ah_bt_coex_single_ant; /* Single or dual antenna configuration */ 493250003Sadrian u_int8_t ah_bt_wlan_isolation; /* Isolation between BT and WLAN in dB */ 494250003Sadrian /* 495250003Sadrian * Bluetooth coexistence runtime settings 496250003Sadrian */ 497250003Sadrian HAL_BOOL ah_bt_coex_enabled; /* If Bluetooth coexistence is enabled */ 498250003Sadrian u_int32_t ah_bt_coex_mode; /* Register setting for AR_BT_COEX_MODE */ 499250003Sadrian u_int32_t ah_bt_coex_bt_weight[AR9300_NUM_BT_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 500250003Sadrian u_int32_t ah_bt_coex_wlan_weight[AR9300_NUM_WLAN_WEIGHTS]; /* Register setting for AR_BT_COEX_WEIGHT */ 501250003Sadrian u_int32_t ah_bt_coex_mode2; /* Register setting for AR_BT_COEX_MODE2 */ 502250003Sadrian u_int32_t ah_bt_coex_flag; /* Special tuning flags for BT coex */ 503250003Sadrian#endif 504250003Sadrian 505250003Sadrian /* 506250003Sadrian * Generic timer support 507250003Sadrian */ 508250003Sadrian u_int32_t ah_avail_gen_timers; /* mask of available timers */ 509250003Sadrian u_int32_t ah_intr_gen_timer_trigger; /* generic timer trigger interrupt state */ 510250003Sadrian u_int32_t ah_intr_gen_timer_thresh; /* generic timer trigger interrupt state */ 511250003Sadrian HAL_BOOL ah_enable_tsf2; /* enable TSF2 for gen timer 8-15. */ 512250003Sadrian 513250003Sadrian /* 514250003Sadrian * ANI & Radar support. 515250003Sadrian */ 516250003Sadrian u_int32_t ah_proc_phy_err; /* Process Phy errs */ 517250003Sadrian u_int32_t ah_ani_period; /* ani update list period */ 518250003Sadrian struct ar9300_ani_state *ah_curani; /* cached last reference */ 519250003Sadrian struct ar9300_ani_state ah_ani[255]; /* per-channel state */ 520250003Sadrian struct ar9300_radar_state ah_radar[HAL_NUMRADAR_STATES]; /* Per-Channel Radar detector state */ 521250003Sadrian struct ar9300_radar_q_elem *ah_radarq; /* radar event queue */ 522250003Sadrian struct ar9300_radar_q_info ah_radarq_info; /* radar event q read/write state */ 523250003Sadrian struct ar9300_ar_state ah_ar; /* AR detector state */ 524250003Sadrian struct ar9300_radar_q_elem *ah_arq; /* AR event queue */ 525250003Sadrian struct ar9300_radar_q_info ah_arq_info; /* AR event q read/write state */ 526250003Sadrian 527250003Sadrian /* 528250003Sadrian * Transmit power state. Note these are maintained 529250003Sadrian * here so they can be retrieved by diagnostic tools. 530250003Sadrian */ 531250003Sadrian u_int16_t ah_rates_array[16]; 532250003Sadrian 533250003Sadrian /* 534250003Sadrian * Tx queue interrupt state. 535250003Sadrian */ 536250003Sadrian u_int32_t ah_intr_txqs; 537250003Sadrian 538250003Sadrian HAL_BOOL ah_intr_mitigation_rx; /* rx Interrupt Mitigation Settings */ 539250003Sadrian HAL_BOOL ah_intr_mitigation_tx; /* tx Interrupt Mitigation Settings */ 540250003Sadrian 541250003Sadrian /* 542250003Sadrian * Extension Channel Rx Clear State 543250003Sadrian */ 544250003Sadrian u_int32_t ah_cycle_count; 545250003Sadrian u_int32_t ah_ctl_busy; 546250003Sadrian u_int32_t ah_ext_busy; 547250003Sadrian 548250003Sadrian /* HT CWM state */ 549250003Sadrian HAL_HT_EXTPROTSPACING ah_ext_prot_spacing; 550250003Sadrian u_int8_t ah_tx_chainmask; /* tx chain mask */ 551250003Sadrian u_int8_t ah_rx_chainmask; /* rx chain mask */ 552250003Sadrian 553250003Sadrian u_int8_t ah_tx_cal_chainmask; /* tx cal chain mask */ 554250003Sadrian u_int8_t ah_rx_cal_chainmask; /* rx cal chain mask */ 555250003Sadrian 556250003Sadrian int ah_hwp; 557250003Sadrian void *ah_cal_mem; 558250003Sadrian HAL_BOOL ah_emu_eeprom; 559250003Sadrian 560250003Sadrian HAL_ANI_CMD ah_ani_function; 561250003Sadrian HAL_BOOL ah_rifs_enabled; 562250003Sadrian u_int32_t ah_rifs_reg[11]; 563250003Sadrian u_int32_t ah_rifs_sec_cnt; 564250003Sadrian 565250003Sadrian /* open-loop power control */ 566250003Sadrian u_int32_t original_gain[22]; 567250003Sadrian int32_t init_pdadc; 568250003Sadrian int32_t pdadc_delta; 569250003Sadrian 570250003Sadrian /* cycle counts for beacon stuck diagnostics */ 571250003Sadrian u_int32_t ah_cycles; 572250003Sadrian u_int32_t ah_rx_clear; 573250003Sadrian u_int32_t ah_rx_frame; 574250003Sadrian u_int32_t ah_tx_frame; 575250003Sadrian 576250003Sadrian#define BB_HANG_SIG1 0 577250003Sadrian#define BB_HANG_SIG2 1 578250003Sadrian#define BB_HANG_SIG3 2 579250003Sadrian#define BB_HANG_SIG4 3 580250003Sadrian#define MAC_HANG_SIG1 4 581250003Sadrian#define MAC_HANG_SIG2 5 582250003Sadrian /* bb hang detection */ 583250003Sadrian int ah_hang[6]; 584250003Sadrian hal_hw_hangs_t ah_hang_wars; 585250003Sadrian /* 586250003Sadrian * Support for ar9300 multiple INIs 587250003Sadrian */ 588250003Sadrian struct ar9300_ini_array ah_ini_pcie_serdes; 589250003Sadrian struct ar9300_ini_array ah_ini_pcie_serdes_low_power; 590250003Sadrian struct ar9300_ini_array ah_ini_modes_additional; 591250003Sadrian struct ar9300_ini_array ah_ini_modes_additional_40mhz; 592250003Sadrian struct ar9300_ini_array ah_ini_modes_rxgain; 593250003Sadrian struct ar9300_ini_array ah_ini_modes_rxgain_bounds; 594250003Sadrian struct ar9300_ini_array ah_ini_modes_txgain; 595250003Sadrian struct ar9300_ini_array ah_ini_japan2484; 596250003Sadrian struct ar9300_ini_array ah_ini_radio_post_sys2ant; 597250003Sadrian struct ar9300_ini_array ah_ini_BTCOEX_MAX_TXPWR; 598250003Sadrian /* 599250003Sadrian * New INI format starting with Osprey 2.0 INI. 600250003Sadrian * Pre, core, post arrays for each sub-system (mac, bb, radio, soc) 601250003Sadrian */ 602250003Sadrian #define ATH_INI_PRE 0 603250003Sadrian #define ATH_INI_CORE 1 604250003Sadrian #define ATH_INI_POST 2 605250003Sadrian #define ATH_INI_NUM_SPLIT (ATH_INI_POST + 1) 606250003Sadrian struct ar9300_ini_array ah_ini_mac[ATH_INI_NUM_SPLIT]; /* New INI format */ 607250003Sadrian struct ar9300_ini_array ah_ini_bb[ATH_INI_NUM_SPLIT]; /* New INI format */ 608250003Sadrian struct ar9300_ini_array ah_ini_radio[ATH_INI_NUM_SPLIT]; /* New INI format */ 609250003Sadrian struct ar9300_ini_array ah_ini_soc[ATH_INI_NUM_SPLIT]; /* New INI format */ 610250003Sadrian 611250003Sadrian /* 612250003Sadrian * Added to support DFS postamble array in INI that we need to apply 613250003Sadrian * in DFS channels 614250003Sadrian */ 615250003Sadrian 616250003Sadrian struct ar9300_ini_array ah_ini_dfs; 617250003Sadrian 618250003Sadrian#if ATH_WOW 619250003Sadrian struct ar9300_ini_array ah_ini_pcie_serdes_wow; /* SerDes values during WOW sleep */ 620250003Sadrian#endif 621250003Sadrian 622250003Sadrian /* To indicate EEPROM mapping used */ 623250003Sadrian u_int32_t ah_immunity_vals[6]; 624250003Sadrian HAL_BOOL ah_immunity_on; 625250003Sadrian /* 626250003Sadrian * snap shot of counter register for debug purposes 627250003Sadrian */ 628250003Sadrian#ifdef AH_DEBUG 629250003Sadrian u_int32_t last_tf; 630250003Sadrian u_int32_t last_rf; 631250003Sadrian u_int32_t last_rc; 632250003Sadrian u_int32_t last_cc; 633250003Sadrian#endif 634250003Sadrian HAL_BOOL ah_dma_stuck; /* Set to AH_TRUE when RX/TX DMA failed to stop. */ 635250003Sadrian u_int32_t nf_tsf32; /* timestamp for NF calibration duration */ 636250003Sadrian 637250003Sadrian u_int32_t reg_dmn; /* Regulatory Domain */ 638250003Sadrian int16_t twice_antenna_gain; /* Antenna Gain */ 639250003Sadrian u_int16_t twice_antenna_reduction; /* Antenna Gain Allowed */ 640250003Sadrian 641250003Sadrian /* 642250003Sadrian * Upper limit after factoring in the regulatory max, antenna gain and 643250003Sadrian * multichain factor. No TxBF, CDD or STBC gain factored 644250003Sadrian */ 645250003Sadrian int16_t upper_limit[AR9300_MAX_CHAINS]; 646250003Sadrian 647250003Sadrian /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains */ 648250003Sadrian int16_t txpower[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 649250003Sadrian 650250003Sadrian 651250003Sadrian /* adjusted power for descriptor-based TPC for 1, 2, or 3 chains with STBC*/ 652250003Sadrian int16_t txpower_stbc[AR9300_MAX_RATES][AR9300_MAX_CHAINS]; 653250003Sadrian 654250003Sadrian /* Transmit Status ring support */ 655250003Sadrian struct ar9300_txs *ts_ring; 656250003Sadrian u_int16_t ts_tail; 657250003Sadrian u_int16_t ts_size; 658250003Sadrian u_int32_t ts_paddr_start; 659250003Sadrian u_int32_t ts_paddr_end; 660250003Sadrian 661250003Sadrian /* Receive Buffer size */ 662250003Sadrian#define HAL_RXBUFSIZE_DEFAULT 0xfff 663250003Sadrian u_int16_t rx_buf_size; 664250003Sadrian 665250003Sadrian u_int32_t ah_wa_reg_val; // Store the permanent value of Reg 0x4004 so we dont have to R/M/W. (We should not be reading this register when in sleep states). 666250003Sadrian 667250003Sadrian /* Indicate the PLL source clock rate is 25Mhz or not. 668250003Sadrian * clk_25mhz = 0 by default. 669250003Sadrian */ 670250003Sadrian u_int8_t clk_25mhz; 671250003Sadrian /* For PAPRD uses */ 672250003Sadrian u_int16_t small_signal_gain[AH_MAX_CHAINS]; 673250003Sadrian u_int32_t pa_table[AH_MAX_CHAINS][AR9300_PAPRD_TABLE_SZ]; 674250003Sadrian u_int32_t paprd_gain_table_entries[AR9300_PAPRD_GAIN_TABLE_SZ]; 675250003Sadrian u_int32_t paprd_gain_table_index[AR9300_PAPRD_GAIN_TABLE_SZ]; 676250003Sadrian u_int32_t ah_2g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht20 */ 677250003Sadrian u_int32_t ah_2g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_2g.paprd_rate_mask_ht40 */ 678250003Sadrian u_int32_t ah_5g_paprd_rate_mask_ht20; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht20 */ 679250003Sadrian u_int32_t ah_5g_paprd_rate_mask_ht40; /* Copy of eep->modal_header_5g.paprd_rate_mask_ht40 */ 680250003Sadrian u_int32_t paprd_training_power; 681250003Sadrian /* For GreenTx use to store the default tx power */ 682250003Sadrian u_int8_t ah_default_tx_power[ar9300_rate_size]; 683250003Sadrian HAL_BOOL ah_paprd_broken; 684250003Sadrian 685250003Sadrian /* To store offsets of host interface registers */ 686250003Sadrian struct { 687250003Sadrian u_int32_t AR_RC; 688250003Sadrian u_int32_t AR_WA; 689250003Sadrian u_int32_t AR_PM_STATE; 690250003Sadrian u_int32_t AR_H_INFOL; 691250003Sadrian u_int32_t AR_H_INFOH; 692250003Sadrian u_int32_t AR_PCIE_PM_CTRL; 693250003Sadrian u_int32_t AR_HOST_TIMEOUT; 694250003Sadrian u_int32_t AR_EEPROM; 695250003Sadrian u_int32_t AR_SREV; 696250003Sadrian u_int32_t AR_INTR_SYNC_CAUSE; 697250003Sadrian u_int32_t AR_INTR_SYNC_CAUSE_CLR; 698250003Sadrian u_int32_t AR_INTR_SYNC_ENABLE; 699250003Sadrian u_int32_t AR_INTR_ASYNC_MASK; 700250003Sadrian u_int32_t AR_INTR_SYNC_MASK; 701250003Sadrian u_int32_t AR_INTR_ASYNC_CAUSE_CLR; 702250003Sadrian u_int32_t AR_INTR_ASYNC_CAUSE; 703250003Sadrian u_int32_t AR_INTR_ASYNC_ENABLE; 704250003Sadrian u_int32_t AR_PCIE_SERDES; 705250003Sadrian u_int32_t AR_PCIE_SERDES2; 706250003Sadrian u_int32_t AR_GPIO_OUT; 707250003Sadrian u_int32_t AR_GPIO_IN; 708250003Sadrian u_int32_t AR_GPIO_OE_OUT; 709250003Sadrian u_int32_t AR_GPIO_OE1_OUT; 710250003Sadrian u_int32_t AR_GPIO_INTR_POL; 711250003Sadrian u_int32_t AR_GPIO_INPUT_EN_VAL; 712250003Sadrian u_int32_t AR_GPIO_INPUT_MUX1; 713250003Sadrian u_int32_t AR_GPIO_INPUT_MUX2; 714250003Sadrian u_int32_t AR_GPIO_OUTPUT_MUX1; 715250003Sadrian u_int32_t AR_GPIO_OUTPUT_MUX2; 716250003Sadrian u_int32_t AR_GPIO_OUTPUT_MUX3; 717250003Sadrian u_int32_t AR_INPUT_STATE; 718250003Sadrian u_int32_t AR_SPARE; 719250003Sadrian u_int32_t AR_PCIE_CORE_RESET_EN; 720250003Sadrian u_int32_t AR_CLKRUN; 721250003Sadrian u_int32_t AR_EEPROM_STATUS_DATA; 722250003Sadrian u_int32_t AR_OBS; 723250003Sadrian u_int32_t AR_RFSILENT; 724250003Sadrian u_int32_t AR_GPIO_PDPU; 725250003Sadrian u_int32_t AR_GPIO_DS; 726250003Sadrian u_int32_t AR_MISC; 727250003Sadrian u_int32_t AR_PCIE_MSI; 728250003Sadrian u_int32_t AR_TSF_SNAPSHOT_BT_ACTIVE; 729250003Sadrian u_int32_t AR_TSF_SNAPSHOT_BT_PRIORITY; 730250003Sadrian u_int32_t AR_TSF_SNAPSHOT_BT_CNTL; 731250003Sadrian u_int32_t AR_PCIE_PHY_LATENCY_NFTS_ADJ; 732250003Sadrian u_int32_t AR_TDMA_CCA_CNTL; 733250003Sadrian u_int32_t AR_TXAPSYNC; 734250003Sadrian u_int32_t AR_TXSYNC_INIT_SYNC_TMR; 735250003Sadrian u_int32_t AR_INTR_PRIO_SYNC_CAUSE; 736250003Sadrian u_int32_t AR_INTR_PRIO_SYNC_ENABLE; 737250003Sadrian u_int32_t AR_INTR_PRIO_ASYNC_MASK; 738250003Sadrian u_int32_t AR_INTR_PRIO_SYNC_MASK; 739250003Sadrian u_int32_t AR_INTR_PRIO_ASYNC_CAUSE; 740250003Sadrian u_int32_t AR_INTR_PRIO_ASYNC_ENABLE; 741250003Sadrian } ah_hostifregs; 742250003Sadrian 743250003Sadrian u_int32_t ah_enterprise_mode; 744250003Sadrian u_int32_t ah_radar1; 745250003Sadrian u_int32_t ah_dc_offset; 746250003Sadrian HAL_BOOL ah_hw_green_tx_enable; /* 1:enalbe H/W Green Tx */ 747250003Sadrian HAL_BOOL ah_smartantenna_enable; /* 1:enalbe H/W */ 748250003Sadrian u_int32_t ah_disable_cck; 749250003Sadrian HAL_BOOL ah_lna_div_use_bt_ant_enable; /* 1:enable Rx(LNA) Diversity */ 750250003Sadrian 751250003Sadrian 752250003Sadrian /* 753250003Sadrian * Different types of memory where the calibration data might be stored. 754250003Sadrian * All types are searched in Ar9300EepromRestore() in the order flash, eeprom, otp. 755250003Sadrian * To disable searching a type, set its parameter to 0. 756250003Sadrian */ 757250003Sadrian int try_dram; 758250003Sadrian int try_flash; 759250003Sadrian int try_eeprom; 760250003Sadrian int try_otp; 761250003Sadrian#ifdef ATH_CAL_NAND_FLASH 762250003Sadrian int try_nand; 763250003Sadrian#endif 764250003Sadrian /* 765250003Sadrian * This is where we found the calibration data. 766250003Sadrian */ 767250003Sadrian int calibration_data_source; 768250003Sadrian int calibration_data_source_address; 769250003Sadrian /* 770250003Sadrian * This is where we look for the calibration data. must be set before ath_attach() is called 771250003Sadrian */ 772250003Sadrian int calibration_data_try; 773250003Sadrian int calibration_data_try_address; 774250003Sadrian u_int8_t 775250003Sadrian tx_iq_cal_enable : 1, 776250003Sadrian tx_iq_cal_during_agc_cal : 1, 777250003Sadrian tx_cl_cal_enable : 1; 778250003Sadrian 779250003Sadrian#if ATH_SUPPORT_MCI 780250003Sadrian /* For MCI */ 781250003Sadrian HAL_BOOL ah_mci_ready; 782250003Sadrian u_int32_t ah_mci_int_raw; 783250003Sadrian u_int32_t ah_mci_int_rx_msg; 784250003Sadrian u_int32_t ah_mci_rx_status; 785250003Sadrian u_int32_t ah_mci_cont_status; 786250003Sadrian u_int8_t ah_mci_bt_state; 787250003Sadrian u_int32_t ah_mci_gpm_addr; 788250003Sadrian u_int8_t *ah_mci_gpm_buf; 789250003Sadrian u_int32_t ah_mci_gpm_len; 790250003Sadrian u_int32_t ah_mci_gpm_idx; 791250003Sadrian u_int32_t ah_mci_sched_addr; 792250003Sadrian u_int8_t *ah_mci_sched_buf; 793250003Sadrian u_int8_t ah_mci_coex_major_version_wlan; 794250003Sadrian u_int8_t ah_mci_coex_minor_version_wlan; 795250003Sadrian u_int8_t ah_mci_coex_major_version_bt; 796250003Sadrian u_int8_t ah_mci_coex_minor_version_bt; 797250003Sadrian HAL_BOOL ah_mci_coex_bt_version_known; 798250003Sadrian HAL_BOOL ah_mci_coex_wlan_channels_update; 799250003Sadrian u_int32_t ah_mci_coex_wlan_channels[4]; 800250003Sadrian HAL_BOOL ah_mci_coex_2g5g_update; 801250003Sadrian HAL_BOOL ah_mci_coex_is_2g; 802250003Sadrian HAL_BOOL ah_mci_query_bt; 803250003Sadrian HAL_BOOL ah_mci_unhalt_bt_gpm; /* need send UNHALT */ 804250003Sadrian HAL_BOOL ah_mci_halted_bt_gpm; /* HALT sent */ 805250003Sadrian HAL_BOOL ah_mci_need_flush_btinfo; 806250003Sadrian HAL_BOOL ah_mci_concur_tx_en; 807250003Sadrian u_int8_t ah_mci_stomp_low_tx_pri; 808250003Sadrian u_int8_t ah_mci_stomp_all_tx_pri; 809250003Sadrian u_int8_t ah_mci_stomp_none_tx_pri; 810250003Sadrian u_int32_t ah_mci_wlan_cal_seq; 811250003Sadrian u_int32_t ah_mci_wlan_cal_done; 812250003Sadrian#if ATH_SUPPORT_AIC 813250003Sadrian HAL_BOOL ah_aic_enabled; 814250003Sadrian u_int32_t ah_aic_sram[ATH_AIC_MAX_BT_CHANNEL]; 815250003Sadrian#endif 816250003Sadrian#endif /* ATH_SUPPORT_MCI */ 817250003Sadrian u_int8_t ah_cac_quiet_enabled; 818250003Sadrian#if ATH_WOW_OFFLOAD 819250003Sadrian u_int32_t ah_mcast_filter_l32_set; 820250003Sadrian u_int32_t ah_mcast_filter_u32_set; 821250003Sadrian#endif 822250003Sadrian HAL_BOOL ah_reduced_self_gen_mask; 823250003Sadrian}; 824250003Sadrian 825250003Sadrian#define AH9300(_ah) ((struct ath_hal_9300 *)(_ah)) 826250003Sadrian 827250003Sadrian#define IS_9300_EMU(ah) \ 828250003Sadrian (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_EMU_PCIE) 829250003Sadrian 830250003Sadrian#define ar9300_eep_data_in_flash(_ah) \ 831250003Sadrian (!(AH_PRIVATE(_ah)->ah_flags & AH_USE_EEPROM)) 832250003Sadrian 833250003Sadrian#define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \ 834250003Sadrian (IS_CHAN_5GHZ(_c) && \ 835250003Sadrian ((AH_PRIVATE(_ah))->ah_config.ath_hal_fastClockEnable)) 836250003Sadrian 837250003Sadrian#if notyet 838250003Sadrian// Need these additional conditions for IS_5GHZ_FAST_CLOCK_EN when we have valid eeprom contents. 839250003Sadrian&& \ 840250003Sadrian ((ar9300_eeprom_get(AH9300(_ah), EEP_MINOR_REV) <= AR9300_EEP_MINOR_VER_16) || \ 841250003Sadrian (ar9300_eeprom_get(AH9300(_ah), EEP_FSTCLK_5G)))) 842250003Sadrian#endif 843250003Sadrian 844250003Sadrian/* 845250003Sadrian * WAR for bug 6773. OS_DELAY() does a PIO READ on the PCI bus which allows 846250003Sadrian * other cards' DMA reads to complete in the middle of our reset. 847250003Sadrian */ 848250003Sadrian#define WAR_6773(x) do { \ 849250003Sadrian if ((++(x) % 64) == 0) \ 850250003Sadrian OS_DELAY(1); \ 851250003Sadrian} while (0) 852250003Sadrian 853250003Sadrian#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 854250003Sadrian int r; \ 855250003Sadrian for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 856250003Sadrian OS_REG_WRITE(ah, INI_RA((iniarray), (r), 0), INI_RA((iniarray), r, (column)));\ 857250003Sadrian WAR_6773(regWr); \ 858250003Sadrian } \ 859250003Sadrian} while (0) 860250003Sadrian 861250003Sadrian#define UPPER_5G_SUB_BANDSTART 5700 862250003Sadrian#define MID_5G_SUB_BANDSTART 5400 863250003Sadrian#define TRAINPOWER_DB_OFFSET 6 864250003Sadrian 865250003Sadrian#define AH_PAPRD_GET_SCALE_FACTOR(_scale, _eep, _is2G, _channel) do{ if(_is2G) { _scale = (_eep->modal_header_2g.paprd_rate_mask_ht20>>25)&0x7; \ 866250003Sadrian } else { \ 867250003Sadrian if(_channel >= UPPER_5G_SUB_BANDSTART){ _scale = (_eep->modal_header_5g.paprd_rate_mask_ht20>>25)&0x7;} \ 868250003Sadrian else if((UPPER_5G_SUB_BANDSTART < _channel) && (_channel >= MID_5G_SUB_BANDSTART)) \ 869250003Sadrian { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>28)&0x7;} \ 870250003Sadrian else { _scale = (_eep->modal_header_5g.paprd_rate_mask_ht40>>25)&0x7;} } }while(0) 871250003Sadrian 872250003Sadrian#ifdef AH_ASSERT 873250003Sadrian #define ar9300FeatureNotSupported(feature, ah, func) \ 874250003Sadrian ath_hal_printf(ah, # feature \ 875250003Sadrian " not supported but called from %s\n", (func)), \ 876250003Sadrian hal_assert(0) 877250003Sadrian#else 878250003Sadrian #define ar9300FeatureNotSupported(feature, ah, func) \ 879250003Sadrian ath_hal_printf(ah, # feature \ 880250003Sadrian " not supported but called from %s\n", (func)) 881250003Sadrian#endif /* AH_ASSERT */ 882250003Sadrian 883250003Sadrianextern void ar9300_detach(struct ath_hal *ah); 884250003Sadrianextern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); 885250003Sadrian 886250003Sadrian/* 887250003Sadrian * Green Tx, Based on different RSSI of Received Beacon thresholds, 888250003Sadrian * using different tx power by modified register tx power related values. 889250003Sadrian * The thresholds are decided by system team. 890250003Sadrian */ 891250003Sadrian#define WB225_SW_GREEN_TX_THRES1_DB 56 /* in dB */ 892250003Sadrian#define WB225_SW_GREEN_TX_THRES2_DB 41 /* in dB */ 893250003Sadrian#define WB225_OB_CALIBRATION_VALUE 5 /* For Green Tx OLPC Delta 894250003Sadrian Calibration Offset */ 895250003Sadrian#define WB225_OB_GREEN_TX_SHORT_VALUE 1 /* For Green Tx OB value 896250003Sadrian in short distance*/ 897250003Sadrian#define WB225_OB_GREEN_TX_MIDDLE_VALUE 3 /* For Green Tx OB value 898250003Sadrian in middle distance */ 899250003Sadrian#define WB225_OB_GREEN_TX_LONG_VALUE 5 /* For Green Tx OB value 900250003Sadrian in long distance */ 901250003Sadrian#define WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE 0x06060606 /* For SwGreen Tx 902250003Sadrian BB_powertx_rate9 reg 903250003Sadrian value in short 904250003Sadrian distance */ 905250003Sadrian#define WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE 0x0E0E0E0E /* For SwGreen Tx 906250003Sadrian BB_powertx_rate9 reg 907250003Sadrian value in middle 908250003Sadrian distance */ 909250003Sadrian 910250003Sadrian 911250003Sadrian/* Tx power for short distacnce in SwGreenTx.*/ 912250003Sadrianstatic const u_int8_t wb225_sw_gtx_tp_distance_short[ar9300_rate_size] = { 913250003Sadrian 6, /*ALL_TARGET_LEGACY_6_24*/ 914250003Sadrian 6, /*ALL_TARGET_LEGACY_36*/ 915250003Sadrian 6, /*ALL_TARGET_LEGACY_48*/ 916250003Sadrian 4, /*ALL_TARGET_LEGACY_54*/ 917250003Sadrian 6, /*ALL_TARGET_LEGACY_1L_5L*/ 918250003Sadrian 6, /*ALL_TARGET_LEGACY_5S*/ 919250003Sadrian 6, /*ALL_TARGET_LEGACY_11L*/ 920250003Sadrian 6, /*ALL_TARGET_LEGACY_11S*/ 921250003Sadrian 6, /*ALL_TARGET_HT20_0_8_16*/ 922250003Sadrian 6, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 923250003Sadrian 4, /*ALL_TARGET_HT20_4*/ 924250003Sadrian 4, /*ALL_TARGET_HT20_5*/ 925250003Sadrian 4, /*ALL_TARGET_HT20_6*/ 926250003Sadrian 2, /*ALL_TARGET_HT20_7*/ 927250003Sadrian 0, /*ALL_TARGET_HT20_12*/ 928250003Sadrian 0, /*ALL_TARGET_HT20_13*/ 929250003Sadrian 0, /*ALL_TARGET_HT20_14*/ 930250003Sadrian 0, /*ALL_TARGET_HT20_15*/ 931250003Sadrian 0, /*ALL_TARGET_HT20_20*/ 932250003Sadrian 0, /*ALL_TARGET_HT20_21*/ 933250003Sadrian 0, /*ALL_TARGET_HT20_22*/ 934250003Sadrian 0, /*ALL_TARGET_HT20_23*/ 935250003Sadrian 6, /*ALL_TARGET_HT40_0_8_16*/ 936250003Sadrian 6, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 937250003Sadrian 4, /*ALL_TARGET_HT40_4*/ 938250003Sadrian 4, /*ALL_TARGET_HT40_5*/ 939250003Sadrian 4, /*ALL_TARGET_HT40_6*/ 940250003Sadrian 2, /*ALL_TARGET_HT40_7*/ 941250003Sadrian 0, /*ALL_TARGET_HT40_12*/ 942250003Sadrian 0, /*ALL_TARGET_HT40_13*/ 943250003Sadrian 0, /*ALL_TARGET_HT40_14*/ 944250003Sadrian 0, /*ALL_TARGET_HT40_15*/ 945250003Sadrian 0, /*ALL_TARGET_HT40_20*/ 946250003Sadrian 0, /*ALL_TARGET_HT40_21*/ 947250003Sadrian 0, /*ALL_TARGET_HT40_22*/ 948250003Sadrian 0 /*ALL_TARGET_HT40_23*/ 949250003Sadrian}; 950250003Sadrian 951250003Sadrian/* Tx power for middle distacnce in SwGreenTx.*/ 952250003Sadrianstatic const u_int8_t wb225_sw_gtx_tp_distance_middle[ar9300_rate_size] = { 953250003Sadrian 14, /*ALL_TARGET_LEGACY_6_24*/ 954250003Sadrian 14, /*ALL_TARGET_LEGACY_36*/ 955250003Sadrian 14, /*ALL_TARGET_LEGACY_48*/ 956250003Sadrian 12, /*ALL_TARGET_LEGACY_54*/ 957250003Sadrian 14, /*ALL_TARGET_LEGACY_1L_5L*/ 958250003Sadrian 14, /*ALL_TARGET_LEGACY_5S*/ 959250003Sadrian 14, /*ALL_TARGET_LEGACY_11L*/ 960250003Sadrian 14, /*ALL_TARGET_LEGACY_11S*/ 961250003Sadrian 14, /*ALL_TARGET_HT20_0_8_16*/ 962250003Sadrian 14, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 963250003Sadrian 14, /*ALL_TARGET_HT20_4*/ 964250003Sadrian 14, /*ALL_TARGET_HT20_5*/ 965250003Sadrian 12, /*ALL_TARGET_HT20_6*/ 966250003Sadrian 10, /*ALL_TARGET_HT20_7*/ 967250003Sadrian 0, /*ALL_TARGET_HT20_12*/ 968250003Sadrian 0, /*ALL_TARGET_HT20_13*/ 969250003Sadrian 0, /*ALL_TARGET_HT20_14*/ 970250003Sadrian 0, /*ALL_TARGET_HT20_15*/ 971250003Sadrian 0, /*ALL_TARGET_HT20_20*/ 972250003Sadrian 0, /*ALL_TARGET_HT20_21*/ 973250003Sadrian 0, /*ALL_TARGET_HT20_22*/ 974250003Sadrian 0, /*ALL_TARGET_HT20_23*/ 975250003Sadrian 14, /*ALL_TARGET_HT40_0_8_16*/ 976250003Sadrian 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 977250003Sadrian 14, /*ALL_TARGET_HT40_4*/ 978250003Sadrian 14, /*ALL_TARGET_HT40_5*/ 979250003Sadrian 12, /*ALL_TARGET_HT40_6*/ 980250003Sadrian 10, /*ALL_TARGET_HT40_7*/ 981250003Sadrian 0, /*ALL_TARGET_HT40_12*/ 982250003Sadrian 0, /*ALL_TARGET_HT40_13*/ 983250003Sadrian 0, /*ALL_TARGET_HT40_14*/ 984250003Sadrian 0, /*ALL_TARGET_HT40_15*/ 985250003Sadrian 0, /*ALL_TARGET_HT40_20*/ 986250003Sadrian 0, /*ALL_TARGET_HT40_21*/ 987250003Sadrian 0, /*ALL_TARGET_HT40_22*/ 988250003Sadrian 0 /*ALL_TARGET_HT40_23*/ 989250003Sadrian}; 990250003Sadrian 991250003Sadrian/* OLPC DeltaCalibration Offset unit in half dB.*/ 992250003Sadrianstatic const u_int8_t wb225_gtx_olpc_cal_offset[6] = { 993250003Sadrian 0, /* OB0*/ 994250003Sadrian 16, /* OB1*/ 995250003Sadrian 9, /* OB2*/ 996250003Sadrian 5, /* OB3*/ 997250003Sadrian 2, /* OB4*/ 998250003Sadrian 0, /* OB5*/ 999250003Sadrian}; 1000250003Sadrian 1001250003Sadrian/* 1002250003Sadrian * Definitions for HwGreenTx 1003250003Sadrian */ 1004250003Sadrian#define AR9485_HW_GREEN_TX_THRES1_DB 56 /* in dB */ 1005250003Sadrian#define AR9485_HW_GREEN_TX_THRES2_DB 41 /* in dB */ 1006250003Sadrian#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE 0x0C0C0A0A /* For HwGreen Tx 1007250003Sadrian BB_powertx_rate9 reg 1008250003Sadrian value in short 1009250003Sadrian distance */ 1010250003Sadrian#define AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE 0x10100E0E /* For HwGreenTx 1011250003Sadrian BB_powertx_rate9 reg 1012250003Sadrian value in middle 1013250003Sadrian distance */ 1014250003Sadrian 1015250003Sadrian/* Tx power for short distacnce in HwGreenTx.*/ 1016250003Sadrianstatic const u_int8_t ar9485_hw_gtx_tp_distance_short[ar9300_rate_size] = { 1017250003Sadrian 14, /*ALL_TARGET_LEGACY_6_24*/ 1018250003Sadrian 14, /*ALL_TARGET_LEGACY_36*/ 1019250003Sadrian 8, /*ALL_TARGET_LEGACY_48*/ 1020250003Sadrian 2, /*ALL_TARGET_LEGACY_54*/ 1021250003Sadrian 14, /*ALL_TARGET_LEGACY_1L_5L*/ 1022250003Sadrian 14, /*ALL_TARGET_LEGACY_5S*/ 1023250003Sadrian 14, /*ALL_TARGET_LEGACY_11L*/ 1024250003Sadrian 14, /*ALL_TARGET_LEGACY_11S*/ 1025250003Sadrian 12, /*ALL_TARGET_HT20_0_8_16*/ 1026250003Sadrian 12, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1027250003Sadrian 12, /*ALL_TARGET_HT20_4*/ 1028250003Sadrian 12, /*ALL_TARGET_HT20_5*/ 1029250003Sadrian 8, /*ALL_TARGET_HT20_6*/ 1030250003Sadrian 2, /*ALL_TARGET_HT20_7*/ 1031250003Sadrian 0, /*ALL_TARGET_HT20_12*/ 1032250003Sadrian 0, /*ALL_TARGET_HT20_13*/ 1033250003Sadrian 0, /*ALL_TARGET_HT20_14*/ 1034250003Sadrian 0, /*ALL_TARGET_HT20_15*/ 1035250003Sadrian 0, /*ALL_TARGET_HT20_20*/ 1036250003Sadrian 0, /*ALL_TARGET_HT20_21*/ 1037250003Sadrian 0, /*ALL_TARGET_HT20_22*/ 1038250003Sadrian 0, /*ALL_TARGET_HT20_23*/ 1039250003Sadrian 10, /*ALL_TARGET_HT40_0_8_16*/ 1040250003Sadrian 10, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1041250003Sadrian 10, /*ALL_TARGET_HT40_4*/ 1042250003Sadrian 10, /*ALL_TARGET_HT40_5*/ 1043250003Sadrian 6, /*ALL_TARGET_HT40_6*/ 1044250003Sadrian 2, /*ALL_TARGET_HT40_7*/ 1045250003Sadrian 0, /*ALL_TARGET_HT40_12*/ 1046250003Sadrian 0, /*ALL_TARGET_HT40_13*/ 1047250003Sadrian 0, /*ALL_TARGET_HT40_14*/ 1048250003Sadrian 0, /*ALL_TARGET_HT40_15*/ 1049250003Sadrian 0, /*ALL_TARGET_HT40_20*/ 1050250003Sadrian 0, /*ALL_TARGET_HT40_21*/ 1051250003Sadrian 0, /*ALL_TARGET_HT40_22*/ 1052250003Sadrian 0 /*ALL_TARGET_HT40_23*/ 1053250003Sadrian}; 1054250003Sadrian 1055250003Sadrian/* Tx power for middle distacnce in HwGreenTx.*/ 1056250003Sadrianstatic const u_int8_t ar9485_hw_gtx_tp_distance_middle[ar9300_rate_size] = { 1057250003Sadrian 18, /*ALL_TARGET_LEGACY_6_24*/ 1058250003Sadrian 18, /*ALL_TARGET_LEGACY_36*/ 1059250003Sadrian 14, /*ALL_TARGET_LEGACY_48*/ 1060250003Sadrian 12, /*ALL_TARGET_LEGACY_54*/ 1061250003Sadrian 18, /*ALL_TARGET_LEGACY_1L_5L*/ 1062250003Sadrian 18, /*ALL_TARGET_LEGACY_5S*/ 1063250003Sadrian 18, /*ALL_TARGET_LEGACY_11L*/ 1064250003Sadrian 18, /*ALL_TARGET_LEGACY_11S*/ 1065250003Sadrian 16, /*ALL_TARGET_HT20_0_8_16*/ 1066250003Sadrian 16, /*ALL_TARGET_HT20_1_3_9_11_17_19*/ 1067250003Sadrian 16, /*ALL_TARGET_HT20_4*/ 1068250003Sadrian 16, /*ALL_TARGET_HT20_5*/ 1069250003Sadrian 14, /*ALL_TARGET_HT20_6*/ 1070250003Sadrian 12, /*ALL_TARGET_HT20_7*/ 1071250003Sadrian 0, /*ALL_TARGET_HT20_12*/ 1072250003Sadrian 0, /*ALL_TARGET_HT20_13*/ 1073250003Sadrian 0, /*ALL_TARGET_HT20_14*/ 1074250003Sadrian 0, /*ALL_TARGET_HT20_15*/ 1075250003Sadrian 0, /*ALL_TARGET_HT20_20*/ 1076250003Sadrian 0, /*ALL_TARGET_HT20_21*/ 1077250003Sadrian 0, /*ALL_TARGET_HT20_22*/ 1078250003Sadrian 0, /*ALL_TARGET_HT20_23*/ 1079250003Sadrian 14, /*ALL_TARGET_HT40_0_8_16*/ 1080250003Sadrian 14, /*ALL_TARGET_HT40_1_3_9_11_17_19*/ 1081250003Sadrian 14, /*ALL_TARGET_HT40_4*/ 1082250003Sadrian 14, /*ALL_TARGET_HT40_5*/ 1083250003Sadrian 14, /*ALL_TARGET_HT40_6*/ 1084250003Sadrian 12, /*ALL_TARGET_HT40_7*/ 1085250003Sadrian 0, /*ALL_TARGET_HT40_12*/ 1086250003Sadrian 0, /*ALL_TARGET_HT40_13*/ 1087250003Sadrian 0, /*ALL_TARGET_HT40_14*/ 1088250003Sadrian 0, /*ALL_TARGET_HT40_15*/ 1089250003Sadrian 0, /*ALL_TARGET_HT40_20*/ 1090250003Sadrian 0, /*ALL_TARGET_HT40_21*/ 1091250003Sadrian 0, /*ALL_TARGET_HT40_22*/ 1092250003Sadrian 0 /*ALL_TARGET_HT40_23*/ 1093250003Sadrian}; 1094250003Sadrian 1095250003Sadrian/* MIMO Modes used in TPC calculations */ 1096250003Sadriantypedef enum { 1097250003Sadrian AR9300_DEF_MODE = 0, /* Could be CDD or Direct */ 1098250003Sadrian AR9300_TXBF_MODE, 1099250003Sadrian AR9300_STBC_MODE 1100250003Sadrian} AR9300_TXMODES; 1101250003Sadriantypedef enum { 1102250003Sadrian POSEIDON_STORED_REG_OBDB = 0, /* default OB/DB setting from ini */ 1103250003Sadrian POSEIDON_STORED_REG_TPC = 1, /* default txpower value in TPC reg */ 1104250003Sadrian POSEIDON_STORED_REG_BB_PWRTX_RATE9 = 2, /* default txpower value in 1105250003Sadrian * BB_powertx_rate9 reg 1106250003Sadrian */ 1107250003Sadrian POSEIDON_STORED_REG_SZ /* Can not add anymore */ 1108250003Sadrian} POSEIDON_STORED_REGS; 1109250003Sadrian 1110250003Sadriantypedef enum { 1111250003Sadrian POSEIDON_STORED_REG_G2_OLPC_OFFSET = 0,/* default OB/DB setting from ini */ 1112250003Sadrian POSEIDON_STORED_REG_G2_SZ /* should not exceed 3 */ 1113250003Sadrian} POSEIDON_STORED_REGS_G2; 1114250003Sadrian 1115250003Sadrian#if AH_NEED_TX_DATA_SWAP 1116250003Sadrian#if AH_NEED_RX_DATA_SWAP 1117250003Sadrian#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0) 1118250003Sadrian#else 1119250003Sadrian#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0) 1120250003Sadrian#endif 1121250003Sadrian#elif AH_NEED_RX_DATA_SWAP 1122250003Sadrian#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0) 1123250003Sadrian#else 1124250003Sadrian#define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0) 1125250003Sadrian#endif 1126250003Sadrian 1127250003Sadrianextern HAL_BOOL ar9300_rf_attach(struct ath_hal *, HAL_STATUS *); 1128250003Sadrian 1129250003Sadrianstruct ath_hal; 1130250003Sadrian 1131250003Sadrianextern struct ath_hal_9300 * ar9300_new_state(u_int16_t devid, 1132250003Sadrian HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, 1133250003Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, 1134250003Sadrian asf_amem_instance_handle amem_handle, 1135250003Sadrian struct hal_reg_parm *hal_conf_parm, HAL_STATUS *status); 1136250003Sadrianextern struct ath_hal * ar9300_attach(u_int16_t devid, 1137250003Sadrian HAL_ADAPTER_HANDLE osdev, HAL_SOFTC sc, 1138250003Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_BUS_TYPE bustype, 1139250003Sadrian asf_amem_instance_handle amem_handle, 1140250003Sadrian struct hal_reg_parm *hal_conf_parm, 1141250003Sadrian HAL_STATUS *status); 1142250003Sadrianextern void ar9300_detach(struct ath_hal *ah); 1143250003Sadrianextern void ar9300_read_revisions(struct ath_hal *ah); 1144250003Sadrianextern HAL_BOOL ar9300_chip_test(struct ath_hal *ah); 1145250003Sadrianextern HAL_BOOL ar9300_get_channel_edges(struct ath_hal *ah, 1146250003Sadrian u_int16_t flags, u_int16_t *low, u_int16_t *high); 1147250003Sadrianextern HAL_BOOL ar9300_fill_capability_info(struct ath_hal *ah); 1148250003Sadrian 1149250003Sadrianextern void ar9300_beacon_init(struct ath_hal *ah, 1150250003Sadrian u_int32_t next_beacon, u_int32_t beacon_period, HAL_OPMODE opmode); 1151250003Sadrianextern void ar9300_set_sta_beacon_timers(struct ath_hal *ah, 1152250003Sadrian const HAL_BEACON_STATE *); 1153250003Sadrian 1154250003Sadrianextern HAL_BOOL ar9300_is_interrupt_pending(struct ath_hal *ah); 1155250003Sadrianextern HAL_BOOL ar9300_get_pending_interrupts(struct ath_hal *ah, HAL_INT *, HAL_INT_TYPE, u_int8_t, HAL_BOOL); 1156250003Sadrianextern HAL_INT ar9300_get_interrupts(struct ath_hal *ah); 1157250003Sadrianextern HAL_INT ar9300_set_interrupts(struct ath_hal *ah, HAL_INT ints, HAL_BOOL); 1158250003Sadrianextern void ar9300_set_intr_mitigation_timer(struct ath_hal* ah, 1159250003Sadrian HAL_INT_MITIGATION reg, u_int32_t value); 1160250003Sadrianextern u_int32_t ar9300_get_intr_mitigation_timer(struct ath_hal* ah, 1161250003Sadrian HAL_INT_MITIGATION reg); 1162250003Sadrianextern u_int32_t ar9300_get_key_cache_size(struct ath_hal *); 1163250003Sadrianextern HAL_BOOL ar9300_is_key_cache_entry_valid(struct ath_hal *, u_int16_t entry); 1164250003Sadrianextern HAL_BOOL ar9300_reset_key_cache_entry(struct ath_hal *ah, u_int16_t entry); 1165250003Sadrianextern HAL_BOOL ar9300_set_key_cache_entry_mac(struct ath_hal *, 1166250003Sadrian u_int16_t entry, const u_int8_t *mac); 1167250003Sadrianextern HAL_BOOL ar9300_set_key_cache_entry(struct ath_hal *ah, u_int16_t entry, 1168250003Sadrian const HAL_KEYVAL *k, const u_int8_t *mac, int xor_key); 1169250003Sadrianextern HAL_BOOL ar9300_print_keycache(struct ath_hal *ah); 1170250003Sadrian 1171250003Sadrianextern void ar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac); 1172250003Sadrianextern HAL_BOOL ar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *); 1173250003Sadrianextern void ar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mac); 1174250003Sadrianextern HAL_BOOL ar9300_set_bss_id_mask(struct ath_hal *, const u_int8_t *); 1175250003Sadrianextern HAL_STATUS ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg); 1176250003Sadrianextern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz); 1177250003Sadrianextern HAL_BOOL ar9300_set_regulatory_domain(struct ath_hal *ah, 1178250003Sadrian u_int16_t reg_domain, HAL_STATUS *stats); 1179250003Sadrianextern u_int ar9300_get_wireless_modes(struct ath_hal *ah); 1180250003Sadrianextern void ar9300_enable_rf_kill(struct ath_hal *); 1181250003Sadrianextern HAL_BOOL ar9300_gpio_cfg_output(struct ath_hal *, u_int32_t gpio, HAL_GPIO_OUTPUT_MUX_TYPE signalType); 1182250003Sadrianextern HAL_BOOL ar9300_gpio_cfg_output_led_off(struct ath_hal *, u_int32_t gpio, HAL_GPIO_OUTPUT_MUX_TYPE signalType); 1183250003Sadrianextern HAL_BOOL ar9300_gpio_cfg_input(struct ath_hal *, u_int32_t gpio); 1184250003Sadrianextern HAL_BOOL ar9300_gpio_set(struct ath_hal *, u_int32_t gpio, u_int32_t val); 1185250003Sadrianextern u_int32_t ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio); 1186250003Sadrianextern u_int32_t ar9300_gpio_get_intr(struct ath_hal *ah); 1187250003Sadrianextern void ar9300_gpio_set_intr(struct ath_hal *ah, u_int, u_int32_t ilevel); 1188250003Sadrianextern u_int32_t ar9300_gpio_get_polarity(struct ath_hal *ah); 1189250003Sadrianextern void ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t, u_int32_t); 1190250003Sadrianextern u_int32_t ar9300_gpio_get_mask(struct ath_hal *ah); 1191250003Sadrianextern int ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map); 1192250003Sadrianextern void ar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state); 1193250003Sadrianextern void ar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enable); 1194250003Sadrianextern void ar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enable); 1195250003Sadrianextern void ar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 1196250003Sadrian u_int16_t assoc_id); 1197250003Sadrianextern u_int32_t ar9300_ppm_get_rssi_dump(struct ath_hal *); 1198250003Sadrianextern u_int32_t ar9300_ppm_arm_trigger(struct ath_hal *); 1199250003Sadrianextern int ar9300_ppm_get_trigger(struct ath_hal *); 1200250003Sadrianextern u_int32_t ar9300_ppm_force(struct ath_hal *); 1201250003Sadrianextern void ar9300_ppm_un_force(struct ath_hal *); 1202250003Sadrianextern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); 1203250003Sadrianextern u_int32_t ar9300_ppm_get_force_state(struct ath_hal *); 1204250003Sadrianextern void ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t); 1205250003Sadrianextern u_int32_t ar9300_get_dcs_mode(struct ath_hal *ah); 1206250003Sadrianextern u_int32_t ar9300_get_tsf32(struct ath_hal *ah); 1207250003Sadrianextern u_int64_t ar9300_get_tsf64(struct ath_hal *ah); 1208250003Sadrianextern u_int32_t ar9300_get_tsf2_32(struct ath_hal *ah); 1209250003Sadrianextern void ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf); 1210250003Sadrianextern void ar9300_reset_tsf(struct ath_hal *ah); 1211250003Sadrianextern void ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *pSet); 1212250003Sadrianextern u_int32_t ar9300_get_random_seed(struct ath_hal *ah); 1213250003Sadrianextern HAL_BOOL ar9300_detect_card_present(struct ath_hal *ah); 1214250003Sadrianextern void ar9300_update_mib_mac_stats(struct ath_hal *ah); 1215250003Sadrianextern void ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats); 1216250003Sadrianextern HAL_BOOL ar9300_is_japan_channel_spread_supported(struct ath_hal *ah); 1217250003Sadrianextern u_int32_t ar9300_get_cur_rssi(struct ath_hal *ah); 1218250003Sadrianextern u_int32_t ar9300_get_rssi_chain0(struct ath_hal *ah); 1219250003Sadrianextern u_int ar9300_get_def_antenna(struct ath_hal *ah); 1220250003Sadrianextern void ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna); 1221250003Sadrianextern HAL_BOOL ar9300_set_antenna_switch(struct ath_hal *ah, 1222250003Sadrian HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *, u_int8_t *, u_int8_t *); 1223250003Sadrianextern HAL_BOOL ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah); 1224250003Sadrianextern HAL_BOOL ar9300_set_slot_time(struct ath_hal *, u_int); 1225250003Sadrianextern HAL_BOOL ar9300_set_ack_timeout(struct ath_hal *, u_int); 1226250003Sadrianextern u_int ar9300_get_ack_timeout(struct ath_hal *); 1227250003Sadrianextern HAL_STATUS ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 1228250003Sadrian u_int32_t next_start, HAL_QUIET_FLAG flag); 1229250003Sadrianextern void ar9300_set_pcu_config(struct ath_hal *); 1230250003Sadrianextern HAL_STATUS ar9300_get_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1231250003Sadrian u_int32_t, u_int32_t *); 1232250003Sadrianextern HAL_BOOL ar9300_set_capability(struct ath_hal *, HAL_CAPABILITY_TYPE, 1233250003Sadrian u_int32_t, u_int32_t, HAL_STATUS *); 1234250003Sadrianextern HAL_BOOL ar9300_get_diag_state(struct ath_hal *ah, int request, 1235250003Sadrian const void *args, u_int32_t argsize, 1236250003Sadrian void **result, u_int32_t *resultsize); 1237250003Sadrianextern void ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info); 1238250003Sadrianextern int8_t ar9300_get_11n_ext_busy(struct ath_hal *ah); 1239250003Sadrianextern void ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode); 1240250003Sadrianextern HAL_HT_RXCLEAR ar9300_get_11n_rx_clear(struct ath_hal *ah); 1241250003Sadrianextern void ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear); 1242250003Sadrianextern HAL_BOOL ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, 1243250003Sadrian int set_chip); 1244250003Sadrianextern HAL_POWER_MODE ar9300_get_power_mode(struct ath_hal *ah); 1245250003Sadrianextern HAL_BOOL ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip); 1246250003Sadrianextern void ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode); 1247250003Sadrian 1248250003Sadrianextern void ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off); 1249250003Sadrian 1250250003Sadrianextern void ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 1251250003Sadrian u_int16_t assoc_id); 1252250003Sadrian 1253250003Sadrian 1254250003Sadrian#if ATH_WOW 1255250003Sadrianextern void ar9300_wow_apply_pattern(struct ath_hal *ah, u_int8_t *p_ath_pattern, 1256250003Sadrian u_int8_t *p_ath_mask, int32_t pattern_count, u_int32_t ath_pattern_len); 1257250003Sadrian//extern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah,u_int8_t *chipPatternBytes); 1258250003Sadrianextern u_int32_t ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnable); 1259250003Sadrianextern HAL_BOOL ar9300_wow_enable(struct ath_hal *ah, u_int32_t pattern_enable, u_int32_t timeout_in_seconds, int clearbssid, 1260250003Sadrian HAL_BOOL offloadEnable); 1261250003Sadrian#if ATH_WOW_OFFLOAD 1262250003Sadrian/* ARP offload */ 1263250003Sadrian#define WOW_OFFLOAD_ARP_INFO_MAX 2 1264250003Sadrian 1265250003Sadrianstruct hal_wow_offload_arp_info { 1266250003Sadrian u_int32_t valid; 1267250003Sadrian u_int32_t id; 1268250003Sadrian 1269250003Sadrian u_int32_t Flags; 1270250003Sadrian union { 1271250003Sadrian u_int8_t u8[4]; 1272250003Sadrian u_int32_t u32; 1273250003Sadrian } RemoteIPv4Address; 1274250003Sadrian union { 1275250003Sadrian u_int8_t u8[4]; 1276250003Sadrian u_int32_t u32; 1277250003Sadrian } HostIPv4Address; 1278250003Sadrian union { 1279250003Sadrian u_int8_t u8[6]; 1280250003Sadrian u_int32_t u32[2]; 1281250003Sadrian } MacAddress; 1282250003Sadrian}; 1283250003Sadrian 1284250003Sadrian/* NS offload */ 1285250003Sadrian#define WOW_OFFLOAD_NS_INFO_MAX 2 1286250003Sadrian 1287250003Sadrianstruct hal_wow_offload_ns_info { 1288250003Sadrian u_int32_t valid; 1289250003Sadrian u_int32_t id; 1290250003Sadrian 1291250003Sadrian u_int32_t Flags; 1292250003Sadrian union { 1293250003Sadrian u_int8_t u8[16]; 1294250003Sadrian u_int32_t u32[4]; 1295250003Sadrian } RemoteIPv6Address; 1296250003Sadrian union { 1297250003Sadrian u_int8_t u8[16]; 1298250003Sadrian u_int32_t u32[4]; 1299250003Sadrian } SolicitedNodeIPv6Address; 1300250003Sadrian union { 1301250003Sadrian u_int8_t u8[6]; 1302250003Sadrian u_int32_t u32[2]; 1303250003Sadrian } MacAddress; 1304250003Sadrian union { 1305250003Sadrian u_int8_t u8[16]; 1306250003Sadrian u_int32_t u32[4]; 1307250003Sadrian } TargetIPv6Addresses[2]; 1308250003Sadrian}; 1309250003Sadrian 1310250003Sadrianextern void ar9300_wowoffload_prep(struct ath_hal *ah); 1311250003Sadrianextern void ar9300_wowoffload_post(struct ath_hal *ah); 1312250003Sadrianextern u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t size); 1313250003Sadrianextern void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param); 1314250003Sadrianextern void ar9300_wowoffload_download_acer_magic(struct ath_hal *ah, HAL_BOOL valid, u_int8_t* datap, u_int32_t bytes); 1315250003Sadrianextern void ar9300_wowoffload_download_acer_swka(struct ath_hal *ah, u_int32_t id, HAL_BOOL valid, u_int32_t period, u_int32_t size, u_int32_t* datap); 1316250003Sadrianextern void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1317250003Sadrianextern void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data); 1318250003Sadrian#endif /* ATH_WOW_OFFLOAD */ 1319250003Sadrian#endif 1320250003Sadrian 1321250003Sadrianextern HAL_BOOL ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, 1322250003Sadrian HAL_CHANNEL *chan, HAL_HT_MACMODE macmode, u_int8_t txchainmask, 1323250003Sadrian u_int8_t rxchainmask, HAL_HT_EXTPROTSPACING extprotspacing, 1324250003Sadrian HAL_BOOL b_channel_change, HAL_STATUS *status, int is_scan); 1325250003Sadrianextern HAL_BOOL ar9300_lean_channel_change(struct ath_hal *ah, HAL_OPMODE opmode, HAL_CHANNEL *chan, 1326250003Sadrian HAL_HT_MACMODE macmode, u_int8_t txchainmask, u_int8_t rxchainmask); 1327250003Sadrianextern HAL_BOOL ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type); 1328250003Sadrianextern void ar9300_init_pll(struct ath_hal *ah, HAL_CHANNEL *chan); 1329250003Sadrianextern void ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t rxMask); 1330250003Sadrianextern u_int16_t ar9300_is_single_ant_power_save_possible(struct ath_hal *ah); 1331250003Sadrianextern void ar9300_set_operating_mode(struct ath_hal *ah, int opmode); 1332250003Sadrianextern HAL_BOOL ar9300_phy_disable(struct ath_hal *ah); 1333250003Sadrianextern HAL_BOOL ar9300_disable(struct ath_hal *ah); 1334250003Sadrianextern HAL_BOOL ar9300_chip_reset(struct ath_hal *ah, HAL_CHANNEL *); 1335250003Sadrianextern HAL_BOOL ar9300_calibration(struct ath_hal *ah, HAL_CHANNEL *chan, 1336250003Sadrian u_int8_t rxchainmask, HAL_BOOL longcal, HAL_BOOL *isIQdone, int is_scan, u_int32_t *sched_cals); 1337250003Sadrianextern void ar9300_reset_cal_valid(struct ath_hal *ah, HAL_CHANNEL *chan, 1338250003Sadrian HAL_BOOL *isIQdone, u_int32_t cal_type); 1339250003Sadrianextern void ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains); 1340250003Sadrianextern void ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains); 1341250003Sadrianextern void ar9300_temp_comp_cal_collect(struct ath_hal *ah); 1342250003Sadrianextern void ar9300_temp_comp_calibration(struct ath_hal *ah, u_int8_t num_chains); 1343250003Sadrianextern int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah); 1344250003Sadrianextern void ar9300_upload_noise_floor(struct ath_hal *ah, int is2G, int16_t nfarray[]); 1345250003Sadrian 1346250003Sadrianextern HAL_BOOL ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit, 1347250003Sadrian u_int16_t extra_txpow, u_int16_t tpc_in_db); 1348250003Sadrianextern void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf, 1349250003Sadrian HAL_CHANNEL *chan, int is_scan); 1350250003Sadrianextern HAL_BOOL ar9300_load_nf(struct ath_hal *ah, int16_t nf[]); 1351250003Sadrian 1352250003Sadrianextern HAL_RFGAIN ar9300_get_rfgain(struct ath_hal *ah); 1353250003Sadrianextern const HAL_RATE_TABLE *ar9300_get_rate_table(struct ath_hal *, u_int mode); 1354250003Sadrianextern int16_t ar9300_get_rate_txpower(struct ath_hal *ah, u_int mode, 1355250003Sadrian u_int8_t rate_index, u_int8_t chainmask, u_int8_t mimo_mode); 1356250003Sadrianextern void ar9300_init_rate_txpower(struct ath_hal *ah, u_int mode, 1357250003Sadrian HAL_CHANNEL_INTERNAL *chan, 1358250003Sadrian u_int8_t powerPerRate[], 1359250003Sadrian u_int8_t chainmask); 1360250003Sadrianextern void ar9300_adjust_reg_txpower_cdd(struct ath_hal *ah, 1361250003Sadrian u_int8_t powerPerRate[]); 1362250003Sadrianextern void ar9300_reset_tx_status_ring(struct ath_hal *ah); 1363250003Sadrianextern void ar9300_enable_mib_counters(struct ath_hal *); 1364250003Sadrianextern void ar9300_disable_mib_counters(struct ath_hal *); 1365250003Sadrianextern void ar9300_ani_attach(struct ath_hal *); 1366250003Sadrianextern void ar9300_ani_detach(struct ath_hal *); 1367250003Sadrianextern struct ar9300_ani_state *ar9300_ani_get_current_state(struct ath_hal *); 1368250003Sadrianextern struct ar9300_stats *ar9300_ani_get_current_stats(struct ath_hal *); 1369250003Sadrianextern HAL_BOOL ar9300_ani_control(struct ath_hal *, HAL_ANI_CMD cmd, int param); 1370250003Sadrianstruct ath_rx_status; 1371250003Sadrian 1372250003Sadrianextern void ar9300_process_mib_intr(struct ath_hal *, const HAL_NODE_STATS *); 1373250003Sadrianextern void ar9300_ani_ar_poll(struct ath_hal *, const HAL_NODE_STATS *, 1374250003Sadrian HAL_CHANNEL *, HAL_ANISTATS *); 1375250003Sadrianextern void ar9300_ani_reset(struct ath_hal *, HAL_BOOL is_scanning); 1376250003Sadrianextern void ar9300_ani_init_defaults(struct ath_hal *ah, HAL_HT_MACMODE macmode); 1377250003Sadrianextern void ar9300_enable_tpc(struct ath_hal *); 1378250003Sadrian 1379250003Sadrianextern HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is2GHz); 1380250003Sadrianextern void ar9300_rx_gain_table_apply(struct ath_hal *ah); 1381250003Sadrianextern void ar9300_tx_gain_table_apply(struct ath_hal *ah); 1382250003Sadrianextern void ar9300_mat_enable(struct ath_hal *ah, int enable); 1383250003Sadrianextern void ar9300_dump_keycache(struct ath_hal *ah, int n, u_int32_t *entry); 1384250003Sadrianextern HAL_BOOL ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal * ah, HAL_BOOL enable, HAL_CHANNEL * chan); 1385250003Sadrian 1386250003Sadrian#ifdef AH_SUPPORT_AR9300 1387250003Sadrian/* BB Panic Watchdog declarations */ 1388250003Sadrian#define HAL_BB_PANIC_WD_TMO 25 /* in ms, 0 to disable */ 1389250003Sadrian#define HAL_BB_PANIC_WD_TMO_HORNET 85 1390250003Sadrianextern void ar9300_config_bb_panic_watchdog(struct ath_hal *); 1391250003Sadrianextern void ar9300_handle_bb_panic(struct ath_hal *); 1392250003Sadrianextern int ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic); 1393250003Sadrianextern HAL_BOOL ar9300_handle_radar_bb_panic(struct ath_hal *ah); 1394250003Sadrian#endif 1395250003Sadrianextern void ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason); 1396250003Sadrian 1397250003Sadrian/* DFS declarations */ 1398250003Sadrian#ifdef ATH_SUPPORT_DFS 1399250003Sadrianextern void ar9300_check_dfs(struct ath_hal *ah, HAL_CHANNEL *chan); 1400250003Sadrianextern void ar9300_dfs_found(struct ath_hal *ah, HAL_CHANNEL *chan, 1401250003Sadrian u_int64_t nolTime); 1402250003Sadrianextern void ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1403250003Sadrianextern void ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe); 1404250003Sadrianextern HAL_BOOL ar9300_radar_wait(struct ath_hal *ah, HAL_CHANNEL *chan); 1405250003Sadrianextern struct dfs_pulse * ar9300_get_dfs_radars(struct ath_hal *ah, 1406250003Sadrian u_int32_t dfsdomain, int *numradars, struct dfs_bin5pulse **bin5pulses, 1407250003Sadrian int *numb5radars, HAL_PHYERR_PARAM *pe); 1408250003Sadrianextern void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val); 1409250003Sadrianextern u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable); 1410250003Sadrianextern void ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable); 1411250003Sadrianextern void ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start); 1412250003Sadrian#endif 1413250003Sadrian 1414250003Sadrianextern HAL_CHANNEL * ar9300_get_extension_channel(struct ath_hal *ah); 1415250003Sadrianextern HAL_BOOL ar9300_is_fast_clock_enabled(struct ath_hal *ah); 1416250003Sadrian 1417250003Sadrian 1418250003Sadrianextern void ar9300_mark_phy_inactive(struct ath_hal *ah); 1419250003Sadrian 1420250003Sadrian/* Spectral scan declarations */ 1421250003Sadrianextern void ar9300_configure_spectral_scan(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1422250003Sadrianextern void ar9300_set_cca_threshold(struct ath_hal *ah, u_int8_t thresh62); 1423250003Sadrianextern void ar9300_get_spectral_params(struct ath_hal *ah, HAL_SPECTRAL_PARAM *ss); 1424250003Sadrianextern HAL_BOOL ar9300_is_spectral_active(struct ath_hal *ah); 1425250003Sadrianextern HAL_BOOL ar9300_is_spectral_enabled(struct ath_hal *ah); 1426250003Sadrianextern void ar9300_start_spectral_scan(struct ath_hal *ah); 1427250003Sadrianextern void ar9300_stop_spectral_scan(struct ath_hal *ah); 1428250003Sadrianextern u_int32_t ar9300_get_spectral_config(struct ath_hal *ah); 1429250003Sadrianextern void ar9300_restore_spectral_config(struct ath_hal *ah, u_int32_t restoreval); 1430250003Sadrianint16_t ar9300_get_ctl_chan_nf(struct ath_hal *ah); 1431250003Sadrianint16_t ar9300_get_ext_chan_nf(struct ath_hal *ah); 1432250003Sadrian/* End spectral scan declarations */ 1433250003Sadrian 1434250003Sadrian/* Raw ADC capture functions */ 1435250003Sadrianextern void ar9300_enable_test_addac_mode(struct ath_hal *ah); 1436250003Sadrianextern void ar9300_disable_test_addac_mode(struct ath_hal *ah); 1437250003Sadrianextern void ar9300_begin_adc_capture(struct ath_hal *ah, int auto_agc_gain); 1438250003Sadrianextern HAL_STATUS ar9300_retrieve_capture_data(struct ath_hal *ah, u_int16_t chain_mask, int disable_dc_filter, void *sample_buf, u_int32_t *max_samples); 1439250003Sadrianextern HAL_STATUS ar9300_calc_adc_ref_powers(struct ath_hal *ah, int freq_mhz, int16_t *sample_min, int16_t *sample_max, int32_t *chain_ref_pwr, int num_chain_ref_pwr); 1440250003Sadrianextern HAL_STATUS ar9300_get_min_agc_gain(struct ath_hal *ah, int freq_mhz, int32_t *chain_gain, int num_chain_gain); 1441250003Sadrian 1442250003Sadrianextern HAL_BOOL ar9300_reset_11n(struct ath_hal *ah, HAL_OPMODE opmode, 1443250003Sadrian HAL_CHANNEL *chan, HAL_BOOL b_channel_change, HAL_STATUS *status); 1444250003Sadrianextern void ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now); 1445250003Sadrian 1446250003Sadrianextern void ar9300_get_channel_centers(struct ath_hal *ah, 1447250003Sadrian HAL_CHANNEL_INTERNAL *chan, 1448250003Sadrian CHAN_CENTERS *centers); 1449250003Sadrianextern u_int16_t ar9300_get_ctl_center(struct ath_hal *ah, 1450250003Sadrian HAL_CHANNEL_INTERNAL *chan); 1451250003Sadrianextern u_int16_t ar9300_get_ext_center(struct ath_hal *ah, 1452250003Sadrian HAL_CHANNEL_INTERNAL *chan); 1453250003Sadrianextern u_int32_t ar9300_get_mib_cycle_counts_pct(struct ath_hal *, u_int32_t*, u_int32_t*, u_int32_t*); 1454250003Sadrian 1455250003Sadrianextern void ar9300_dma_reg_dump(struct ath_hal *); 1456250003Sadrianextern HAL_BOOL ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable); 1457250003Sadrianextern HAL_BOOL ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable); 1458250003Sadrianextern HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable); 1459250003Sadrianextern HAL_BOOL ar9300_detect_bb_hang(struct ath_hal *ah); 1460250003Sadrianextern HAL_BOOL ar9300_detect_mac_hang(struct ath_hal *ah); 1461250003Sadrian 1462250003Sadrian#ifdef ATH_BT_COEX 1463250003Sadrianextern void ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo); 1464250003Sadrianextern void ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf); 1465250003Sadrianextern void ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum); 1466250003Sadrianextern void ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1467250003Sadrianextern void ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh); 1468250003Sadrianextern void ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, u_int32_t value); 1469250003Sadrianextern void ar9300_bt_coex_disable(struct ath_hal *ah); 1470250003Sadrianextern int ar9300_bt_coex_enable(struct ath_hal *ah); 1471250003Sadrianextern void ar9300_init_bt_coex(struct ath_hal *ah); 1472250003Sadrianextern u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg); 1473250003Sadrianextern u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn); 1474250003Sadrian#endif 1475250003Sadrianextern int ar9300_alloc_generic_timer(struct ath_hal *ah, HAL_GEN_TIMER_DOMAIN tsf); 1476250003Sadrianextern void ar9300_free_generic_timer(struct ath_hal *ah, int index); 1477250003Sadrianextern void ar9300_start_generic_timer(struct ath_hal *ah, int index, u_int32_t timer_next, 1478250003Sadrian u_int32_t timer_period); 1479250003Sadrianextern void ar9300_stop_generic_timer(struct ath_hal *ah, int index); 1480250003Sadrianextern void ar9300_get_gen_timer_interrupts(struct ath_hal *ah, u_int32_t *trigger, 1481250003Sadrian u_int32_t *thresh); 1482250003Sadrianextern void ar9300_start_tsf2(struct ath_hal *ah); 1483250003Sadrian 1484250003Sadrianextern void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi); 1485250003Sadrianextern HAL_BOOL ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah); 1486250003Sadrianextern void ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah); 1487250003Sadrianextern void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value); 1488250003Sadrianextern void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah); 1489250003Sadrianextern int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah); 1490250003Sadrianextern void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 1491250003Sadrian u_int32_t rssi_threshold); 1492250003Sadrianextern void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah); 1493250003Sadrianextern void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on); 1494250003Sadrianextern HAL_BOOL ar9300_is_ani_noise_spur(struct ath_hal *ah); 1495250003Sadrianextern void ar9300_get_vow_stats(struct ath_hal *ah, HAL_VOWSTATS *p_stats, 1496250003Sadrian u_int8_t); 1497250003Sadrian 1498250003Sadrianextern int ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq); 1499250003Sadrianextern int ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq); 1500250003Sadrianextern void ar9300_wow_set_gpio_reset_low(struct ath_hal * ah); 1501250003Sadrianextern void ar9300_get_mib_cycle_counts(struct ath_hal *, HAL_COUNTERS*); 1502250003Sadrianextern void ar9300_clear_mib_counters(struct ath_hal *ah); 1503250003Sadrian 1504250003Sadrian/* EEPROM interface functions */ 1505250003Sadrian/* Common Interface functions */ 1506250003Sadrianextern HAL_STATUS ar9300_eeprom_attach(struct ath_hal *); 1507250003Sadrianextern u_int32_t ar9300_eeprom_get(struct ath_hal_9300 *ahp, EEPROM_PARAM param); 1508250003Sadrian 1509250003Sadrianextern u_int32_t ar9300_ini_fixup(struct ath_hal *ah, 1510250003Sadrian ar9300_eeprom_t *p_eep_data, 1511250003Sadrian u_int32_t reg, 1512250003Sadrian u_int32_t val); 1513250003Sadrian 1514250003Sadrianextern HAL_STATUS ar9300_eeprom_set_transmit_power(struct ath_hal *ah, 1515250003Sadrian ar9300_eeprom_t *p_eep_data, HAL_CHANNEL_INTERNAL *chan, 1516250003Sadrian u_int16_t cfg_ctl, u_int16_t twice_antenna_reduction, 1517250003Sadrian u_int16_t twice_max_regulatory_power, u_int16_t power_limit); 1518250003Sadrianextern void ar9300_eeprom_set_addac(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 1519250003Sadrianextern HAL_BOOL ar9300_eeprom_set_param(struct ath_hal *ah, EEPROM_PARAM param, u_int32_t value); 1520250003Sadrianextern HAL_BOOL ar9300_eeprom_set_board_values(struct ath_hal *, HAL_CHANNEL_INTERNAL *); 1521250003Sadrianextern HAL_BOOL ar9300_eeprom_read_word(struct ath_hal *, u_int off, u_int16_t *data); 1522250003Sadrianextern HAL_BOOL ar9300_eeprom_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many); 1523250003Sadrianextern HAL_BOOL ar9300_otp_read(struct ath_hal *ah, u_int off, u_int32_t *data, HAL_BOOL is_wifi); 1524250003Sadrian 1525250003Sadrianextern HAL_BOOL ar9300_flash_read(struct ath_hal *, u_int off, u_int16_t *data); 1526250003Sadrianextern HAL_BOOL ar9300_flash_write(struct ath_hal *, u_int off, u_int16_t data); 1527250003Sadrianextern u_int ar9300_eeprom_dump_support(struct ath_hal *ah, void **pp_e); 1528250003Sadrianextern u_int8_t ar9300_eeprom_get_num_ant_config(struct ath_hal_9300 *ahp, HAL_FREQ_BAND freq_band); 1529250003Sadrianextern HAL_STATUS ar9300_eeprom_get_ant_cfg(struct ath_hal_9300 *ahp, HAL_CHANNEL_INTERNAL *chan, 1530250003Sadrian u_int8_t index, u_int16_t *config); 1531250003Sadrianextern u_int8_t* ar9300_eeprom_get_cust_data(struct ath_hal_9300 *ahp); 1532250003Sadrianextern u_int8_t *ar9300_eeprom_get_spur_chans_ptr(struct ath_hal *ah, HAL_BOOL is_2ghz); 1533250003Sadrianextern HAL_BOOL ar9300_interference_is_present(struct ath_hal *ah); 1534250003Sadrianextern HAL_BOOL ar9300_tuning_caps_apply(struct ath_hal *ah); 1535250003Sadrianextern void ar9300_disp_tpc_tables(struct ath_hal *ah); 1536250003Sadrianextern u_int8_t *ar9300_get_tpc_tables(struct ath_hal *ah); 1537250003Sadrianextern u_int8_t ar9300_eeprom_set_tx_gain_cap(struct ath_hal *ah, int *tx_gain_max); 1538250003Sadrianextern u_int8_t ar9300_eeprom_tx_gain_table_index_max_apply(struct ath_hal *ah, u_int16_t channel); 1539250003Sadrian 1540250003Sadrian/* Common EEPROM Help function */ 1541250003Sadrianextern void ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable); 1542250003Sadrianextern void ar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs); 1543250003Sadrian 1544250003Sadrianextern u_int ar9300_mac_to_clks(struct ath_hal *ah, u_int clks); 1545250003Sadrian 1546250003Sadrian/* tx_bf interface */ 1547250003Sadrian#define ar9300_init_txbf(ah) 1548250003Sadrian#define ar9300_set_11n_txbf_sounding(ah, ds, series, cec, opt) 1549250003Sadrian#define ar9300_set_11n_txbf_cal(ah, ds, cal_pos, code_rate, cec, opt) 1550250003Sadrian#define ar9300_txbf_save_cv_from_compress( \ 1551250003Sadrian ah, key_idx, mimo_control, compress_rpt) \ 1552250003Sadrian false 1553250003Sadrian#define ar9300_txbf_save_cv_from_non_compress( \ 1554250003Sadrian ah, key_idx, mimo_control, non_compress_rpt) \ 1555250003Sadrian false 1556250003Sadrian#define ar9300_txbf_rc_update( \ 1557250003Sadrian ah, rx_status, local_h, csi_frame, ness_a, ness_b, bw) \ 1558250003Sadrian false 1559250003Sadrian#define ar9300_fill_csi_frame( \ 1560250003Sadrian ah, rx_status, bandwidth, local_h, csi_frame_body) \ 1561250003Sadrian 0 1562250003Sadrian#define ar9300_fill_txbf_capabilities(ah) 1563250003Sadrian#define ar9300_get_txbf_capabilities(ah) NULL 1564250003Sadrian#define ar9300_txbf_set_key( \ 1565250003Sadrian ah, entry, rx_staggered_sounding, channel_estimation_cap, mmss) 1566250003Sadrian#define ar9300_read_key_cache_mac(ah, entry, mac) false 1567250003Sadrian#define ar9300_txbf_get_cv_cache_nr(ah, key_idx, nr) 1568250003Sadrian#define ar9300_set_selfgenrate_limit(ah, ts_ratecode) 1569250003Sadrian#define ar9300_reset_lowest_txrate(ah) 1570250003Sadrian#define ar9300_txbf_set_basic_set(ah) 1571250003Sadrian 1572250003Sadrianextern void ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs); 1573250003Sadrianextern void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah); 1574250003Sadrian 1575250003Sadrian 1576250003Sadrian 1577250003Sadrian#if ATH_SUPPORT_MCI 1578250003Sadrianextern void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type); 1579250003Sadrianextern void ar9300_mci_bt_coex_disable(struct ath_hal *ah); 1580250003Sadrianextern int ar9300_mci_bt_coex_enable(struct ath_hal *ah); 1581250003Sadrianextern void ar9300_mci_setup (struct ath_hal *ah, u_int32_t gpm_addr, 1582250003Sadrian void *gpm_buf, u_int16_t len, 1583250003Sadrian u_int32_t sched_addr); 1584250003Sadrianextern void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done); 1585250003Sadrianextern void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done); 1586250003Sadrianextern void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done); 1587250003Sadrianextern HAL_BOOL ar9300_mci_send_message (struct ath_hal *ah, u_int8_t header, 1588250003Sadrian u_int32_t flag, u_int32_t *payload, u_int8_t len, 1589250003Sadrian HAL_BOOL wait_done, HAL_BOOL check_bt); 1590250003Sadrianextern u_int32_t ar9300_mci_get_interrupt (struct ath_hal *ah, 1591250003Sadrian u_int32_t *mci_int, 1592250003Sadrian u_int32_t *mci_int_rx_msg); 1593250003Sadrianextern u_int32_t ar9300_mci_state (struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data); 1594250003Sadrianextern void ar9300_mci_reset (struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g, HAL_BOOL is_full_sleep); 1595250003Sadrianextern void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah, HAL_BOOL halt, HAL_BOOL wait_done); 1596250003Sadrianextern void ar9300_mci_mute_bt(struct ath_hal *ah); 1597250003Sadrianextern u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type, u_int8_t gpm_opcode, int32_t time_out); 1598250003Sadrianextern void ar9300_mci_enable_interrupt(struct ath_hal *ah); 1599250003Sadrianextern void ar9300_mci_disable_interrupt(struct ath_hal *ah); 1600250003Sadrianextern void ar9300_mci_detach (struct ath_hal *ah); 1601250003Sadrianextern u_int32_t ar9300_mci_check_int (struct ath_hal *ah, u_int32_t ints); 1602250003Sadrianextern void ar9300_mci_sync_bt_state (struct ath_hal *ah); 1603250003Sadrianextern void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g); 1604250003Sadrianextern void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done); 1605250003Sadrian#if ATH_SUPPORT_AIC 1606250003Sadrianextern u_int32_t ar9300_aic_calibration (struct ath_hal *ah); 1607250003Sadrianextern u_int32_t ar9300_aic_start_normal (struct ath_hal *ah); 1608250003Sadrian#endif 1609250003Sadrian#endif 1610250003Sadrian 1611250003Sadrianextern HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable); 1612250003Sadrian 1613250003Sadrianextern HAL_BOOL ar9300_regulatory_domain_override( 1614250003Sadrian struct ath_hal *ah, u_int16_t regdmn); 1615250003Sadrian#if ATH_ANT_DIV_COMB 1616250003Sadrianextern void ar9300_ant_div_comb_get_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1617250003Sadrianextern void ar9300_ant_div_comb_set_config(struct ath_hal *ah, HAL_ANT_COMB_CONFIG* div_comb_conf); 1618250003Sadrian#endif /* ATH_ANT_DIV_COMB */ 1619250003Sadrianextern void ar9300_disable_phy_restart(struct ath_hal *ah, 1620250003Sadrian int disable_phy_restart); 1621250003Sadrianextern void ar9300_enable_keysearch_always(struct ath_hal *ah, int enable); 1622250003Sadrianextern HAL_BOOL ar9300ForceVCS( struct ath_hal *ah); 1623250003Sadrianextern HAL_BOOL ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val); 1624250003Sadrianextern HAL_BOOL ar9300Get3StreamSignature( struct ath_hal *ah); 1625250003Sadrian 1626250003Sadrian#ifdef ATH_TX99_DIAG 1627250003Sadrian#ifndef ATH_SUPPORT_HTC 1628250003Sadrianextern void ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, u_int32_t txpower); 1629250003Sadrianextern void ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask); 1630250003Sadrianextern void ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, int chtype); 1631250003Sadrianextern void ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data); 1632250003Sadrianextern void ar9300_tx99_stop(struct ath_hal *ah); 1633250003Sadrian#endif /* ATH_SUPPORT_HTC */ 1634250003Sadrian#endif /* ATH_TX99_DIAG */ 1635250003Sadrian 1636250003Sadrianenum { 1637250003Sadrian AR9300_COEFF_TX_TYPE = 0, 1638250003Sadrian AR9300_COEFF_RX_TYPE 1639250003Sadrian}; 1640250003Sadrian 1641250003Sadrian#endif /* _ATH_AR9300_H_ */ 1642