1294838Szbb/*- 2294838Szbb******************************************************************************* 3294838SzbbCopyright (C) 2015 Annapurna Labs Ltd. 4294838Szbb 5294838SzbbThis file may be licensed under the terms of the Annapurna Labs Commercial 6294838SzbbLicense Agreement. 7294838Szbb 8294838SzbbAlternatively, this file can be distributed under the terms of the GNU General 9294838SzbbPublic License V2 as published by the Free Software Foundation and can be 10294838Szbbfound at http://www.gnu.org/licenses/gpl-2.0.html 11294838Szbb 12294838SzbbAlternatively, redistribution and use in source and binary forms, with or 13294838Szbbwithout modification, are permitted provided that the following conditions are 14294838Szbbmet: 15294838Szbb 16294838Szbb * Redistributions of source code must retain the above copyright notice, 17294838Szbb this list of conditions and the following disclaimer. 18294838Szbb 19294838Szbb * Redistributions in binary form must reproduce the above copyright 20294838Szbb notice, this list of conditions and the following disclaimer in 21294838Szbb the documentation and/or other materials provided with the 22294838Szbb distribution. 23294838Szbb 24294838Szbb THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25294838Szbb ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26294838Szbb WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27294838Szbb DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28294838Szbb ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29294838Szbb (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30294838Szbb LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31294838Szbb ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32294838Szbb (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33294838Szbb SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34294838Szbb 35294838Szbb*******************************************************************************/ 36294838Szbb 37294838Szbb/** 38294838Szbb * @{ 39294838Szbb * @file al_hal_an_lt_wrapper_regs.h 40294838Szbb * 41294838Szbb * @brief ... registers 42294838Szbb * 43294838Szbb */ 44294838Szbb 45294838Szbb#ifndef __AL_HAL_AN_LT_wrapper_REGS_H__ 46294838Szbb#define __AL_HAL_AN_LT_wrapper_REGS_H__ 47294838Szbb 48294838Szbb#include "al_hal_plat_types.h" 49294838Szbb 50294838Szbb#ifdef __cplusplus 51294838Szbbextern "C" { 52294838Szbb#endif 53294838Szbb/* 54294838Szbb* Unit Registers 55294838Szbb*/ 56294838Szbb 57294838Szbb 58294838Szbb 59294838Szbbstruct al_an_lt_wrapper_gen { 60294838Szbb /* [0x0] AN LT wrapper Version */ 61294838Szbb uint32_t version; 62294838Szbb /* [0x4] AN LT general configuration */ 63294838Szbb uint32_t cfg; 64294838Szbb uint32_t rsrvd[14]; 65294838Szbb}; 66294838Szbbstruct al_an_lt_wrapper_an_lt { 67294838Szbb /* [0x0] AN LT register file address */ 68294838Szbb uint32_t addr; 69294838Szbb /* [0x4] PCS register file data */ 70294838Szbb uint32_t data; 71294838Szbb /* [0x8] AN LT control signals */ 72294838Szbb uint32_t ctrl; 73294838Szbb /* [0xc] AN LT status signals */ 74294838Szbb uint32_t status; 75294838Szbb uint32_t rsrvd[4]; 76294838Szbb}; 77294838Szbb 78294838Szbbenum al_eth_an_lt_unit { 79294838Szbb AL_ETH_AN_LT_UNIT_32_BIT = 0, 80294838Szbb AL_ETH_AN_LT_UNIT_20_BIT = 1, 81294838Szbb AL_ETH_AN_LT_UNIT_16_BIT = 2, 82294838Szbb}; 83294838Szbb 84294838Szbbstruct al_an_lt_wrapper_regs { 85294838Szbb uint32_t rsrvd_0[64]; 86294838Szbb struct al_an_lt_wrapper_gen gen; /* [0x100] */ 87294838Szbb struct al_an_lt_wrapper_an_lt an_lt[3]; /* [0x140] */ 88294838Szbb}; 89294838Szbb 90294838Szbb 91294838Szbb/* 92294838Szbb* Registers Fields 93294838Szbb*/ 94294838Szbb 95294838Szbb 96294838Szbb/**** version register ****/ 97294838Szbb/* Revision number (Minor) */ 98294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF 99294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0 100294838Szbb/* Revision number (Major) */ 101294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00 102294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8 103294838Szbb/* Date of release */ 104294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_DATE_DAY_MASK 0x001F0000 105294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_DATE_DAY_SHIFT 16 106294838Szbb/* Month of release */ 107294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_DATA_MONTH_MASK 0x01E00000 108294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_DATA_MONTH_SHIFT 21 109294838Szbb/* Year of release (starting from 2000) */ 110294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_DATE_YEAR_MASK 0x3E000000 111294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_DATE_YEAR_SHIFT 25 112294838Szbb/* Reserved */ 113294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_RESERVED_MASK 0xC0000000 114294838Szbb#define AN_LT_WRAPPER_GEN_VERSION_RESERVED_SHIFT 30 115294838Szbb 116294838Szbb/**** cfg register ****/ 117294838Szbb/* 118294838Szbb * selection between different bus widths: 119294838Szbb * 0 ��� 16 120294838Szbb * 1 ��� 20 121294838Szbb * 2 ��� 32 122294838Szbb * 3 ��� N/A 123294838Szbb */ 124294838Szbb#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK 0x00000003 125294838Szbb#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT 0 126294838Szbb/* 127294838Szbb * selection between different bus widths: 128294838Szbb * 0 ��� 16 129294838Szbb * 1 ��� 20 130294838Szbb * 2 ��� 32 131294838Szbb * 3 ��� N/A 132294838Szbb */ 133294838Szbb#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK 0x0000000C 134294838Szbb#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT 2 135294838Szbb/* bypass the AN/LT block */ 136294838Szbb#define AN_LT_WRAPPER_GEN_CFG_BYPASS_RX (1 << 4) 137294838Szbb/* bypass the AN/LT block */ 138294838Szbb#define AN_LT_WRAPPER_GEN_CFG_BYPASS_TX (1 << 5) 139294838Szbb 140294838Szbb/**** addr register ****/ 141294838Szbb/* Address value */ 142294838Szbb#define AN_LT_WRAPPER_AN_LT_ADDR_VAL_MASK 0x000007FF 143294838Szbb#define AN_LT_WRAPPER_AN_LT_ADDR_VAL_SHIFT 0 144294838Szbb 145294838Szbb/**** data register ****/ 146294838Szbb/* Data value */ 147294838Szbb#define AN_LT_WRAPPER_AN_LT_DATA_VAL_MASK 0x0000FFFF 148294838Szbb#define AN_LT_WRAPPER_AN_LT_DATA_VAL_SHIFT 0 149294838Szbb 150294838Szbb/**** ctrl register ****/ 151294838Szbb/* 152294838Szbb * Default Auto-Negotiation Enable. If ���1���, the auto-negotiation process will 153294838Szbb * start after reset de-assertion. The application can also start the 154294838Szbb * auto-negotiation process by writing the KXAN_CONTROL.an_enable bit with ���1���. 155294838Szbb * Important: This signal is OR'ed with the KXAN_CONTROL.an_enable bit. Hence, 156294838Szbb * when asserted (1) the application is unable to disable autonegotiation and 157294838Szbb * writing the an_enable bit has no effect. 158294838Szbb * Note: Even if enabled by this pin, the application must write the correct 159294838Szbb * abilities in the KXAN_ABILITY_1/2/3 registers within 60ms from reset 160294838Szbb * deassertion (break_link_timer). 161294838Szbb */ 162294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_AN_ENA (1 << 0) 163294838Szbb/* 164294838Szbb * If set to 1, the Arbitration State Machine reached the TRANSMIT_DISABLE 165294838Szbb * state. 166294838Szbb */ 167294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_AN_DIS_TIMER (1 << 1) 168294838Szbb 169294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS_KX (1 << 4) 170294838Szbb 171294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS_KX4 (1 << 5) 172294838Szbb 173294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS (1 << 6) 174294838Szbb/* 175294838Szbb * PHY LOS indication selection 176294838Szbb * 0 - Select input from the SerDes 177294838Szbb * 1 - Select register value from phy_los_in_def 178294838Szbb */ 179294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_SEL (1 << 8) 180294838Szbb/* PHY LOS default value */ 181294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_DEF (1 << 9) 182294838Szbb/* PHY LOS polarity */ 183294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_POL (1 << 10) 184294838Szbb/* 185294838Szbb * PHY LOS indication selection 186294838Szbb * 0 ��� select AN output 187294838Szbb * 1 - Select register value from phy_los_out_def 188294838Szbb * 2 - Select input from the SerDes 189294838Szbb * 3 ��� 0 190294838Szbb */ 191294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_SEL_MASK 0x00003000 192294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_SEL_SHIFT 12 193294838Szbb/* PHY LOS default value */ 194294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_DEF (1 << 14) 195294838Szbb/* PHY LOS polarity */ 196294838Szbb#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_POL (1 << 15) 197294838Szbb 198294838Szbb/**** status register ****/ 199294838Szbb/* Auto-Negotiation Done. If ���1���, the auto-negotiation process has completed. */ 200294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_AN_DONE (1 << 0) 201294838Szbb/* 202294838Szbb * If set to 1, auto-negotiation is enabled on the link. It represents the 203294838Szbb * enable control bit KXAN_CONTROL.an_enable. When set to 1, the signals 204294838Szbb * an_status/an_select are valid. 205294838Szbb */ 206294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_AN_VAL (1 << 1) 207294838Szbb/* 208294838Szbb * If set to 0, auto-negotiation is in progress, if set to 1, the Arbitration 209294838Szbb * State Machine reached the AN_GOOD_CHECK state (i.e. before autonegotiation is 210294838Szbb * done, but the link no longer is used to transfer DME pages). Stays asserted 211294838Szbb * also during AN_GOOD (autoneg done). 212294838Szbb */ 213294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_AN_STATUS (1 << 2) 214294838Szbb/* 215294838Szbb * Selected Technology. Becomes valid when an_status is 1. 216294838Szbb * The selection mode number (from 0 to 24) corresponds to the Technology 217294838Szbb * Ability (A0-A24) from the ability pages (see 4.3.2.3 page 13). The mode 218294838Szbb * selection is based on the matching technology abilities and priority. 219294838Szbb * A value of 31 is an invalid setting that indicates that no common technology 220294838Szbb * could be resolved. The application should then inspect the base page results 221294838Szbb * to determine if the link is operable or not. 222294838Szbb */ 223294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_AN_SELECT_MASK 0x000001F0 224294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_AN_SELECT_SHIFT 4 225294838Szbb/* 226294838Szbb * If set to 1, the Arbitration State Machine reached the TRANSMIT_DISABLE state 227294838Szbb */ 228294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_AN_TR_DIS_STATUS (1 << 16) 229294838Szbb/* 230294838Szbb * FEC Enable. Asserts when autonegotiation base page exchange identified both 231294838Szbb * link partners advertising FEC capability and at least one is requesting FEC. 232294838Szbb * The signal stays constant following base page exchange until autonegotiation 233294838Szbb * is disabled or restarted. 234294838Szbb * Note: the information can also be extracted from the base page exchange or 235294838Szbb * the BP_ETH_STATUS register. 236294838Szbb */ 237294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_FEC_ENA (1 << 17) 238294838Szbb/* 239294838Szbb * Link Training Frame Lock. If set to 1 the training frame delineation has been 240294838Szbb * acquired. 241294838Szbb */ 242294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_LT_LOCK (1 << 20) 243294838Szbb/* 244294838Szbb * If set to 0, link-training is in progress, if set to 1, the training is 245294838Szbb * completed and the PCS datapath has been enabled (phy_los_out no longer 246294838Szbb * gated). 247294838Szbb */ 248294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_LT_STATUS (1 << 21) 249294838Szbb/* 250294838Szbb * If set to 1, link-training is enabled on the link. It represents the enable 251294838Szbb * control bit PMD Control.taining enable. When set to 1, the signal lt_status 252294838Szbb * is valid 253294838Szbb */ 254294838Szbb#define AN_LT_WRAPPER_AN_LT_STATUS_LT_VAL (1 << 22) 255294838Szbb 256294838Szbb#ifdef __cplusplus 257294838Szbb} 258294838Szbb#endif 259294838Szbb 260294838Szbb#endif /* __AL_HAL_AN_LT_wrapper_REGS_H__ */ 261294838Szbb 262294838Szbb/** @} end of ... group */ 263294838Szbb 264294838Szbb 265