1294838Szbb/*- 2294838Szbb******************************************************************************* 3294838SzbbCopyright (C) 2015 Annapurna Labs Ltd. 4294838Szbb 5294838SzbbThis file may be licensed under the terms of the Annapurna Labs Commercial 6294838SzbbLicense Agreement. 7294838Szbb 8294838SzbbAlternatively, this file can be distributed under the terms of the GNU General 9294838SzbbPublic License V2 as published by the Free Software Foundation and can be 10294838Szbbfound at http://www.gnu.org/licenses/gpl-2.0.html 11294838Szbb 12294838SzbbAlternatively, redistribution and use in source and binary forms, with or 13294838Szbbwithout modification, are permitted provided that the following conditions are 14294838Szbbmet: 15294838Szbb 16294838Szbb * Redistributions of source code must retain the above copyright notice, 17294838Szbbthis list of conditions and the following disclaimer. 18294838Szbb 19294838Szbb * Redistributions in binary form must reproduce the above copyright 20294838Szbbnotice, this list of conditions and the following disclaimer in 21294838Szbbthe documentation and/or other materials provided with the 22294838Szbbdistribution. 23294838Szbb 24294838SzbbTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25294838SzbbANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26294838SzbbWARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27294838SzbbDISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28294838SzbbANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29294838Szbb(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30294838SzbbLOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31294838SzbbANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32294838Szbb(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33294838SzbbSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34294838Szbb 35294838Szbb*******************************************************************************/ 36294838Szbb 37294838Szbb/** 38294838Szbb * @defgroup group_udma_config UDMA Config 39294838Szbb * @ingroup group_udma_api 40294838Szbb * UDMA Config API 41294838Szbb * @{ 42294838Szbb * @file al_hal_udma_config.h 43294838Szbb * 44294838Szbb * @brief C Header file for the Universal DMA HAL driver for configuration APIs 45294838Szbb * 46294838Szbb */ 47294838Szbb 48294838Szbb#ifndef __AL_HAL_UDMA_CONFIG_H__ 49294838Szbb#define __AL_HAL_UDMA_CONFIG_H__ 50294838Szbb 51294838Szbb#include <al_hal_udma.h> 52294838Szbb 53294838Szbb 54294838Szbb/* *INDENT-OFF* */ 55294838Szbb#ifdef __cplusplus 56294838Szbbextern "C" { 57294838Szbb#endif 58294838Szbb/* *INDENT-ON* */ 59294838Szbb 60294838Szbb/** Scheduling mode */ 61294838Szbbenum al_udma_sch_mode { 62294838Szbb STRICT, /* Strict */ 63294838Szbb SRR, /* Simple Sound Rubin */ 64294838Szbb DWRR /* Deficit Weighted Round Rubin */ 65294838Szbb}; 66294838Szbb 67294838Szbb/** AXI configuration */ 68294838Szbbstruct al_udma_axi_conf { 69294838Szbb uint32_t axi_timeout; /* Timeout for AXI transactions */ 70294838Szbb uint8_t arb_promotion; /* arbitration promotion */ 71294838Szbb al_bool swap_8_bytes; /* enable 8 bytes swap instead of 4 bytes */ 72294838Szbb al_bool swap_s2m_data; 73294838Szbb al_bool swap_s2m_desc; 74294838Szbb al_bool swap_m2s_data; 75294838Szbb al_bool swap_m2s_desc; 76294838Szbb}; 77294838Szbb 78294838Szbb/** UDMA AXI M2S configuration */ 79294838Szbbstruct al_udma_axi_submaster { 80294838Szbb uint8_t id; /* AXI ID */ 81294838Szbb uint8_t cache_type; 82294838Szbb uint8_t burst; 83294838Szbb uint16_t used_ext; 84294838Szbb uint8_t bus_size; 85294838Szbb uint8_t qos; 86294838Szbb uint8_t prot; 87294838Szbb uint8_t max_beats; 88294838Szbb}; 89294838Szbb 90294838Szbb/** UDMA AXI M2S configuration */ 91294838Szbbstruct al_udma_m2s_axi_conf { 92294838Szbb struct al_udma_axi_submaster comp_write; 93294838Szbb struct al_udma_axi_submaster data_read; 94294838Szbb struct al_udma_axi_submaster desc_read; 95294838Szbb al_bool break_on_max_boundary; /* Data read break on max boundary */ 96294838Szbb uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */ 97294838Szbb uint8_t ostand_max_data_read; 98294838Szbb uint8_t ostand_max_desc_read; 99294838Szbb uint8_t ostand_max_comp_req; 100294838Szbb uint8_t ostand_max_comp_write; 101294838Szbb}; 102294838Szbb 103294838Szbb/** UDMA AXI S2M configuration */ 104294838Szbbstruct al_udma_s2m_axi_conf { 105294838Szbb struct al_udma_axi_submaster data_write; 106294838Szbb struct al_udma_axi_submaster desc_read; 107294838Szbb struct al_udma_axi_submaster comp_write; 108294838Szbb al_bool break_on_max_boundary; /* Data read break on max boundary */ 109294838Szbb uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */ 110294838Szbb uint8_t ostand_max_data_req; 111294838Szbb uint8_t ostand_max_data_write; 112294838Szbb uint8_t ostand_max_comp_req; 113294838Szbb uint8_t ostand_max_comp_write; 114294838Szbb uint8_t ostand_max_desc_read; 115294838Szbb uint8_t ack_fifo_depth; /* size of the stream application ack fifo */ 116294838Szbb}; 117294838Szbb 118294838Szbb/** M2S error logging */ 119294838Szbbstruct al_udma_err_log { 120294838Szbb uint32_t error_status; 121294838Szbb uint32_t header[4]; 122294838Szbb}; 123294838Szbb 124294838Szbb/** M2S max packet size configuration */ 125294838Szbbstruct al_udma_m2s_pkt_len_conf { 126294838Szbb uint32_t max_pkt_size; 127294838Szbb al_bool encode_64k_as_zero; 128294838Szbb}; 129294838Szbb 130294838Szbb/** M2S Descriptor Prefetch configuration */ 131294838Szbbstruct al_udma_m2s_desc_pref_conf { 132294838Szbb uint8_t desc_fifo_depth; 133294838Szbb enum al_udma_sch_mode sch_mode; /* Scheduling mode 134294838Szbb * (either strict or RR) */ 135294838Szbb 136294838Szbb uint8_t max_desc_per_packet; /* max number of descriptors to 137294838Szbb * prefetch */ 138294838Szbb /* in one burst (5b) */ 139294838Szbb uint8_t pref_thr; 140294838Szbb uint8_t min_burst_above_thr; /* min burst size when fifo above 141294838Szbb * pref_thr (4b) 142294838Szbb */ 143294838Szbb uint8_t min_burst_below_thr; /* min burst size when fifo below 144294838Szbb * pref_thr (4b) 145294838Szbb */ 146294838Szbb uint8_t max_pkt_limit; /* maximum number of packets in the data 147294838Szbb * read FIFO, defined based on header 148294838Szbb * FIFO size 149294838Szbb */ 150294838Szbb uint16_t data_fifo_depth; /* maximum number of data beats in the 151294838Szbb * data read FIFO, 152294838Szbb * defined based on header FIFO size 153294838Szbb */ 154294838Szbb}; 155294838Szbb 156294838Szbb/** S2M Descriptor Prefetch configuration */ 157294838Szbbstruct al_udma_s2m_desc_pref_conf { 158294838Szbb uint8_t desc_fifo_depth; 159294838Szbb enum al_udma_sch_mode sch_mode; /* Scheduling mode * 160294838Szbb * (either strict or RR) 161294838Szbb */ 162294838Szbb 163294838Szbb al_bool q_promotion; /* enable promotion */ 164294838Szbb al_bool force_promotion; /* force promotion */ 165294838Szbb al_bool en_pref_prediction; /* enable prefetch prediction */ 166294838Szbb uint8_t promotion_th; /* Threshold for queue promotion */ 167294838Szbb 168294838Szbb uint8_t pref_thr; 169294838Szbb uint8_t min_burst_above_thr; /* min burst size when fifo above 170294838Szbb * pref_thr (4b) 171294838Szbb */ 172294838Szbb uint8_t min_burst_below_thr; /* min burst size when fifo below 173294838Szbb * pref_thr (4b) 174294838Szbb */ 175294838Szbb uint8_t a_full_thr; /* almost full threshold */ 176294838Szbb}; 177294838Szbb 178294838Szbb/** S2M Data write configuration */ 179294838Szbbstruct al_udma_s2m_data_write_conf { 180294838Szbb uint16_t data_fifo_depth; /* maximum number of data beats in the 181294838Szbb * data write FIFO, defined based on 182294838Szbb * header FIFO size 183294838Szbb */ 184294838Szbb uint8_t max_pkt_limit; /* maximum number of packets in the 185294838Szbb * data write FIFO,defined based on 186294838Szbb * header FIFO size 187294838Szbb */ 188294838Szbb uint8_t fifo_margin; 189294838Szbb uint32_t desc_wait_timer; /* waiting time for the host to write 190294838Szbb * new descriptor to the queue 191294838Szbb * (for the current packet in process) 192294838Szbb */ 193294838Szbb uint32_t flags; /* bitwise of flags of s2m 194294838Szbb * data_cfg_2 register 195294838Szbb */ 196294838Szbb}; 197294838Szbb 198294838Szbb/** S2M Completion configuration */ 199294838Szbbstruct al_udma_s2m_completion_conf { 200294838Szbb uint8_t desc_size; /* Size of completion descriptor 201294838Szbb * in words 202294838Szbb */ 203294838Szbb al_bool cnt_words; /* Completion fifo in use counter: 204294838Szbb * AL_TRUE words, AL_FALS descriptors 205294838Szbb */ 206294838Szbb al_bool q_promotion; /* Enable promotion of the current 207294838Szbb * unack in progress */ 208294838Szbb /* in the completion write scheduler */ 209294838Szbb al_bool force_rr; /* force RR arbitration in the 210294838Szbb * scheduler 211294838Szbb */ 212294838Szbb // uint8_t ack_fifo_depth; /* size of the stream application ack fifo */ 213294838Szbb uint8_t q_free_min; /* minimum number of free completion 214294838Szbb * entries 215294838Szbb */ 216294838Szbb /* to qualify for promotion */ 217294838Szbb 218294838Szbb uint16_t comp_fifo_depth; /* Size of completion fifo in words */ 219294838Szbb uint16_t unack_fifo_depth; /* Size of unacked fifo in descs */ 220294838Szbb uint32_t timeout; /* Ack timout from stream interface */ 221294838Szbb}; 222294838Szbb 223294838Szbb/** M2S UDMA DWRR configuration */ 224294838Szbbstruct al_udma_m2s_dwrr_conf { 225294838Szbb al_bool enable_dwrr; 226294838Szbb uint8_t inc_factor; 227294838Szbb uint8_t weight; 228294838Szbb al_bool pkt_mode; 229294838Szbb uint32_t deficit_init_val; 230294838Szbb}; 231294838Szbb 232294838Szbb/** M2S DMA Rate Limitation mode */ 233294838Szbbstruct al_udma_m2s_rlimit_mode { 234294838Szbb al_bool pkt_mode_en; 235294838Szbb uint16_t short_cycle_sz; 236294838Szbb uint32_t token_init_val; 237294838Szbb}; 238294838Szbb 239294838Szbb/** M2S Stream/Q Rate Limitation */ 240294838Szbbstruct al_udma_m2s_rlimit_cfg { 241294838Szbb uint32_t max_burst_sz; /* maximum number of accumulated bytes in the 242294838Szbb * token counter 243294838Szbb */ 244294838Szbb uint16_t long_cycle_sz; /* number of short cycles between token fill */ 245294838Szbb uint32_t long_cycle; /* number of bits to add in each long cycle */ 246294838Szbb uint32_t short_cycle; /* number of bits to add in each cycle */ 247294838Szbb uint32_t mask; /* mask the different types of rate limiters */ 248294838Szbb}; 249294838Szbb 250294838Szbbenum al_udma_m2s_rlimit_action { 251294838Szbb AL_UDMA_STRM_RLIMIT_ENABLE, 252294838Szbb AL_UDMA_STRM_RLIMIT_PAUSE, 253294838Szbb AL_UDMA_STRM_RLIMIT_RESET 254294838Szbb}; 255294838Szbb 256294838Szbb/** M2S UDMA Q scheduling configuration */ 257294838Szbbstruct al_udma_m2s_q_dwrr_conf { 258294838Szbb uint32_t max_deficit_cnt_sz; /*maximum number of accumulated bytes 259294838Szbb * in the deficit counter 260294838Szbb */ 261294838Szbb al_bool strict; /* bypass DWRR */ 262294838Szbb uint8_t axi_qos; 263294838Szbb uint16_t q_qos; 264294838Szbb uint8_t weight; 265294838Szbb}; 266294838Szbb 267294838Szbb/** M2S UDMA / UDMA Q scheduling configuration */ 268294838Szbbstruct al_udma_m2s_sc { 269294838Szbb enum al_udma_sch_mode sch_mode; /* Scheduling Mode */ 270294838Szbb struct al_udma_m2s_dwrr_conf dwrr; /* DWRR configuration */ 271294838Szbb}; 272294838Szbb 273294838Szbb/** UDMA / UDMA Q rate limitation configuration */ 274294838Szbbstruct al_udma_m2s_rlimit { 275294838Szbb struct al_udma_m2s_rlimit_mode rlimit_mode; 276294838Szbb /* rate limitation enablers */ 277294838Szbb#if 0 278294838Szbb struct al_udma_tkn_bkt_conf token_bkt; /* Token Bucket configuration */ 279294838Szbb#endif 280294838Szbb}; 281294838Szbb 282294838Szbb/** UDMA Data read configuration */ 283294838Szbbstruct al_udma_m2s_data_rd_conf { 284294838Szbb uint8_t max_rd_d_beats; /* max burst size for reading data 285294838Szbb * (in AXI beats-128b) (5b) 286294838Szbb */ 287294838Szbb uint8_t max_rd_d_out_req; /* max number of outstanding data 288294838Szbb * read requests (6b) 289294838Szbb */ 290294838Szbb uint16_t max_rd_d_out_beats; /* max num. of data read beats (10b) */ 291294838Szbb}; 292294838Szbb 293294838Szbb/** M2S UDMA completion and application timeouts */ 294294838Szbbstruct al_udma_m2s_comp_timeouts { 295294838Szbb enum al_udma_sch_mode sch_mode; /* Scheduling mode 296294838Szbb * (either strict or RR) 297294838Szbb */ 298294838Szbb al_bool enable_q_promotion; 299294838Szbb uint8_t unack_fifo_depth; /* unacked desc fifo size */ 300294838Szbb uint8_t comp_fifo_depth; /* desc fifo size */ 301294838Szbb uint32_t coal_timeout; /* (24b) */ 302294838Szbb uint32_t app_timeout; /* (24b) */ 303294838Szbb}; 304294838Szbb 305294838Szbb/** S2M UDMA per queue completion configuration */ 306294838Szbbstruct al_udma_s2m_q_comp_conf { 307294838Szbb al_bool dis_comp_coal; /* disable completion coalescing */ 308294838Szbb al_bool en_comp_ring_update; /* enable writing completion descs */ 309294838Szbb uint32_t comp_timer; /* completion coalescing timer */ 310294838Szbb al_bool en_hdr_split; /* enable header split */ 311294838Szbb al_bool force_hdr_split; /* force header split */ 312294838Szbb uint16_t hdr_split_size; /* size used for the header split */ 313294838Szbb uint8_t q_qos; /* queue QoS */ 314294838Szbb}; 315294838Szbb 316294838Szbb/** UDMA per queue VMID control configuration */ 317294838Szbbstruct al_udma_gen_vmid_q_conf { 318294838Szbb /* Enable usage of the VMID per queue according to 'vmid' */ 319294838Szbb al_bool queue_en; 320294838Szbb 321294838Szbb /* Enable usage of the VMID from the descriptor buffer address 63:48 */ 322294838Szbb al_bool desc_en; 323294838Szbb 324294838Szbb /* VMID to be applied when 'queue_en' is asserted */ 325294838Szbb uint16_t vmid; 326294838Szbb 327294838Szbb /* VMADDR to be applied to msbs when 'desc_en' is asserted. 328294838Szbb * Relevant for revisions >= AL_UDMA_REV_ID_REV2 */ 329294838Szbb uint16_t vmaddr; 330294838Szbb}; 331294838Szbb 332294838Szbb/** UDMA VMID control configuration */ 333294838Szbbstruct al_udma_gen_vmid_conf { 334294838Szbb /* TX queue configuration */ 335294838Szbb struct al_udma_gen_vmid_q_conf tx_q_conf[DMA_MAX_Q]; 336294838Szbb 337294838Szbb /* RX queue configuration */ 338294838Szbb struct al_udma_gen_vmid_q_conf rx_q_conf[DMA_MAX_Q]; 339294838Szbb}; 340294838Szbb 341294838Szbb/** UDMA VMID MSIX control configuration */ 342294838Szbbstruct al_udma_gen_vmid_msix_conf { 343294838Szbb /* Enable write to all VMID_n registers in the MSI-X Controller */ 344294838Szbb al_bool access_en; 345294838Szbb 346294838Szbb /* use VMID_n [7:0] from MSI-X Controller for MSI-X message */ 347294838Szbb al_bool sel; 348294838Szbb}; 349294838Szbb 350294838Szbb/** UDMA per Tx queue advanced VMID control configuration */ 351294838Szbbstruct al_udma_gen_vmid_advanced_tx_q_conf { 352294838Szbb /********************************************************************** 353294838Szbb * Tx Data VMID 354294838Szbb **********************************************************************/ 355294838Szbb /* Tx data VMID enable */ 356294838Szbb al_bool tx_q_data_vmid_en; 357294838Szbb 358294838Szbb /* 359294838Szbb * For Tx data reads, replacement bits for the original address. 360294838Szbb * The number of bits replaced is determined according to 361294838Szbb * 'tx_q_addr_hi_sel' 362294838Szbb */ 363294838Szbb unsigned int tx_q_addr_hi; 364294838Szbb 365294838Szbb /* 366294838Szbb * For Tx data reads, 6 bits serving the number of bits taken from the 367294838Szbb * extra register on account of bits coming from the original address 368294838Szbb * field. 369294838Szbb * When 'tx_q_addr_hi_sel'=32 all of 'tx_q_addr_hi' will be taken. 370294838Szbb * When 'tx_q_addr_hi_sel'=0 none of it will be taken, and when any 371294838Szbb * value in between, it will start from the MSB bit and sweep down as 372294838Szbb * many bits as needed. For example if 'tx_q_addr_hi_sel'=8, the final 373294838Szbb * address [63:56] will carry 'tx_q_addr_hi'[31:24] while [55:32] will 374294838Szbb * carry the original buffer address[55:32]. 375294838Szbb */ 376294838Szbb unsigned int tx_q_addr_hi_sel; 377294838Szbb 378294838Szbb /* 379294838Szbb * Tx data read VMID 380294838Szbb * Masked per bit with 'tx_q_data_vmid_mask' 381294838Szbb */ 382294838Szbb unsigned int tx_q_data_vmid; 383294838Szbb 384294838Szbb /* 385294838Szbb * Tx data read VMID mask 386294838Szbb * Each '1' selects from the buffer address, each '0' selects from 387294838Szbb * 'tx_q_data_vmid' 388294838Szbb */ 389294838Szbb unsigned int tx_q_data_vmid_mask; 390294838Szbb 391294838Szbb /********************************************************************** 392294838Szbb * Tx prefetch VMID 393294838Szbb **********************************************************************/ 394294838Szbb /* Tx prefetch VMID enable */ 395294838Szbb al_bool tx_q_prefetch_vmid_en; 396294838Szbb 397294838Szbb /* Tx prefetch VMID */ 398294838Szbb unsigned int tx_q_prefetch_vmid; 399294838Szbb 400294838Szbb /********************************************************************** 401294838Szbb * Tx completion VMID 402294838Szbb **********************************************************************/ 403294838Szbb /* Tx completion VMID enable */ 404294838Szbb al_bool tx_q_compl_vmid_en; 405294838Szbb 406294838Szbb /* Tx completion VMID */ 407294838Szbb unsigned int tx_q_compl_vmid; 408294838Szbb}; 409294838Szbb 410294838Szbb/** UDMA per Rx queue advanced VMID control configuration */ 411294838Szbbstruct al_udma_gen_vmid_advanced_rx_q_conf { 412294838Szbb /********************************************************************** 413294838Szbb * Rx Data VMID 414294838Szbb **********************************************************************/ 415294838Szbb /* Rx data VMID enable */ 416294838Szbb al_bool rx_q_data_vmid_en; 417294838Szbb 418294838Szbb /* 419294838Szbb * For Rx data writes, replacement bits for the original address. 420294838Szbb * The number of bits replaced is determined according to 421294838Szbb * 'rx_q_addr_hi_sel' 422294838Szbb */ 423294838Szbb unsigned int rx_q_addr_hi; 424294838Szbb 425294838Szbb /* 426294838Szbb * For Rx data writes, 6 bits serving the number of bits taken from the 427294838Szbb * extra register on account of bits coming from the original address 428294838Szbb * field. 429294838Szbb */ 430294838Szbb unsigned int rx_q_addr_hi_sel; 431294838Szbb 432294838Szbb /* 433294838Szbb * Rx data write VMID 434294838Szbb * Masked per bit with 'rx_q_data_vmid_mask' 435294838Szbb */ 436294838Szbb unsigned int rx_q_data_vmid; 437294838Szbb 438294838Szbb /* Rx data write VMID mask */ 439294838Szbb unsigned int rx_q_data_vmid_mask; 440294838Szbb 441294838Szbb /********************************************************************** 442294838Szbb * Rx Data Buffer 2 VMID 443294838Szbb **********************************************************************/ 444294838Szbb /* Rx data buff2 VMID enable */ 445294838Szbb al_bool rx_q_data_buff2_vmid_en; 446294838Szbb 447294838Szbb /* 448294838Szbb * For Rx data buff2 writes, replacement bits for the original address. 449294838Szbb * The number of bits replaced is determined according to 450294838Szbb * 'rx_q_data_buff2_addr_hi_sel' 451294838Szbb */ 452294838Szbb unsigned int rx_q_data_buff2_addr_hi; 453294838Szbb 454294838Szbb /* 455294838Szbb * For Rx data buff2 writes, 6 bits serving the number of bits taken 456294838Szbb * from the extra register on account of bits coming from the original 457294838Szbb * address field. 458294838Szbb */ 459294838Szbb unsigned int rx_q_data_buff2_addr_hi_sel; 460294838Szbb 461294838Szbb /* 462294838Szbb * Rx data buff2 write VMID 463294838Szbb * Masked per bit with 'rx_q_data_buff2_mask' 464294838Szbb */ 465294838Szbb unsigned int rx_q_data_buff2_vmid; 466294838Szbb 467294838Szbb /* Rx data buff2 write VMID mask */ 468294838Szbb unsigned int rx_q_data_buff2_mask; 469294838Szbb 470294838Szbb /********************************************************************** 471294838Szbb * Rx DDP VMID 472294838Szbb **********************************************************************/ 473294838Szbb /* Rx DDP write VMID enable */ 474294838Szbb al_bool rx_q_ddp_vmid_en; 475294838Szbb 476294838Szbb /* 477294838Szbb * For Rx DDP writes, replacement bits for the original address. 478294838Szbb * The number of bits replaced is determined according to 479294838Szbb * 'rx_q_ddp_addr_hi_sel' 480294838Szbb */ 481294838Szbb unsigned int rx_q_ddp_addr_hi; 482294838Szbb 483294838Szbb /* 484294838Szbb * For Rx DDP writes, 6 bits serving the number of bits taken from the 485294838Szbb * extra register on account of bits coming from the original address 486294838Szbb * field. 487294838Szbb */ 488294838Szbb unsigned int rx_q_ddp_addr_hi_sel; 489294838Szbb 490294838Szbb /* 491294838Szbb * Rx DDP write VMID 492294838Szbb * Masked per bit with 'rx_q_ddp_mask' 493294838Szbb */ 494294838Szbb unsigned int rx_q_ddp_vmid; 495294838Szbb 496294838Szbb /* Rx DDP write VMID mask */ 497294838Szbb unsigned int rx_q_ddp_mask; 498294838Szbb 499294838Szbb /********************************************************************** 500294838Szbb * Rx prefetch VMID 501294838Szbb **********************************************************************/ 502294838Szbb /* Rx prefetch VMID enable */ 503294838Szbb al_bool rx_q_prefetch_vmid_en; 504294838Szbb 505294838Szbb /* Rx prefetch VMID */ 506294838Szbb unsigned int rx_q_prefetch_vmid; 507294838Szbb 508294838Szbb /********************************************************************** 509294838Szbb * Rx completion VMID 510294838Szbb **********************************************************************/ 511294838Szbb /* Rx completion VMID enable */ 512294838Szbb al_bool rx_q_compl_vmid_en; 513294838Szbb 514294838Szbb /* Rx completion VMID */ 515294838Szbb unsigned int rx_q_compl_vmid; 516294838Szbb}; 517294838Szbb 518294838Szbb/** 519294838Szbb * Header split, buffer 2 per queue configuration 520294838Szbb * When header split is enabled, Buffer_2 is used as an address for the header 521294838Szbb * data. Buffer_2 is defined as 32-bits in the RX descriptor and it is defined 522294838Szbb * that the MSB ([63:32]) of Buffer_1 is used as address [63:32] for the header 523294838Szbb * address. 524294838Szbb */ 525294838Szbbstruct al_udma_gen_hdr_split_buff2_q_conf { 526294838Szbb /* 527294838Szbb * MSB of the 64-bit address (bits [63:32]) that can be used for header 528294838Szbb * split for this queue 529294838Szbb */ 530294838Szbb unsigned int addr_msb; 531294838Szbb 532294838Szbb /* 533294838Szbb * Determine how to select the MSB (bits [63:32]) of the address when 534294838Szbb * header split is enabled (4 bits, one per byte) 535294838Szbb * - Bits [3:0]: 536294838Szbb * [0] ��� selector for bits [39:32] 537294838Szbb * [1] ��� selector for bits [47:40] 538294838Szbb * [2] ��� selector for bits [55:48] 539294838Szbb * [3] ��� selector for bits [63:55] 540294838Szbb * - Bit value: 541294838Szbb * 0 ��� Use Buffer_1 (legacy operation) 542294838Szbb * 1 ��� Use the queue configuration 'addr_msb' 543294838Szbb */ 544294838Szbb unsigned int add_msb_sel; 545294838Szbb}; 546294838Szbb 547294838Szbb/* Report Error - to be used for abort */ 548294838Szbbvoid al_udma_err_report(struct al_udma *udma); 549294838Szbb 550294838Szbb/* Statistics - TBD */ 551294838Szbbvoid al_udma_stats_get(struct al_udma *udma); 552294838Szbb 553294838Szbb/* Misc configurations */ 554294838Szbb/* Configure AXI configuration */ 555294838Szbbint al_udma_axi_set(struct udma_gen_axi *axi_regs, 556294838Szbb struct al_udma_axi_conf *axi); 557294838Szbb 558294838Szbb/* Configure UDMA AXI M2S configuration */ 559294838Szbbint al_udma_m2s_axi_set(struct al_udma *udma, 560294838Szbb struct al_udma_m2s_axi_conf *axi_m2s); 561294838Szbb 562294838Szbb/* Configure UDMA AXI S2M configuration */ 563294838Szbbint al_udma_s2m_axi_set(struct al_udma *udma, 564294838Szbb struct al_udma_s2m_axi_conf *axi_s2m); 565294838Szbb 566294838Szbb/* Configure M2S packet len */ 567294838Szbbint al_udma_m2s_packet_size_cfg_set(struct al_udma *udma, 568294838Szbb struct al_udma_m2s_pkt_len_conf *conf); 569294838Szbb 570294838Szbb/* Configure M2S UDMA descriptor prefetch */ 571294838Szbbint al_udma_m2s_pref_set(struct al_udma *udma, 572294838Szbb struct al_udma_m2s_desc_pref_conf *conf); 573294838Szbbint al_udma_m2s_pref_get(struct al_udma *udma, 574294838Szbb struct al_udma_m2s_desc_pref_conf *conf); 575294838Szbb 576294838Szbb/* set m2s packet's max descriptors (including meta descriptors) */ 577294838Szbb#define AL_UDMA_M2S_MAX_ALLOWED_DESCS_PER_PACKET 31 578294838Szbbint al_udma_m2s_max_descs_set(struct al_udma *udma, uint8_t max_descs); 579294838Szbb 580294838Szbb/* set s2m packets' max descriptors */ 581294838Szbb#define AL_UDMA_S2M_MAX_ALLOWED_DESCS_PER_PACKET 31 582294838Szbbint al_udma_s2m_max_descs_set(struct al_udma *udma, uint8_t max_descs); 583294838Szbb 584294838Szbb 585294838Szbb/* Configure S2M UDMA descriptor prefetch */ 586294838Szbbint al_udma_s2m_pref_set(struct al_udma *udma, 587294838Szbb struct al_udma_s2m_desc_pref_conf *conf); 588294838Szbbint al_udma_m2s_pref_get(struct al_udma *udma, 589294838Szbb struct al_udma_m2s_desc_pref_conf *conf); 590294838Szbb 591294838Szbb/* Configure S2M UDMA data write */ 592294838Szbbint al_udma_s2m_data_write_set(struct al_udma *udma, 593294838Szbb struct al_udma_s2m_data_write_conf *conf); 594294838Szbb 595294838Szbb/* Configure the s2m full line write feature */ 596294838Szbbint al_udma_s2m_full_line_write_set(struct al_udma *umda, al_bool enable); 597294838Szbb 598294838Szbb/* Configure S2M UDMA completion */ 599294838Szbbint al_udma_s2m_completion_set(struct al_udma *udma, 600294838Szbb struct al_udma_s2m_completion_conf *conf); 601294838Szbb 602294838Szbb/* Configure the M2S UDMA scheduling mode */ 603294838Szbbint al_udma_m2s_sc_set(struct al_udma *udma, 604294838Szbb struct al_udma_m2s_dwrr_conf *sched); 605294838Szbb 606294838Szbb/* Configure the M2S UDMA rate limitation */ 607294838Szbbint al_udma_m2s_rlimit_set(struct al_udma *udma, 608294838Szbb struct al_udma_m2s_rlimit_mode *mode); 609294838Szbbint al_udma_m2s_rlimit_reset(struct al_udma *udma); 610294838Szbb 611294838Szbb/* Configure the M2S Stream rate limitation */ 612294838Szbbint al_udma_m2s_strm_rlimit_set(struct al_udma *udma, 613294838Szbb struct al_udma_m2s_rlimit_cfg *conf); 614294838Szbbint al_udma_m2s_strm_rlimit_act(struct al_udma *udma, 615294838Szbb enum al_udma_m2s_rlimit_action act); 616294838Szbb 617294838Szbb/* Configure the M2S UDMA Q rate limitation */ 618294838Szbbint al_udma_m2s_q_rlimit_set(struct al_udma_q *udma_q, 619294838Szbb struct al_udma_m2s_rlimit_cfg *conf); 620294838Szbbint al_udma_m2s_q_rlimit_act(struct al_udma_q *udma_q, 621294838Szbb enum al_udma_m2s_rlimit_action act); 622294838Szbb 623294838Szbb/* Configure the M2S UDMA Q scheduling mode */ 624294838Szbbint al_udma_m2s_q_sc_set(struct al_udma_q *udma_q, 625294838Szbb struct al_udma_m2s_q_dwrr_conf *conf); 626294838Szbbint al_udma_m2s_q_sc_pause(struct al_udma_q *udma_q, al_bool set); 627294838Szbbint al_udma_m2s_q_sc_reset(struct al_udma_q *udma_q); 628294838Szbb 629294838Szbb/* M2S UDMA completion and application timeouts */ 630294838Szbbint al_udma_m2s_comp_timeouts_set(struct al_udma *udma, 631294838Szbb struct al_udma_m2s_comp_timeouts *conf); 632294838Szbbint al_udma_m2s_comp_timeouts_get(struct al_udma *udma, 633294838Szbb struct al_udma_m2s_comp_timeouts *conf); 634294838Szbb 635294838Szbb/* UDMA get revision */ 636294838Szbbstatic INLINE unsigned int al_udma_get_revision(struct unit_regs __iomem *unit_regs) 637294838Szbb{ 638294838Szbb return (al_reg_read32(&unit_regs->gen.dma_misc.revision) 639294838Szbb & UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK) >> 640294838Szbb UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT; 641294838Szbb} 642294838Szbb 643294838Szbb/** 644294838Szbb * S2M UDMA Configure the expected behavior of Rx/S2M UDMA when there are no Rx Descriptors. 645294838Szbb * 646294838Szbb * @param udma 647294838Szbb * @param drop_packet when set to true, the UDMA will drop packet. 648294838Szbb * @param gen_interrupt when set to true, the UDMA will generate 649294838Szbb * no_desc_hint interrupt when a packet received and the UDMA 650294838Szbb * doesn't find enough free descriptors for it. 651294838Szbb * @param wait_for_desc_timeout timeout in SB cycles to wait for new 652294838Szbb * descriptors before dropping the packets. 653294838Szbb * Notes: 654294838Szbb * - The hint interrupt is raised immediately without waiting 655294838Szbb * for new descs. 656294838Szbb * - value 0 means wait for ever. 657294838Szbb * 658294838Szbb * Notes: 659294838Szbb * - When get_interrupt is set, the API won't program the iofic to unmask this 660294838Szbb * interrupt, in this case the callee should take care for doing that unmask 661294838Szbb * using the al_udma_iofic_config() API. 662294838Szbb * 663294838Szbb * - The hardware's default configuration is: no drop packet, generate hint 664294838Szbb * interrupt. 665294838Szbb * - This API must be called once and before enabling the UDMA 666294838Szbb * 667294838Szbb * @return 0 if no error found. 668294838Szbb */ 669294838Szbbint al_udma_s2m_no_desc_cfg_set(struct al_udma *udma, al_bool drop_packet, al_bool gen_interrupt, uint32_t wait_for_desc_timeout); 670294838Szbb 671294838Szbb/** 672294838Szbb * S2M UDMA configure a queue's completion update 673294838Szbb * 674294838Szbb * @param q_udma 675294838Szbb * @param enable set to true to enable completion update 676294838Szbb * 677294838Szbb * completion update better be disabled for tx queues as those descriptors 678294838Szbb * doesn't carry useful information, thus disabling it saves DMA accesses. 679294838Szbb * 680294838Szbb * @return 0 if no error found. 681294838Szbb */ 682294838Szbbint al_udma_s2m_q_compl_updade_config(struct al_udma_q *udma_q, al_bool enable); 683294838Szbb 684294838Szbb/** 685294838Szbb * S2M UDMA configure a queue's completion descriptors coalescing 686294838Szbb * 687294838Szbb * @param q_udma 688294838Szbb * @param enable set to true to enable completion coalescing 689294838Szbb * @param coal_timeout in South Bridge cycles. 690294838Szbb * 691294838Szbb * @return 0 if no error found. 692294838Szbb */ 693294838Szbbint al_udma_s2m_q_compl_coal_config(struct al_udma_q *udma_q, al_bool enable, uint32_t coal_timeout); 694294838Szbb 695294838Szbb/** 696294838Szbb * S2M UDMA configure completion descriptors write burst parameters 697294838Szbb * 698294838Szbb * @param udma 699294838Szbb * @param burst_size completion descriptors write burst size in bytes. 700294838Szbb * 701294838Szbb * @return 0 if no error found. 702294838Szbb */int al_udma_s2m_compl_desc_burst_config(struct al_udma *udma, uint16_t 703294838Szbb burst_size); 704294838Szbb 705294838Szbb/** 706294838Szbb * S2M UDMA configure a queue's completion header split 707294838Szbb * 708294838Szbb * @param q_udma 709294838Szbb * @param enable set to true to enable completion header split 710294838Szbb * @param force_hdr_split the header split length will be taken from the queue configuration 711294838Szbb * @param hdr_len header split length. 712294838Szbb * 713294838Szbb * @return 0 if no error found. 714294838Szbb */ 715294838Szbbint al_udma_s2m_q_compl_hdr_split_config(struct al_udma_q *udma_q, 716294838Szbb al_bool enable, 717294838Szbb al_bool force_hdr_split, 718294838Szbb uint32_t hdr_len); 719294838Szbb 720294838Szbb/* S2M UDMA per queue completion configuration */ 721294838Szbbint al_udma_s2m_q_comp_set(struct al_udma_q *udma_q, 722294838Szbb struct al_udma_s2m_q_comp_conf *conf); 723294838Szbb 724294838Szbb/** UDMA VMID control configuration */ 725294838Szbbvoid al_udma_gen_vmid_conf_set( 726294838Szbb struct unit_regs __iomem *unit_regs, 727294838Szbb struct al_udma_gen_vmid_conf *conf); 728294838Szbb 729294838Szbb/** UDMA VMID MSIX control configuration */ 730294838Szbbvoid al_udma_gen_vmid_msix_conf_set( 731294838Szbb struct unit_regs __iomem *unit_regs, 732294838Szbb struct al_udma_gen_vmid_msix_conf *conf); 733294838Szbb 734294838Szbb/** UDMA VMID control advanced Tx queue configuration */ 735294838Szbbvoid al_udma_gen_vmid_advanced_tx_q_conf( 736294838Szbb struct al_udma_q *q, 737294838Szbb struct al_udma_gen_vmid_advanced_tx_q_conf *conf); 738294838Szbb 739294838Szbb/** UDMA VMID control advanced Rx queue configuration */ 740294838Szbbvoid al_udma_gen_vmid_advanced_rx_q_conf( 741294838Szbb struct al_udma_q *q, 742294838Szbb struct al_udma_gen_vmid_advanced_rx_q_conf *conf); 743294838Szbb 744294838Szbb/** UDMA header split buffer 2 Rx queue configuration */ 745294838Szbbvoid al_udma_gen_hdr_split_buff2_rx_q_conf( 746294838Szbb struct al_udma_q *q, 747294838Szbb struct al_udma_gen_hdr_split_buff2_q_conf *conf); 748294838Szbb 749294838Szbb/* *INDENT-OFF* */ 750294838Szbb#ifdef __cplusplus 751294838Szbb} 752294838Szbb#endif 753294838Szbb/* *INDENT-ON* */ 754294838Szbb/** @} end of UDMA config group */ 755294838Szbb#endif /* __AL_HAL_UDMA_CONFIG_H__ */ 756