al_hal_pcie_w_reg.h revision 285431
1/*- 2******************************************************************************** 3Copyright (C) 2015 Annapurna Labs Ltd. 4 5This file may be licensed under the terms of the Annapurna Labs Commercial 6License Agreement. 7 8Alternatively, this file can be distributed under the terms of the GNU General 9Public License V2 as published by the Free Software Foundation and can be 10found at http://www.gnu.org/licenses/gpl-2.0.html 11 12Alternatively, redistribution and use in source and binary forms, with or 13without modification, are permitted provided that the following conditions are 14met: 15 16 * Redistributions of source code must retain the above copyright notice, 17this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20notice, this list of conditions and the following disclaimer in 21the documentation and/or other materials provided with the 22distribution. 23 24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35*******************************************************************************/ 36 37 38#ifndef __AL_HAL_PCIE_W_REG_H__ 39#define __AL_HAL_PCIE_W_REG_H__ 40 41#ifdef __cplusplus 42extern "C" { 43#endif 44/* 45* Unit Registers 46*/ 47 48 49 50struct al_pcie_rev1_w_global_ctrl { 51 /* [0x0] */ 52 uint32_t port_init; 53 /* [0x4] */ 54 uint32_t port_status; 55 /* [0x8] */ 56 uint32_t pm_control; 57 uint32_t rsrvd_0; 58 /* [0x10] */ 59 uint32_t events_gen; 60 uint32_t rsrvd[3]; 61}; 62struct al_pcie_rev2_w_global_ctrl { 63 /* [0x0] */ 64 uint32_t port_init; 65 /* [0x4] */ 66 uint32_t port_status; 67 /* [0x8] */ 68 uint32_t pm_control; 69 uint32_t rsrvd_0; 70 /* [0x10] */ 71 uint32_t events_gen; 72 /* [0x14] */ 73 uint32_t pended_corr_err_sts_int; 74 /* [0x18] */ 75 uint32_t pended_uncorr_err_sts_int; 76 /* [0x1c] */ 77 uint32_t sris_kp_counter_value; 78}; 79struct al_pcie_rev3_w_global_ctrl { 80 /* [0x0] */ 81 uint32_t port_init; 82 /* [0x4] */ 83 uint32_t port_status; 84 /* [0x8] */ 85 uint32_t pm_control; 86 /* [0xc] */ 87 uint32_t pended_corr_err_sts_int; 88 /* [0x10] */ 89 uint32_t pended_uncorr_err_sts_int; 90 /* [0x14] */ 91 uint32_t sris_kp_counter_value; 92 uint32_t rsrvd[2]; 93}; 94 95struct al_pcie_rev3_w_events_gen_per_func { 96 /* [0x0] */ 97 uint32_t events_gen; 98}; 99struct al_pcie_rev3_w_pm_state_per_func { 100 /* [0x0] */ 101 uint32_t pm_state_per_func; 102}; 103struct al_pcie_rev3_w_cfg_bars_ovrd { 104 /* [0x0] */ 105 uint32_t bar0_mask_lsb; 106 /* [0x4] */ 107 uint32_t bar0_mask_msb; 108 /* [0x8] */ 109 uint32_t bar0_limit_lsb; 110 /* [0xc] */ 111 uint32_t bar0_limit_msb; 112 /* [0x10] */ 113 uint32_t bar0_start_lsb; 114 /* [0x14] */ 115 uint32_t bar0_start_msb; 116 /* [0x18] */ 117 uint32_t bar0_ctrl; 118 /* [0x1c] */ 119 uint32_t bar1_mask_lsb; 120 /* [0x20] */ 121 uint32_t bar1_mask_msb; 122 /* [0x24] */ 123 uint32_t bar1_limit_lsb; 124 /* [0x28] */ 125 uint32_t bar1_limit_msb; 126 /* [0x2c] */ 127 uint32_t bar1_start_lsb; 128 /* [0x30] */ 129 uint32_t bar1_start_msb; 130 /* [0x34] */ 131 uint32_t bar1_ctrl; 132 /* [0x38] */ 133 uint32_t bar2_mask_lsb; 134 /* [0x3c] */ 135 uint32_t bar2_mask_msb; 136 /* [0x40] */ 137 uint32_t bar2_limit_lsb; 138 /* [0x44] */ 139 uint32_t bar2_limit_msb; 140 /* [0x48] */ 141 uint32_t bar2_start_lsb; 142 /* [0x4c] */ 143 uint32_t bar2_start_msb; 144 /* [0x50] */ 145 uint32_t bar2_ctrl; 146 /* [0x54] */ 147 uint32_t bar3_mask_lsb; 148 /* [0x58] */ 149 uint32_t bar3_mask_msb; 150 /* [0x5c] */ 151 uint32_t bar3_limit_lsb; 152 /* [0x60] */ 153 uint32_t bar3_limit_msb; 154 /* [0x64] */ 155 uint32_t bar3_start_lsb; 156 /* [0x68] */ 157 uint32_t bar3_start_msb; 158 /* [0x6c] */ 159 uint32_t bar3_ctrl; 160 /* [0x70] */ 161 uint32_t bar4_mask_lsb; 162 /* [0x74] */ 163 uint32_t bar4_mask_msb; 164 /* [0x78] */ 165 uint32_t bar4_limit_lsb; 166 /* [0x7c] */ 167 uint32_t bar4_limit_msb; 168 /* [0x80] */ 169 uint32_t bar4_start_lsb; 170 /* [0x84] */ 171 uint32_t bar4_start_msb; 172 /* [0x88] */ 173 uint32_t bar4_ctrl; 174 /* [0x8c] */ 175 uint32_t bar5_mask_lsb; 176 /* [0x90] */ 177 uint32_t bar5_mask_msb; 178 /* [0x94] */ 179 uint32_t bar5_limit_lsb; 180 /* [0x98] */ 181 uint32_t bar5_limit_msb; 182 /* [0x9c] */ 183 uint32_t bar5_start_lsb; 184 /* [0xa0] */ 185 uint32_t bar5_start_msb; 186 /* [0xa4] */ 187 uint32_t bar5_ctrl; 188 uint32_t rsrvd[2]; 189}; 190 191struct al_pcie_revx_w_debug { 192 /* [0x0] */ 193 uint32_t info_0; 194 /* [0x4] */ 195 uint32_t info_1; 196 /* [0x8] */ 197 uint32_t info_2; 198 /* [0xc] */ 199 uint32_t info_3; 200}; 201struct al_pcie_revx_w_ob_ven_msg { 202 /* [0x0] */ 203 uint32_t control; 204 /* [0x4] */ 205 uint32_t param_1; 206 /* [0x8] */ 207 uint32_t param_2; 208 /* [0xc] */ 209 uint32_t data_high; 210 uint32_t rsrvd_0; 211 /* [0x14] */ 212 uint32_t data_low; 213}; 214struct al_pcie_revx_w_ap_user_send_msg { 215 /* [0x0] */ 216 uint32_t req_info; 217 /* [0x4] */ 218 uint32_t ack_info; 219}; 220struct al_pcie_revx_w_link_down { 221 /* [0x0] */ 222 uint32_t reset_delay; 223 /* [0x4] */ 224 uint32_t reset_extend_rsrvd; 225}; 226struct al_pcie_revx_w_cntl_gen { 227 /* [0x0] */ 228 uint32_t features; 229}; 230struct al_pcie_revx_w_parity { 231 /* [0x0] */ 232 uint32_t en_core; 233 /* [0x4] */ 234 uint32_t status_core; 235}; 236struct al_pcie_revx_w_last_wr { 237 /* [0x0] */ 238 uint32_t cfg_addr; 239}; 240struct al_pcie_rev1_2_w_atu { 241 /* [0x0] */ 242 uint32_t in_mask_pair[6]; 243 /* [0x18] */ 244 uint32_t out_mask_pair[6]; 245}; 246struct al_pcie_rev3_w_atu { 247 /* [0x0] */ 248 uint32_t in_mask_pair[12]; 249 /* [0x30] */ 250 uint32_t out_mask_pair[8]; 251 /* [0x50] */ 252 uint32_t reg_out_mask; 253 uint32_t rsrvd[11]; 254}; 255struct al_pcie_rev3_w_cfg_func_ext { 256 /* [0x0] */ 257 uint32_t cfg; 258}; 259struct al_pcie_rev3_w_app_hdr_interface_send { 260 /* [0x0] */ 261 uint32_t app_hdr_31_0; 262 /* [0x4] */ 263 uint32_t app_hdr_63_32; 264 /* [0x8] */ 265 uint32_t app_hdr_95_64; 266 /* [0xc] */ 267 uint32_t app_hdr_127_96; 268 /* [0x10] */ 269 uint32_t app_err_bus; 270 /* [0x14] */ 271 uint32_t app_func_num_advisory; 272 /* [0x18] */ 273 uint32_t app_hdr_cmd; 274}; 275struct al_pcie_rev3_w_diag_command { 276 /* [0x0] */ 277 uint32_t diag_ctrl; 278}; 279struct al_pcie_rev1_w_soc_int { 280 /* [0x0] */ 281 uint32_t status_0; 282 /* [0x4] */ 283 uint32_t status_1; 284 /* [0x8] */ 285 uint32_t status_2; 286 /* [0xc] */ 287 uint32_t mask_inta_leg_0; 288 /* [0x10] */ 289 uint32_t mask_inta_leg_1; 290 /* [0x14] */ 291 uint32_t mask_inta_leg_2; 292 /* [0x18] */ 293 uint32_t mask_msi_leg_0; 294 /* [0x1c] */ 295 uint32_t mask_msi_leg_1; 296 /* [0x20] */ 297 uint32_t mask_msi_leg_2; 298 /* [0x24] */ 299 uint32_t msi_leg_cntl; 300}; 301struct al_pcie_rev2_w_soc_int { 302 /* [0x0] */ 303 uint32_t status_0; 304 /* [0x4] */ 305 uint32_t status_1; 306 /* [0x8] */ 307 uint32_t status_2; 308 /* [0xc] */ 309 uint32_t status_3; 310 /* [0x10] */ 311 uint32_t mask_inta_leg_0; 312 /* [0x14] */ 313 uint32_t mask_inta_leg_1; 314 /* [0x18] */ 315 uint32_t mask_inta_leg_2; 316 /* [0x1c] */ 317 uint32_t mask_inta_leg_3; 318 /* [0x20] */ 319 uint32_t mask_msi_leg_0; 320 /* [0x24] */ 321 uint32_t mask_msi_leg_1; 322 /* [0x28] */ 323 uint32_t mask_msi_leg_2; 324 /* [0x2c] */ 325 uint32_t mask_msi_leg_3; 326 /* [0x30] */ 327 uint32_t msi_leg_cntl; 328}; 329struct al_pcie_rev3_w_soc_int_per_func { 330 /* [0x0] */ 331 uint32_t status_0; 332 /* [0x4] */ 333 uint32_t status_1; 334 /* [0x8] */ 335 uint32_t status_2; 336 /* [0xc] */ 337 uint32_t status_3; 338 /* [0x10] */ 339 uint32_t mask_inta_leg_0; 340 /* [0x14] */ 341 uint32_t mask_inta_leg_1; 342 /* [0x18] */ 343 uint32_t mask_inta_leg_2; 344 /* [0x1c] */ 345 uint32_t mask_inta_leg_3; 346 /* [0x20] */ 347 uint32_t mask_msi_leg_0; 348 /* [0x24] */ 349 uint32_t mask_msi_leg_1; 350 /* [0x28] */ 351 uint32_t mask_msi_leg_2; 352 /* [0x2c] */ 353 uint32_t mask_msi_leg_3; 354 /* [0x30] */ 355 uint32_t msi_leg_cntl; 356}; 357 358struct al_pcie_revx_w_ap_err { 359 /* 360 * [0x0] latch the header in case of any error occur in the core, read 361 * on clear of the last register in the bind. 362 */ 363 uint32_t hdr_log; 364}; 365struct al_pcie_revx_w_status_per_func { 366 /* 367 * [0x0] latch the header in case of any error occure in the core, read 368 * on clear of the last register in the bind. 369 */ 370 uint32_t status_per_func; 371}; 372struct al_pcie_revx_w_int_grp { 373 /* 374 * [0x0] Interrupt Cause Register 375 * Set by hardware 376 * - If MSI-X is enabled and auto_clear control bit =TRUE, automatically 377 * cleared after MSI-X message associated with this specific interrupt 378 * bit is sent (MSI-X acknowledge is received). 379 * - Software can set a bit in this register by writing 1 to the 380 * associated bit in the Interrupt Cause Set register 381 * Write-0 clears a bit. Write-1 has no effect. 382 * - On CPU Read - If clear_on_read control bit =TRUE, automatically 383 * cleared (all bits are cleared). 384 * When there is a conflict and on the same clock cycle, hardware tries 385 * to set a bit in the Interrupt Cause register, the specific bit is set 386 * to ensure the interrupt indication is not lost. 387 */ 388 uint32_t cause; 389 uint32_t rsrvd_0; 390 /* 391 * [0x8] Interrupt Cause Set Register 392 * Writing 1 to a bit in this register sets its corresponding cause bit, 393 * enabling software to generate a hardware interrupt. Write 0 has no 394 * effect. 395 */ 396 uint32_t cause_set; 397 uint32_t rsrvd_1; 398 /* 399 * [0x10] Interrupt Mask Register 400 * If Auto-mask control bit =TRUE, automatically set to 1 after MSI-X 401 * message associatd with the associated interrupt bit is sent (AXI 402 * write acknowledge is received). 403 */ 404 uint32_t mask; 405 uint32_t rsrvd_2; 406 /* 407 * [0x18] Interrupt Mask Clear Register 408 * Used when auto-mask control bit=True. Enables CPU to clear a specific 409 * bit. It prevents a scenario in which the CPU overrides another bit 410 * with 1 (old value) that hardware has just cleared to 0. 411 * Write 0 to this register clears its corresponding mask bit. Write 1 412 * has no effect. 413 */ 414 uint32_t mask_clear; 415 uint32_t rsrvd_3; 416 /* 417 * [0x20] Interrupt Status Register 418 * This register latches the status of the interrupt source. 419 */ 420 uint32_t status; 421 uint32_t rsrvd_4; 422 /* [0x28] Interrupt Control Register */ 423 uint32_t control; 424 uint32_t rsrvd_5; 425 /* 426 * [0x30] Interrupt Mask Register 427 * Each bit in this register masks the corresponding cause bit for 428 * generating an Abort signal. Its default value is determined by unit 429 * instantiation. 430 * (Abort = Wire-OR of Cause & !Interrupt_Abort_Mask) 431 * This register provides error handling configuration for error 432 * interrupts 433 */ 434 uint32_t abort_mask; 435 uint32_t rsrvd_6; 436 /* 437 * [0x38] Interrupt Log Register 438 * Each bit in this register masks the corresponding cause bit for 439 * capturing the log registers. Its default value is determined by unit 440 * instantiation. 441 * (Log_capture = Wire-OR of Cause & !Interrupt_Log_Mask) 442 * This register provides error handling configuration for error 443 * interrupts. 444 */ 445 uint32_t log_mask; 446 uint32_t rsrvd; 447}; 448 449struct al_pcie_rev1_w_regs { 450 struct al_pcie_rev1_w_global_ctrl global_ctrl; /* [0x0] */ 451 uint32_t rsrvd_0[24]; 452 struct al_pcie_revx_w_debug debug; /* [0x80] */ 453 struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */ 454 uint32_t rsrvd_1[86]; 455 struct al_pcie_rev1_w_soc_int soc_int; /* [0x200] */ 456 struct al_pcie_revx_w_link_down link_down; /* [0x228] */ 457 struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */ 458 struct al_pcie_revx_w_parity parity; /* [0x234] */ 459 struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */ 460 struct al_pcie_rev1_2_w_atu atu; /* [0x240] */ 461 uint32_t rsrvd_2[36]; 462 struct al_pcie_revx_w_int_grp int_grp_a_m0; /* [0x300] */ 463 struct al_pcie_revx_w_int_grp int_grp_b_m0; /* [0x340] */ 464 uint32_t rsrvd_3[32]; 465 struct al_pcie_revx_w_int_grp int_grp_a; /* [0x400] */ 466 struct al_pcie_revx_w_int_grp int_grp_b; /* [0x440] */ 467}; 468 469struct al_pcie_rev2_w_regs { 470 struct al_pcie_rev2_w_global_ctrl global_ctrl; /* [0x0] */ 471 uint32_t rsrvd_0[24]; 472 struct al_pcie_revx_w_debug debug; /* [0x80] */ 473 struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */ 474 struct al_pcie_revx_w_ap_user_send_msg ap_user_send_msg; /* [0xa8] */ 475 uint32_t rsrvd_1[20]; 476 struct al_pcie_rev2_w_soc_int soc_int; /* [0x100] */ 477 uint32_t rsrvd_2[61]; 478 struct al_pcie_revx_w_link_down link_down; /* [0x228] */ 479 struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */ 480 struct al_pcie_revx_w_parity parity; /* [0x234] */ 481 struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */ 482 struct al_pcie_rev1_2_w_atu atu; /* [0x240] */ 483 uint32_t rsrvd_3[6]; 484 struct al_pcie_revx_w_ap_err ap_err[4]; /* [0x288] */ 485 uint32_t rsrvd_4[26]; 486 struct al_pcie_revx_w_status_per_func status_per_func; /* [0x300] */ 487 uint32_t rsrvd_5[63]; 488 struct al_pcie_revx_w_int_grp int_grp_a; /* [0x400] */ 489 struct al_pcie_revx_w_int_grp int_grp_b; /* [0x440] */ 490}; 491 492struct al_pcie_rev3_w_regs { 493 struct al_pcie_rev3_w_global_ctrl global_ctrl; /* [0x0] */ 494 uint32_t rsrvd_0[24]; 495 struct al_pcie_revx_w_debug debug; /* [0x80] */ 496 struct al_pcie_revx_w_ob_ven_msg ob_ven_msg; /* [0x90] */ 497 struct al_pcie_revx_w_ap_user_send_msg ap_user_send_msg; /* [0xa8] */ 498 uint32_t rsrvd_1[94]; 499 struct al_pcie_revx_w_link_down link_down; /* [0x228] */ 500 struct al_pcie_revx_w_cntl_gen ctrl_gen; /* [0x230] */ 501 struct al_pcie_revx_w_parity parity; /* [0x234] */ 502 struct al_pcie_revx_w_last_wr last_wr; /* [0x23c] */ 503 struct al_pcie_rev3_w_atu atu; /* [0x240] */ 504 uint32_t rsrvd_2[8]; 505 struct al_pcie_rev3_w_cfg_func_ext cfg_func_ext; /* [0x2e0] */ 506 struct al_pcie_rev3_w_app_hdr_interface_send app_hdr_interface_send;/* [0x2e4] */ 507 struct al_pcie_rev3_w_diag_command diag_command; /* [0x300] */ 508 uint32_t rsrvd_3[3]; 509 struct al_pcie_rev3_w_soc_int_per_func soc_int_per_func[REV3_MAX_NUM_OF_PFS]; /* [0x310] */ 510 uint32_t rsrvd_4[44]; 511 struct al_pcie_rev3_w_events_gen_per_func events_gen_per_func[REV3_MAX_NUM_OF_PFS]; /* [0x490] */ 512 uint32_t rsrvd_5[4]; 513 struct al_pcie_rev3_w_pm_state_per_func pm_state_per_func[REV3_MAX_NUM_OF_PFS];/* [0x4b0] */ 514 uint32_t rsrvd_6[16]; 515 struct al_pcie_rev3_w_cfg_bars_ovrd cfg_bars_ovrd[REV3_MAX_NUM_OF_PFS]; /* [0x500] */ 516 uint32_t rsrvd_7[176]; 517 uint32_t rsrvd_8[16]; 518 struct al_pcie_revx_w_ap_err ap_err[5]; /* [0xac0] */ 519 uint32_t rsrvd_9[11]; 520 struct al_pcie_revx_w_status_per_func status_per_func[4]; /* [0xb00] */ 521 uint32_t rsrvd_10[316]; 522 struct al_pcie_revx_w_int_grp int_grp_a; /* [0x1000] */ 523 struct al_pcie_revx_w_int_grp int_grp_b; /* [0x1040] */ 524 struct al_pcie_revx_w_int_grp int_grp_c; /* [0x1080] */ 525 struct al_pcie_revx_w_int_grp int_grp_d; /* [0x10c0] */ 526}; 527 528/* 529* Registers Fields 530*/ 531 532 533/**** Port_Init register ****/ 534/* Enable port to start LTSSM Link Training */ 535#define PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_MASK (1 << 0) 536#define PCIE_W_GLOBAL_CTRL_PORT_INIT_APP_LTSSM_EN_SHIFT (0) 537/* 538 * Device Type 539 * Indicates the specific type of this PCIe Function. It is also used to set the 540 * Device/Port Type field. 541 * 4'b0000: PCIe Endpoint 542 * 4'b0001: Legacy PCIe Endpoint 543 * 4'b0100: Root Port of PCIe Root Complex 544 * Must be programmed before link training sequence. According to the reset 545 * strap 546 */ 547#define PCIE_W_GLOBAL_CTRL_PORT_INIT_DEVICE_TYPE_MASK 0x000000F0 548#define PCIE_W_GLOBAL_CTRL_PORT_INIT_DEVICE_TYPE_SHIFT 4 549/* 550 * Performs Manual Lane reversal for transmit Lanes. 551 * Must be programmed before link training sequence. 552 */ 553#define PCIE_W_GLOBAL_CTRL_PORT_INIT_TX_LANE_FLIP_EN (1 << 8) 554/* 555 * Performs Manual Lane reversal for receive Lanes. 556 * Must be programmed before link training sequence. 557 */ 558#define PCIE_W_GLOBAL_CTRL_PORT_INIT_RX_LANE_FLIP_EN (1 << 9) 559/* 560 * Auxiliary Power Detected 561 * Indicates that auxiliary power (Vaux) is present. This one move to reset 562 * strap from 563 */ 564#define PCIE_W_GLOBAL_CTRL_PORT_INIT_SYS_AUX_PWR_DET_NOT_USE (1 << 10) 565 566/**** Port_Status register ****/ 567/* PHY Link up/down indicator */ 568#define PCIE_W_GLOBAL_CTRL_PORT_STS_PHY_LINK_UP (1 << 0) 569/* 570 * Data Link Layer up/down indicator 571 * This status from the Flow Control Initialization State Machine indicates that 572 * Flow Control has been initiated and the Data Link Layer is ready to transmit 573 * and receive packets. 574 */ 575#define PCIE_W_GLOBAL_CTRL_PORT_STS_DL_LINK_UP (1 << 1) 576/* Reset request due to link down status. */ 577#define PCIE_W_GLOBAL_CTRL_PORT_STS_LINK_REQ_RST (1 << 2) 578/* Power management is in L0s state.. */ 579#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L0S (1 << 3) 580/* Power management is in L1 state. */ 581#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L1 (1 << 4) 582/* Power management is in L2 state. */ 583#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_IN_L2 (1 << 5) 584/* Power management is exiting L2 state. */ 585#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_LINKST_L2_EXIT (1 << 6) 586/* Power state of the device. */ 587#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_DSTATE_MASK 0x00000380 588#define PCIE_W_GLOBAL_CTRL_PORT_STS_PM_DSTATE_SHIFT 7 589/* tie to zero. */ 590#define PCIE_W_GLOBAL_CTRL_PORT_STS_XMLH_IN_RL0S (1 << 10) 591/* Timeout count before flush */ 592#define PCIE_W_GLOBAL_CTRL_PORT_STS_LINK_TOUT_FLUSH_NOT (1 << 11) 593/* Segmentation buffer not empty */ 594#define PCIE_W_GLOBAL_CTRL_PORT_STS_RADM_Q_NOT_EMPTY (1 << 12) 595/* 596 * Clock Turnoff Request 597 * Allows clock generation module to turn off core_clk based on the current 598 * power management state: 599 * 0: core_clk is required to be active for the current power state. 600 * 1: The current power state allows core_clk to be shut down. 601 * This does not indicate the clock requirement for the PHY. 602 */ 603#define PCIE_W_GLOBAL_CTRL_PORT_STS_CORE_CLK_REQ_N (1 << 31) 604 605/**** PM_Control register ****/ 606/* 607 * Wake Up. Used by application logic to wake up the PMC state machine from a 608 * D1, D2, or D3 power state. EP mode only. Change the value from 0 to 1 to send 609 * the message. Per function the upper bits are not use for ocie core less than 610 * 8 functions 611 */ 612#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME (1 << 0) 613#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME_FUNC_MASK 0x000000FF 614#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_PME_FUNC_SHIFT 0 615/* 616 * Request to Enter ASPM L1. 617 * The core ignores the L1 entry request on app_req_entr_l1 when it is busy 618 * processing a transaction. 619 */ 620#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_REQ_ENTR_L1 (1 << 3) 621#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_REQ_ENTR_L1 (1 << 8) 622/* 623 * Request to exit ASPM L1. 624 * Only effective if L1 is enabled. 625 */ 626#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_REQ_EXIT_L1 (1 << 4) 627#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_REQ_EXIT_L1 (1 << 9) 628/* 629 * Indication that component is ready to enter the L23 state. The core delays 630 * sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes 631 * active. 632 * EP mode 633 */ 634#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_READY_ENTR_L23 (1 << 5) 635#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_READY_ENTR_L23 (1 << 10) 636/* 637 * Request to generate a PM_Turn_Off Message to communicate transition to L2/L3 638 * Ready state to downstream components. Host must wait PM_Turn_Off_Ack messages 639 * acceptance RC mode. 640 */ 641#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_PM_XMT_TURNOFF (1 << 6) 642#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_PM_XMT_TURNOFF (1 << 11) 643/* 644 * Provides a capability to defer incoming Configuration Requests until 645 * initialization is complete. When app_req_retry_en is asserted, the core 646 * completes incoming Configuration Requests with a Configuration Request Retry 647 * Status. Other incoming Requests complete with Unsupported Request status. 648 */ 649#define PCIE_W_REV1_2_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN (1 << 7) 650#define PCIE_W_REV3_GLOBAL_CTRL_PM_CONTROL_APP_REQ_RETRY_EN (1 << 12) 651/* 652 * Core core gate enable 653 * If set, core_clk is gated off whenever a clock turnoff request allows the 654 * clock generation module to turn off core_clk (Port_Status.core_clk_req_n 655 * field), and the PHY supports a request to disable clock gating. If not, the 656 * core clock turns off in P2 mode in any case (PIPE). 657 */ 658#define PCIE_W_GLOBAL_CTRL_PM_CONTROL_CORE_CLK_GATE (1 << 31) 659 660/**** sris_kp_counter_value register ****/ 661/* skp counter when SRIS disable */ 662#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_NO_SRIS_MASK 0x000001FF 663#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_NO_SRIS_SHIFT 0 664/* skp counter when SRIS enable */ 665#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_MASK 0x0003FE00 666#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN3_SRIS_SHIFT 9 667/* skp counter when SRIS enable for gen3 */ 668#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_MASK 0x1FFC0000 669#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_GEN21_SRIS_SHIFT 18 670/* mask the interrupt to the soc in case correctable error occur in the ARI. */ 671#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_RSRVD_MASK 0x60000000 672#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_RSRVD_SHIFT 29 673/* not in use in the pcie_x8 core. */ 674#define PCIE_W_GLOBAL_CTRL_SRIS_KP_COUNTER_VALUE_PCIE_X4_SRIS_EN (1 << 31) 675 676/**** Events_Gen register ****/ 677/* INT_D. Not supported */ 678#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTD (1 << 0) 679/* INT_C. Not supported */ 680#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTC (1 << 1) 681/* INT_B. Not supported */ 682#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTB (1 << 2) 683/* Transmit INT_A Interrupt ControlEvery transition from 0 to 1 ... */ 684#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTA (1 << 3) 685/* A request to generate an outbound MSI interrupt when MSI is e ... */ 686#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_TRNS_REQ (1 << 4) 687/* Set the MSI vector before issuing msi_trans_req. */ 688#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK 0x000003E0 689#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_SHIFT 5 690/* The application requests hot reset to a downstream device */ 691#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT (1 << 10) 692/* The application request unlock message to be sent */ 693#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_UNLOCK_GEN (1 << 30) 694/* Indicates that FLR on a Physical Function has been completed */ 695#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE (1 << 31) 696 697/**** Cpl_TO_Info register ****/ 698/* The Traffic Class of the timed out CPL */ 699#define PCIE_W_LCL_LOG_CPL_TO_INFO_TC_MASK 0x00000003 700#define PCIE_W_LCL_LOG_CPL_TO_INFO_TC_SHIFT 0 701/* Indicates which Virtual Function (VF) had a CPL timeout */ 702#define PCIE_W_LCL_LOG_CPL_TO_INFO_FUN_NUM_MASK 0x000000FC 703#define PCIE_W_LCL_LOG_CPL_TO_INFO_FUN_NUM_SHIFT 2 704/* The Tag field of the timed out CPL */ 705#define PCIE_W_LCL_LOG_CPL_TO_INFO_TAG_MASK 0x0000FF00 706#define PCIE_W_LCL_LOG_CPL_TO_INFO_TAG_SHIFT 8 707/* The Attributes field of the timed out CPL */ 708#define PCIE_W_LCL_LOG_CPL_TO_INFO_ATTR_MASK 0x00030000 709#define PCIE_W_LCL_LOG_CPL_TO_INFO_ATTR_SHIFT 16 710/* The Len field of the timed out CPL */ 711#define PCIE_W_LCL_LOG_CPL_TO_INFO_LEN_MASK 0x3FFC0000 712#define PCIE_W_LCL_LOG_CPL_TO_INFO_LEN_SHIFT 18 713/* 714 * Write 1 to this field to clear the information logged in the register. New 715 * logged information will only be valid when the interrupt is cleared . 716 */ 717#define PCIE_W_LCL_LOG_CPL_TO_INFO_VALID (1 << 31) 718#define PCIE_W_LCL_LOG_CPL_TO_INFO_VALID_SHIFT (31) 719 720/**** Rcv_Msg0_0 register ****/ 721/* The Requester ID of the received message */ 722#define PCIE_W_LCL_LOG_RCV_MSG0_0_REQ_ID_MASK 0x0000FFFF 723#define PCIE_W_LCL_LOG_RCV_MSG0_0_REQ_ID_SHIFT 0 724/* 725 * Valid logged message 726 * Writing 1 to this bit enables new message capturing. Write one to clear 727 */ 728#define PCIE_W_LCL_LOG_RCV_MSG0_0_VALID (1 << 31) 729 730/**** Rcv_Msg1_0 register ****/ 731/* The Requester ID of the received message */ 732#define PCIE_W_LCL_LOG_RCV_MSG1_0_REQ_ID_MASK 0x0000FFFF 733#define PCIE_W_LCL_LOG_RCV_MSG1_0_REQ_ID_SHIFT 0 734/* 735 * Valid logged message 736 * Writing 1 to this bit enables new message capturing. Write one to clear 737 */ 738#define PCIE_W_LCL_LOG_RCV_MSG1_0_VALID (1 << 31) 739 740/**** Core_Queues_Status register ****/ 741/* 742 * Indicates which entries in the CPL lookup table 743 * have valid entries stored. NOT supported. 744 */ 745#define PCIE_W_LCL_LOG_CORE_Q_STATUS_CPL_LUT_VALID_MASK 0x0000FFFF 746#define PCIE_W_LCL_LOG_CORE_Q_STATUS_CPL_LUT_VALID_SHIFT 0 747 748/**** Cpl_to register ****/ 749#define PCIE_W_LCL_LOG_CPL_TO_REQID_MASK 0x0000FFFF 750#define PCIE_W_LCL_LOG_CPL_TO_REQID_SHIFT 0 751 752/**** Debug_Info_0 register ****/ 753/* Indicates the current power state */ 754#define PCIE_W_DEBUG_INFO_0_PM_CURRENT_STATE_MASK 0x00000007 755#define PCIE_W_DEBUG_INFO_0_PM_CURRENT_STATE_SHIFT 0 756/* Current state of the LTSSM */ 757#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_MASK 0x000001F8 758#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_SHIFT 3 759/* Decode of the Recovery. Equalization LTSSM state */ 760#define PCIE_W_DEBUG_INFO_0_LTSSM_STATE_RCVRY_EQ (1 << 9) 761/* State of selected internal signals, for debug purposes only */ 762#define PCIE_W_DEBUG_INFO_0_CXPL_DEBUG_INFO_EI_MASK 0x03FFFC00 763#define PCIE_W_DEBUG_INFO_0_CXPL_DEBUG_INFO_EI_SHIFT 10 764 765/**** control register ****/ 766/* Indication to send vendor message; when clear the message was sent. */ 767#define PCIE_W_OB_VEN_MSG_CONTROL_REQ (1 << 0) 768 769/**** param_1 register ****/ 770/* Vendor message parameters */ 771#define PCIE_W_OB_VEN_MSG_PARAM_1_FMT_MASK 0x00000003 772#define PCIE_W_OB_VEN_MSG_PARAM_1_FMT_SHIFT 0 773/* Vendor message parameters */ 774#define PCIE_W_OB_VEN_MSG_PARAM_1_TYPE_MASK 0x0000007C 775#define PCIE_W_OB_VEN_MSG_PARAM_1_TYPE_SHIFT 2 776/* Vendor message parameters */ 777#define PCIE_W_OB_VEN_MSG_PARAM_1_TC_MASK 0x00000380 778#define PCIE_W_OB_VEN_MSG_PARAM_1_TC_SHIFT 7 779/* Vendor message parameters */ 780#define PCIE_W_OB_VEN_MSG_PARAM_1_TD (1 << 10) 781/* Vendor message parameters */ 782#define PCIE_W_OB_VEN_MSG_PARAM_1_EP (1 << 11) 783/* Vendor message parameters */ 784#define PCIE_W_OB_VEN_MSG_PARAM_1_ATTR_MASK 0x00003000 785#define PCIE_W_OB_VEN_MSG_PARAM_1_ATTR_SHIFT 12 786/* Vendor message parameters */ 787#define PCIE_W_OB_VEN_MSG_PARAM_1_LEN_MASK 0x00FFC000 788#define PCIE_W_OB_VEN_MSG_PARAM_1_LEN_SHIFT 14 789/* Vendor message parameters */ 790#define PCIE_W_OB_VEN_MSG_PARAM_1_TAG_MASK 0xFF000000 791#define PCIE_W_OB_VEN_MSG_PARAM_1_TAG_SHIFT 24 792 793/**** param_2 register ****/ 794/* Vendor message parameters */ 795#define PCIE_W_OB_VEN_MSG_PARAM_2_REQ_ID_MASK 0x0000FFFF 796#define PCIE_W_OB_VEN_MSG_PARAM_2_REQ_ID_SHIFT 0 797/* Vendor message parameters */ 798#define PCIE_W_OB_VEN_MSG_PARAM_2_CODE_MASK 0x00FF0000 799#define PCIE_W_OB_VEN_MSG_PARAM_2_CODE_SHIFT 16 800/* Vendor message parameters */ 801#define PCIE_W_OB_VEN_MSG_PARAM_2_RSVD_31_24_MASK 0xFF000000 802#define PCIE_W_OB_VEN_MSG_PARAM_2_RSVD_31_24_SHIFT 24 803 804/**** ack_info register ****/ 805/* Vendor message parameters */ 806#define PCIE_W_AP_USER_SEND_MSG_ACK_INFO_ACK (1 << 0) 807 808/**** features register ****/ 809/* Enable MSI fix from the SATA to the PCIe EP - Only valid for port zero */ 810#define PCIE_W_CTRL_GEN_FEATURES_SATA_EP_MSI_FIX AL_BIT(16) 811 812/**** in/out_mask_x_y register ****/ 813/* When bit [i] set to 1 it maks the compare in the atu_in/out wind ... */ 814#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_MASK 0x0000FFFF 815#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_EVEN_SHIFT 0 816/* When bit [i] set to 1 it maks the compare in the atu_in/out wind ... */ 817#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_MASK 0xFFFF0000 818#define PCIE_W_ATU_MASK_EVEN_ODD_ATU_MASK_40_32_ODD_SHIFT 16 819 820/**** cfg register ****/ 821/* 822 * The 2-bit TPH Requester Enabled field of each TPH 823 * Requester Control register. 824 */ 825#define PCIE_W_CFG_FUNC_EXT_CFG_CFG_TPH_REQ_EN_MASK 0x000000FF 826#define PCIE_W_CFG_FUNC_EXT_CFG_CFG_TPH_REQ_EN_SHIFT 0 827/* SRIS mode enable. */ 828#define PCIE_W_CFG_FUNC_EXT_CFG_APP_SRIS_MODE (1 << 8) 829/* 830 * 831 */ 832#define PCIE_W_CFG_FUNC_EXT_CFG_RSRVD_MASK 0xFFFFFE00 833#define PCIE_W_CFG_FUNC_EXT_CFG_RSRVD_SHIFT 9 834 835/**** app_func_num_advisory register ****/ 836/* 837 * The number of the function that is reporting the error 838 * indicated app_err_bus, valid when app_hdr_valid is asserted. 839 * Correctable and Uncorrected Internal errors (app_err_bus[10:9]) are 840 * not function specific, and are recorded for all physical functions, 841 * regardless of the value this bus. Function numbering starts at '0'. 842 */ 843#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_FUNC_NUM_MASK 0x0000FFFF 844#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_FUNC_NUM_SHIFT 0 845/* 846 * Description: Indicates that your application error is an advisory 847 * error. Your application should assert app_err_advisory under either 848 * of the following conditions: 849 * - The core is configured to mask completion timeout errors, your 850 * application is reporting a completion timeout error app_err_bus, 851 * and your application intends to resend the request. In such cases 852 * the error is an advisory error, as described in PCI Express 3.0 853 * Specification. When your application does not intend to resend 854 * the request, then your application must keep app_err_advisory 855 * de-asserted when reporting a completion timeout error. 856 * - The core is configured to forward poisoned TLPs to your 857 * application and your application is going to treat the poisoned 858 * TLP as a normal TLP, as described in PCI Express 3.0 859 * Specification. Upon receipt of a poisoned TLP, your application 860 * must report the error app_err_bus, and either assert 861 * app_err_advisory (to indicate an advisory error) or de-assert 862 * app_err_advisory (to indicate that your application is dropping the 863 * TLP). 864 * For more details, see the PCI Express 3.0 Specification to determine 865 * when an application error is an advisory error. 866 */ 867#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_APP_ERR_ADVISORY (1 << 16) 868/* 869 * Rsrvd. 870 */ 871#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_RSRVD_MASK 0xFFFE0000 872#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_FUNC_NUM_ADVISORY_RSRVD_SHIFT 17 873 874/**** app_hdr_cmd register ****/ 875/* 876 * When set the header is send (need to clear before sending the next message). 877 */ 878#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_APP_HDR_VALID (1 << 0) 879/* 880 * Rsrvd. 881 */ 882#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_RSRVD_MASK 0xFFFFFFFE 883#define PCIE_W_APP_HDR_INTERFACE_SEND_APP_HDR_CMD_RSRVD_SHIFT 1 884 885/**** diag_ctrl register ****/ 886/* 887 * The 2-bit TPH Requester Enabled field of each TPH 888 * Requester Control register. 889 */ 890#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_DIAG_CTRL_BUS_MASK 0x00000007 891#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_DIAG_CTRL_BUS_SHIFT 0 892/* 893 * 894 */ 895#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_RSRVD_MASK 0xFFFFFFF8 896#define PCIE_W_DIAG_COMMAND_DIAG_CTRL_RSRVD_SHIFT 3 897 898 899/**** Events_Gen register ****/ 900/* INT_D. Not supported */ 901#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTD (1 << 0) 902/* INT_C. Not supported */ 903#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTC (1 << 1) 904/* INT_B. Not supported */ 905#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTB (1 << 2) 906/* 907 * Transmit INT_A Interrupt Control 908 * Every transition from 0 to 1 schedules an Assert_ INT interrupt message for 909 * transmit. 910 * Every transition from 1 to 0, schedules a Deassert_INT interrupt message for 911 * transmit. Which interrupt, the PCIe only use INTA message. 912 */ 913#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_ASSERT_INTA (1 << 3) 914/* 915 * A request to generate an outbound MSI interrupt when MSI is enabled. Change 916 * from 1'b0 to 1'b1 to create an MSI write to be sent. 917 */ 918#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_TRNS_REQ (1 << 4) 919/* Set the MSI vector before issuing msi_trans_req. */ 920#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_MASK 0x000003E0 921#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_MSI_VECTOR_SHIFT 5 922/* 923 * The application requests hot reset to a downstream device. Change the value 924 * from 0 to 1 to send hot reset. Only func 0 is supported. 925 */ 926#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_APP_RST_INIT (1 << 10) 927/* 928 * The application request unlock message to be sent. Change the value from 0 to 929 * 1 to send the message. Only func 0 is supported. 930 */ 931#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_UNLOCK_GEN (1 << 30) 932/* Indicates that FLR on a Physical Function has been completed. */ 933#define PCIE_W_GLOBAL_CTRL_EVENTS_GEN_FLR_PF_DONE (1 << 31) 934 935/**** pm_state_per_func register ****/ 936/* 937 * Description: The current power management D-state of the 938 * function: 939 * \u25a0 000b: D0 940 * \u25a0 001b: D1 941 * \u25a0 010b: D2 942 * \u25a0 011b: D3 943 * \u25a0 100b: Uninitialized 944 * \u25a0 Other values: Not applicable 945 * There are 3 bits of pm_dstate for each configured function. 946 */ 947#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_DSTATE_MASK 0x0000000F 948#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_DSTATE_SHIFT 0 949/* 950 * PME Status bit from the PMCSR. There is 1 bit of 951 * pm_status for each configured function 952 */ 953#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_STATUS (1 << 4) 954/* 955 * PME Enable bit in the PMCSR. There is 1 bit of 956 * pm_pme_en for each configured function. 957 */ 958#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_PM_PME_EN (1 << 5) 959/* 960 * Auxiliary Power Enable bit in the Device Control 961 * register. There is 1 bit of aux_pm_en for each configured function. 962 */ 963#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_AUX_PME_EN (1 << 6) 964/* 965 * This field should be set according to the MAX_FUNC_NUM set in the PCIe core, 966 * it uses as mask (bit per function) to the dsate when set to zero. 967 */ 968#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_ASPM_PF_ENABLE_MAX_FUNC_NUMBER (1 << 7) 969/* 970 * This field should be set according to the MAX_FUNC_NUM set in the PCIe core, 971 * it uses as mask (bit per function) to the ASPM contrl bit, when set to zero. 972 */ 973#define PCIE_W_PM_STATE_PER_FUNC_PM_STATE_PER_FUNC_DSATE_PF_ENABLE_MAX_FUNC_NUMBER (1 << 8) 974 975/**** bar0_ctrl register ****/ 976/* bar is en and override the internal PF bar. */ 977#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_EN_MASK 0x00000003 978#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_EN_SHIFT 0 979/* bar is io */ 980#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_IO_MASK 0x0000000C 981#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_BAR_IO_SHIFT 2 982/* Reserved. */ 983#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_RSRVS_MASK 0xFFFFFFF0 984#define PCIE_W_CFG_BARS_OVRD_BAR0_CTRL_RSRVS_SHIFT 4 985 986/**** bar1_ctrl register ****/ 987/* bar is en and override the internal PF bar. */ 988#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_EN_MASK 0x00000003 989#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_EN_SHIFT 0 990/* bar is io */ 991#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_IO_MASK 0x0000000C 992#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_BAR_IO_SHIFT 2 993/* Reserved. */ 994#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_RSRVS_MASK 0xFFFFFFF0 995#define PCIE_W_CFG_BARS_OVRD_BAR1_CTRL_RSRVS_SHIFT 4 996 997/**** bar2_ctrl register ****/ 998/* bar is en and override the internal PF bar. */ 999#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_EN_MASK 0x00000003 1000#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_EN_SHIFT 0 1001/* bar is io */ 1002#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_IO_MASK 0x0000000C 1003#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_BAR_IO_SHIFT 2 1004/* Reserved. */ 1005#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_RSRVS_MASK 0xFFFFFFF0 1006#define PCIE_W_CFG_BARS_OVRD_BAR2_CTRL_RSRVS_SHIFT 4 1007 1008/**** bar3_ctrl register ****/ 1009/* bar is en and override the internal PF bar. */ 1010#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_EN_MASK 0x00000003 1011#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_EN_SHIFT 0 1012/* bar is io */ 1013#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_IO_MASK 0x0000000C 1014#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_BAR_IO_SHIFT 2 1015/* Reserved. */ 1016#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_RSRVS_MASK 0xFFFFFFF0 1017#define PCIE_W_CFG_BARS_OVRD_BAR3_CTRL_RSRVS_SHIFT 4 1018 1019/**** bar4_ctrl register ****/ 1020/* bar is en and override the internal PF bar. */ 1021#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_EN_MASK 0x00000003 1022#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_EN_SHIFT 0 1023/* bar is io */ 1024#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_IO_MASK 0x0000000C 1025#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_BAR_IO_SHIFT 2 1026/* Reserved. */ 1027#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_RSRVS_MASK 0xFFFFFFF0 1028#define PCIE_W_CFG_BARS_OVRD_BAR4_CTRL_RSRVS_SHIFT 4 1029 1030/**** bar5_ctrl register ****/ 1031/* bar is en and override the internal PF bar. */ 1032#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_EN_MASK 0x00000003 1033#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_EN_SHIFT 0 1034/* bar is io */ 1035#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_IO_MASK 0x0000000C 1036#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_BAR_IO_SHIFT 2 1037/* Reserved. */ 1038#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_RSRVS_MASK 0xFFFFFFF0 1039#define PCIE_W_CFG_BARS_OVRD_BAR5_CTRL_RSRVS_SHIFT 4 1040 1041/**** cause_A register ****/ 1042/* Deassert_INTD received. Write zero to clear this bit. */ 1043#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTD (1 << 0) 1044/* Deassert_INTC received. Write zero to clear this bit. */ 1045#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTC (1 << 1) 1046/* Deassert_INTB received. Write zero to clear this bit. */ 1047#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTB (1 << 2) 1048/* Deassert_INTA received. Write zero to clear this bit. */ 1049#define PCIE_W_INT_GRP_A_CAUSE_A_DEASSERT_INTA (1 << 3) 1050/* Assert_INTD received. Write zero to clear this bit. */ 1051#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTD (1 << 4) 1052/* Assert_INTC received. Write zero to clear this bit. */ 1053#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTC (1 << 5) 1054/* Assert_INTC received. Write zero to clear this bit. */ 1055#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTB (1 << 6) 1056/* Assert_INTA received. Write zero to clear this bit. */ 1057#define PCIE_W_INT_GRP_A_CAUSE_A_ASSERT_INTA (1 << 7) 1058/* 1059 * MSI Controller Interrupt 1060 * MSI interrupt is being received. Write zero to clear this bit 1061 */ 1062#define PCIE_W_INT_GRP_A_CAUSE_A_MSI_CNTR_RCV_INT (1 << 8) 1063/* 1064 * MSI sent grant. Write zero to clear this bit. 1065 */ 1066#define PCIE_W_INT_GRP_A_CAUSE_A_MSI_TRNS_GNT (1 << 9) 1067/* 1068 * System error detected 1069 * Indicates if any device in the hierarchy reports any of the following errors 1070 * and the associated enable bit is set in the Root Control register: 1071 * ERR_COR 1072 * ERR_FATAL 1073 * ERR_NONFATAL 1074 * Also asserted when an internal error is detected. Write zero to clear this 1075 * bit. 1076 */ 1077#define PCIE_W_INT_GRP_A_CAUSE_A_SYS_ERR_RC (1 << 10) 1078/* 1079 * Set when software initiates FLR on a Physical Function by writing to the 1080 * Initiate FLR register bit of that function Write zero to clear this bit. 1081 */ 1082#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_FLR_PF_ACTIVE (1 << 11) 1083#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_11 (1 << 11) 1084/* 1085 * Reported error condition causes a bit to be set in the Root Error Status 1086 * register and the associated error message reporting enable bit is set in the 1087 * Root Error Command Register. Write zero to clear this bit. 1088 */ 1089#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_AER_RC_ERR (1 << 12) 1090#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_12 (1 << 12) 1091/* 1092 * The core asserts aer_rc_err_msi when all of the following conditions are 1093 * true: 1094 * - MSI or MSI-X is enabled. 1095 * - A reported error condition causes a bit to be set in the Root Error Status 1096 * register. 1097 * - The associated error message reporting enable bit is set in the Root Error 1098 * Command register Write zero to clear this bit 1099 */ 1100#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_AER_RC_ERR_MSI (1 << 13) 1101#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_13 (1 << 13) 1102/* 1103 * Wake Up. Wake up from power management unit. 1104 * The core generates wake to request the system to restore power and clock when 1105 * a beacon has been detected. wake is an active high signal and its rising edge 1106 * should be detected to drive the WAKE# on the connector Write zero to clear 1107 * this bit 1108 */ 1109#define PCIE_W_INT_GRP_A_CAUSE_A_WAKE (1 << 14) 1110/* 1111 * The core asserts cfg_pme_int when all of the following conditions are true: 1112 * - INTx Assertion Disable bit in the Command register is 0. 1113 * - PME Interrupt Enable bit in the Root Control register is set to 1. 1114 * - PME Status bit in the Root Status register is set to 1. Write zero to clear 1115 * this bit 1116 */ 1117#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_PME_INT (1 << 15) 1118#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_15 (1 << 15) 1119/* 1120 * The core asserts cfg_pme_msi when all of the following conditions are true: 1121 * - MSI or MSI-X is enabled. 1122 * - PME Interrupt Enable bit in the Root Control register is set to 1. 1123 * - PME Status bit in the Root Status register is set to 1. Write zero to clear 1124 * this bit 1125 */ 1126#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_PME_MSI (1 << 16) 1127#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_RSRVD_16 (1 << 16) 1128/* 1129 * The core asserts hp_pme when all of the following conditions are true: 1130 * - The PME Enable bit in the Power Management Control and Status register is 1131 * set to 1. 1132 * - Any bit in the Slot Status register transitions from 0 to 1 and the 1133 * associated event notification is enabled in the Slot Control register. Write 1134 * zero to clear this bit 1135 */ 1136#define PCIE_W_INT_GRP_A_CAUSE_A_HP_PME (1 << 17) 1137/* 1138 * The core asserts hp_int when all of the following conditions are true: 1139 * - INTx Assertion Disable bit in the Command register is 0. 1140 * - Hot-Plug interrupts are enabled in the Slot Control register. 1141 * - Any bit in the Slot Status register is equal to 1, and the associated event 1142 * notification is enabled in the Slot Control register. Write zero to clear 1143 * this bit 1144 */ 1145#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_HP_INT (1 << 18) 1146/* The outstanding write counter become full should never happen */ 1147#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_WRITE_COUNTER_FULL_ERR (1 << 18) 1148 1149 1150/* 1151 * The core asserts hp_msi when the logical AND of the following conditions 1152 * transitions from false to true: 1153 * - MSI or MSI-X is enabled. 1154 * - Hot-Plug interrupts are enabled in the Slot Control register. 1155 * - Any bit in the Slot Status register transitions from 0 to 1 and the 1156 * associated event notification is enabled in the Slot Control register. 1157 */ 1158#define PCIE_W_INT_GRP_A_CAUSE_A_HP_MSI (1 << 19) 1159/* Read VPD registers notification */ 1160#define PCIE_W_REV1_2_INT_GRP_A_CAUSE_A_VPD_INT (1 << 20) 1161/* not use */ 1162#define PCIE_W_REV3_INT_GRP_A_CAUSE_A_NOT_USE (1 << 20) 1163 1164/* 1165 * The core assert link down event, whenever the link is going down. Write zero 1166 * to clear this bit, pulse signal 1167 */ 1168#define PCIE_W_INT_GRP_A_CAUSE_A_LINK_DOWN_EVENT (1 << 21) 1169/* 1170 * When the EP gets a command to shut down, signal the software to block any new 1171 * TLP. 1172 */ 1173#define PCIE_W_INT_GRP_A_CAUSE_A_PM_XTLH_BLOCK_TLP (1 << 22) 1174/* PHY/MAC link up */ 1175#define PCIE_W_INT_GRP_A_CAUSE_A_XMLH_LINK_UP (1 << 23) 1176/* Data link up */ 1177#define PCIE_W_INT_GRP_A_CAUSE_A_RDLH_LINK_UP (1 << 24) 1178/* The ltssm is in RCVRY_LOCK state. */ 1179#define PCIE_W_INT_GRP_A_CAUSE_A_LTSSM_RCVRY_STATE (1 << 25) 1180/* 1181 * Config write transaction to the config space by the RC peer, enable this 1182 * interrupt only for EP mode. 1183 */ 1184#define PCIE_W_INT_GRP_A_CAUSE_A_CFG_WR_EVENT (1 << 26) 1185/* AER error */ 1186#define PCIE_W_INT_GRP_A_CAUSE_A_AP_PENDED_CORR_ERR_STS_INT (1 << 28) 1187/* AER error */ 1188#define PCIE_W_INT_GRP_A_CAUSE_A_AP_PENDED_UNCORR_ERR_STS_INT (1 << 29) 1189 1190/**** control_A register ****/ 1191/* When Clear_on_Read =1, all bits of Cause register are cleared on read. */ 1192#define PCIE_W_INT_GRP_A_CONTROL_A_CLEAR_ON_READ (1 << 0) 1193/* 1194 * (Must be set only when MSIX is enabled.) 1195 * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its 1196 * corresponding bit in the Mask register is set, masking future interrupts. 1197 */ 1198#define PCIE_W_INT_GRP_A_CONTROL_A_AUTO_MASK (1 << 1) 1199/* 1200 * Auto_Clear (RW) 1201 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared 1202 * after MSI-X is acknowledged. Must be used only if MSI-X is enabled. 1203 */ 1204#define PCIE_W_INT_GRP_A_CONTROL_A_AUTO_CLEAR (1 << 2) 1205/* 1206 * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on 1207 * the posedge of the interrupt source, i.e., when interrupt source =1 and 1208 * Interrupt Status = 0. 1209 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when 1210 * interrupt source =1. 1211 */ 1212#define PCIE_W_INT_GRP_A_CONTROL_A_SET_ON_POSEDGE (1 << 3) 1213/* 1214 * When Moderation_Reset =1, all Moderation timers associated with the interrupt 1215 * cause bits are cleared to 0, enabling immediate interrupt assertion if any 1216 * unmasked cause bit is set to 1. This bit is self-negated. 1217 */ 1218#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RST (1 << 4) 1219/* 1220 * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to 1221 * 1 when the associated summary bit in this group is used to generate a single 1222 * MSI-X for this group. 1223 */ 1224#define PCIE_W_INT_GRP_A_CONTROL_A_MASK_MSI_X (1 << 5) 1225/* MSI-X AWID value. Same ID for all cause bits. */ 1226#define PCIE_W_INT_GRP_A_CONTROL_A_AWID_MASK 0x00000F00 1227#define PCIE_W_INT_GRP_A_CONTROL_A_AWID_SHIFT 8 1228/* 1229 * This value determines the interval between interrupts; writing ZERO disables 1230 * Moderation. 1231 */ 1232#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_INTV_MASK 0x00FF0000 1233#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_INTV_SHIFT 16 1234/* 1235 * This value determines the Moderation_Timer_Clock speed. 1236 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS. 1237 * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS. 1238 * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS. 1239 */ 1240#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RES_MASK 0x0F000000 1241#define PCIE_W_INT_GRP_A_CONTROL_A_MOD_RES_SHIFT 24 1242 1243/**** cause_B register ****/ 1244/* Indicates that the core received a PM_PME Message. Write Zero to clear. */ 1245#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_PME (1 << 0) 1246/* 1247 * Indicates that the core received a PME_TO_Ack Message. Write Zero to clear. 1248 */ 1249#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_TO_ACK (1 << 1) 1250/* 1251 * Indicates that the core received an PME_Turn_Off Message. Write Zero to 1252 * clear. 1253 * EP mode only 1254 */ 1255#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_PM_TURNOFF (1 << 2) 1256/* Indicates that the core received an ERR_CORR Message. Write Zero to clear. */ 1257#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_CORRECTABLE_ERR (1 << 3) 1258/* 1259 * Indicates that the core received an ERR_NONFATAL Message. Write Zero to 1260 * clear. 1261 */ 1262#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_NONFATAL_ERR (1 << 4) 1263/* 1264 * Indicates that the core received an ERR_FATAL Message. Write Zero to clear. 1265 */ 1266#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_FATAL_ERR (1 << 5) 1267/* 1268 * Indicates that the core received a Vendor Defined Message. Write Zero to 1269 * clear. 1270 */ 1271#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_VENDOR_0 (1 << 6) 1272/* 1273 * Indicates that the core received a Vendor Defined Message. Write Zero to 1274 * clear. 1275 */ 1276#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_VENDOR_1 (1 << 7) 1277/* Indicates that the core received an Unlock Message. Write Zero to clear. */ 1278#define PCIE_W_INT_GRP_B_CAUSE_B_MSG_UNLOCK (1 << 8) 1279/* 1280 * Notification when the Link Autonomous Bandwidth Status register (Link Status 1281 * register bit 15) is updated and the Link Autonomous Bandwidth Interrupt 1282 * Enable (Link Control register bit 11) is set. This bit is not applicable to, 1283 * and is reserved, for Endpoint device. Write Zero to clear 1284 */ 1285#define PCIE_W_INT_GRP_B_CAUSE_B_LINK_AUTO_BW_INT (1 << 12) 1286/* 1287 * Notification that the Link Equalization Request bit in the Link Status 2 1288 * Register has been set. Write Zero to clear. 1289 */ 1290#define PCIE_W_INT_GRP_B_CAUSE_B_LINK_EQ_REQ_INT (1 << 13) 1291/* 1292 * OB Vendor message request is granted by the PCIe core Write Zero to clear. 1293 */ 1294#define PCIE_W_INT_GRP_B_CAUSE_B_VENDOR_MSG_GRANT (1 << 14) 1295/* CPL timeout from the PCIe core inidication. Write Zero to clear */ 1296#define PCIE_W_INT_GRP_B_CAUSE_B_CMP_TIME_OUT (1 << 15) 1297/* 1298 * Slave Response Composer Lookup Error 1299 * Indicates that an overflow occurred in a lookup table of the Inbound 1300 * responses. This indicates that there was a violation of the number of 1301 * outstanding NP requests issued for the Outbound direction. Write zero to 1302 * clear 1303 */ 1304#define PCIE_W_INT_GRP_B_CAUSE_B_RADMX_CMPOSER_LOOKUP_ERR (1 << 16) 1305/* Parity Error */ 1306#define PCIE_W_INT_GRP_B_CAUSE_B_PARITY_ERROR_CORE (1 << 17) 1307 1308/**** control_B register ****/ 1309/* When Clear_on_Read =1, all bits of the Cause register are cleared on read. */ 1310#define PCIE_W_INT_GRP_B_CONTROL_B_CLEAR_ON_READ (1 << 0) 1311/* 1312 * (Must be set only when MSIX is enabled.) 1313 * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its 1314 * corresponding bit in the Mask register is set, masking future interrupts. 1315 */ 1316#define PCIE_W_INT_GRP_B_CONTROL_B_AUTO_MASK (1 << 1) 1317/* 1318 * Auto_Clear (RW) 1319 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared 1320 * after MSI-X is acknowledged. Must be used only if MSI-X is enabled. 1321 */ 1322#define PCIE_W_INT_GRP_B_CONTROL_B_AUTO_CLEAR (1 << 2) 1323/* 1324 * When Set_on_Posedge =1, the bits in the interrupt Cause register are set on 1325 * the posedge of the interrupt source, i.e., when Interrupt Source =1 and 1326 * Interrupt Status = 0. 1327 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when 1328 * Interrupt Source =1. 1329 */ 1330#define PCIE_W_INT_GRP_B_CONTROL_B_SET_ON_POSEDGE (1 << 3) 1331/* 1332 * When Moderation_Reset =1, all Moderation timers associated with the interrupt 1333 * cause bits are cleared to 0, enabling an immediate interrupt assertion if any 1334 * unmasked cause bit is set to 1. This bit is self-negated. 1335 */ 1336#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RST (1 << 4) 1337/* 1338 * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to 1339 * 1 when the associated summary bit in this group is used to generate a single 1340 * MSI-X for this group. 1341 */ 1342#define PCIE_W_INT_GRP_B_CONTROL_B_MASK_MSI_X (1 << 5) 1343/* MSI-X AWID value. Same ID for all cause bits. */ 1344#define PCIE_W_INT_GRP_B_CONTROL_B_AWID_MASK 0x00000F00 1345#define PCIE_W_INT_GRP_B_CONTROL_B_AWID_SHIFT 8 1346/* 1347 * This value determines the interval between interrupts. Writing ZERO disables 1348 * Moderation. 1349 */ 1350#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_INTV_MASK 0x00FF0000 1351#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_INTV_SHIFT 16 1352/* 1353 * This value determines the Moderation_Timer_Clock speed. 1354 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS. 1355 * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS. 1356 * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS. 1357 */ 1358#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RES_MASK 0x0F000000 1359#define PCIE_W_INT_GRP_B_CONTROL_B_MOD_RES_SHIFT 24 1360 1361/**** cause_C register ****/ 1362/* VPD interrupt, ot read/write frpm EEPROM */ 1363#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_VPD_INT_FUNC_MASK 0x0000000F 1364#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_VPD_INT_FUNC_SHIFT 0 1365/* flr PF active */ 1366#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_FLR_PF_ACTIVE_MASK 0x000000F0 1367#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_FLR_PF_ACTIVE_SHIFT 4 1368/* System ERR RC. */ 1369#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_SYS_ERR_RC_MASK 0x00000F00 1370#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_SYS_ERR_RC_SHIFT 8 1371/* AER RC INT */ 1372#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_INT_MASK 0x0000F000 1373#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_INT_SHIFT 12 1374/* AER RC MSI */ 1375#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_MSI_MASK 0x000F0000 1376#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_AER_RC_ERR_MSI_SHIFT 16 1377/* PME MSI */ 1378#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_MSI_MASK 0x00F00000 1379#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_MSI_SHIFT 20 1380/* PME int */ 1381#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_INT_MASK 0x0F000000 1382#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_CFG_PME_INT_SHIFT 24 1383/* SB overflow */ 1384#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_RADM_QOVERFLOW (1 << 28) 1385/* ecrc was injected through the diag_ctrl bus */ 1386#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_ECRC_INJECTED (1 << 29) 1387/* lcrc was injected through the diag_ctrl bus */ 1388#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_LCRC_INJECTED (1 << 30) 1389/* lcrc was injected through the diag_ctrl bus */ 1390#define PCIE_W_INTERRUPT_GRP_C_INT_CAUSE_GRP_C_RSRVD (1 << 31) 1391 1392/**** control_C register ****/ 1393/* When Clear_on_Read =1, all bits of Cause register are cleared on read. */ 1394#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_CLEAR_ON_READ (1 << 0) 1395/* 1396 * (Must be set only when MSIX is enabled.) 1397 * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its 1398 * corresponding bit in the Mask register is set, masking future interrupts. 1399 */ 1400#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AUTO_MASK (1 << 1) 1401/* 1402 * Auto_Clear (RW) 1403 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared 1404 * after MSI-X is acknowledged. Must be used only if MSI-X is enabled. 1405 */ 1406#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AUTO_CLEAR (1 << 2) 1407/* 1408 * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on 1409 * the posedge of the interrupt source, i.e., when interrupt source =1 and 1410 * Interrupt Status = 0. 1411 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when 1412 * interrupt source =1. 1413 */ 1414#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_SET_ON_POSEDGE (1 << 3) 1415/* 1416 * When Moderation_Reset =1, all Moderation timers associated with the interrupt 1417 * cause bits are cleared to 0, enabling immediate interrupt assertion if any 1418 * unmasked cause bit is set to 1. This bit is self-negated. 1419 */ 1420#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RST (1 << 4) 1421/* 1422 * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to 1423 * 1 when the associated summary bit in this group is used to generate a single 1424 * MSI-X for this group. 1425 */ 1426#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MASK_MSI_X (1 << 5) 1427/* MSI-X AWID value. Same ID for all cause bits. */ 1428#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AWID_MASK 0x00000F00 1429#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_AWID_SHIFT 8 1430/* 1431 * This value determines the interval between interrupts; writing ZERO disables 1432 * Moderation. 1433 */ 1434#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_INTV_MASK 0x00FF0000 1435#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_INTV_SHIFT 16 1436/* 1437 * This value determines the Moderation_Timer_Clock speed. 1438 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS. 1439 * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS. 1440 * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS. 1441 */ 1442#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RES_MASK 0x0F000000 1443#define PCIE_W_INTERRUPT_GRP_C_INT_CONTROL_GRP_C_MOD_RES_SHIFT 24 1444 1445/**** control_D register ****/ 1446/* When Clear_on_Read =1, all bits of Cause register are cleared on read. */ 1447#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_CLEAR_ON_READ (1 << 0) 1448/* 1449 * (Must be set only when MSIX is enabled.) 1450 * When Auto-Mask =1 and an MSI-X ACK for this bit is received, its 1451 * corresponding bit in the Mask register is set, masking future interrupts. 1452 */ 1453#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AUTO_MASK (1 << 1) 1454/* 1455 * Auto_Clear (RW) 1456 * When Auto-Clear =1, the bits in the Interrupt Cause register are auto-cleared 1457 * after MSI-X is acknowledged. Must be used only if MSI-X is enabled. 1458 */ 1459#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AUTO_CLEAR (1 << 2) 1460/* 1461 * When Set_on_Posedge =1, the bits in the Interrupt Cause register are set on 1462 * the posedge of the interrupt source, i.e., when interrupt source =1 and 1463 * Interrupt Status = 0. 1464 * When Set_on_Posedge =0, the bits in the Interrupt Cause register are set when 1465 * interrupt source =1. 1466 */ 1467#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_SET_ON_POSEDGE (1 << 3) 1468/* 1469 * When Moderation_Reset =1, all Moderation timers associated with the interrupt 1470 * cause bits are cleared to 0, enabling immediate interrupt assertion if any 1471 * unmasked cause bit is set to 1. This bit is self-negated. 1472 */ 1473#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RST (1 << 4) 1474/* 1475 * When mask_msi_x =1, no MSI-X from this group is sent. This bit must be set to 1476 * 1 when the associated summary bit in this group is used to generate a single 1477 * MSI-X for this group. 1478 */ 1479#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MASK_MSI_X (1 << 5) 1480/* MSI-X AWID value. Same ID for all cause bits. */ 1481#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AWID_MASK 0x00000F00 1482#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_AWID_SHIFT 8 1483/* 1484 * This value determines the interval between interrupts; writing ZERO disables 1485 * Moderation. 1486 */ 1487#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_INTV_MASK 0x00FF0000 1488#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_INTV_SHIFT 16 1489/* 1490 * This value determines the Moderation_Timer_Clock speed. 1491 * 0- Moderation-timer is decremented every 1x256 SB clock cycles ~1uS. 1492 * 1- Moderation-timer is decremented every 2x256 SB clock cycles ~2uS. 1493 * N- Moderation-timer is decremented every Nx256 SB clock cycles ~(N+1) uS. 1494 */ 1495#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RES_MASK 0x0F000000 1496#define PCIE_W_INTERRUPT_GRP_D_INT_CONTROL_GRP_D_MOD_RES_SHIFT 24 1497#ifdef __cplusplus 1498} 1499#endif 1500 1501#endif /* __AL_HAL_PCIE_W_REG_H */ 1502 1503/** @} end of ... group */ 1504 1505 1506