pci.h revision 361200
1/*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/compat/linuxkpi/common/include/linux/pci.h 361200 2020-05-18 09:34:41Z hselasky $ 30 */ 31#ifndef _LINUX_PCI_H_ 32#define _LINUX_PCI_H_ 33 34#define CONFIG_PCI_MSI 35 36#include <linux/types.h> 37 38#include <sys/param.h> 39#include <sys/bus.h> 40#include <sys/nv.h> 41#include <sys/pciio.h> 42#include <sys/rman.h> 43#include <sys/bus.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include <dev/pci/pci_private.h> 47 48#include <machine/resource.h> 49 50#include <linux/list.h> 51#include <linux/dmapool.h> 52#include <linux/dma-mapping.h> 53#include <linux/compiler.h> 54#include <linux/errno.h> 55#include <asm/atomic.h> 56#include <linux/device.h> 57 58struct pci_device_id { 59 uint32_t vendor; 60 uint32_t device; 61 uint32_t subvendor; 62 uint32_t subdevice; 63 uint32_t class; 64 uint32_t class_mask; 65 uintptr_t driver_data; 66}; 67 68#define MODULE_DEVICE_TABLE(bus, table) 69 70#define PCI_BASE_CLASS_DISPLAY 0x03 71#define PCI_CLASS_DISPLAY_VGA 0x0300 72#define PCI_CLASS_DISPLAY_OTHER 0x0380 73#define PCI_BASE_CLASS_BRIDGE 0x06 74#define PCI_CLASS_BRIDGE_ISA 0x0601 75 76#define PCI_ANY_ID -1U 77#define PCI_VENDOR_ID_APPLE 0x106b 78#define PCI_VENDOR_ID_ASUSTEK 0x1043 79#define PCI_VENDOR_ID_ATI 0x1002 80#define PCI_VENDOR_ID_DELL 0x1028 81#define PCI_VENDOR_ID_HP 0x103c 82#define PCI_VENDOR_ID_IBM 0x1014 83#define PCI_VENDOR_ID_INTEL 0x8086 84#define PCI_VENDOR_ID_MELLANOX 0x15b3 85#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 86#define PCI_VENDOR_ID_SERVERWORKS 0x1166 87#define PCI_VENDOR_ID_SONY 0x104d 88#define PCI_VENDOR_ID_TOPSPIN 0x1867 89#define PCI_VENDOR_ID_VIA 0x1106 90#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 91#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 92#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 93#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 94#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 95#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 96#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 97#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 98#define PCI_SUBDEVICE_ID_QEMU 0x1100 99 100#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 101#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 102#define PCI_FUNC(devfn) ((devfn) & 0x07) 103#define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 104 105#define PCI_VDEVICE(_vendor, _device) \ 106 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108#define PCI_DEVICE(_vendor, _device) \ 109 .vendor = (_vendor), .device = (_device), \ 110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 111 112#define to_pci_dev(n) container_of(n, struct pci_dev, dev) 113 114#define PCI_VENDOR_ID PCIR_DEVVENDOR 115#define PCI_COMMAND PCIR_COMMAND 116#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 117#define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 118#define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 119#define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 120#define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 121#define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 122#define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 123#define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 124#define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 125#define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 126#define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 127#define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 128#define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 129#define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 130#define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 131#define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 132#define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 133#define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 134#define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 135#define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 136#define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 137#define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 138#define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 139#define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 140#define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 141#define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 142#define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 143#define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 144#define PCI_EXP_LNKCAP_SLS_8_0GB 0x04 /* Supported Link Speed 8.0GT/s */ 145#define PCI_EXP_LNKCAP_SLS_16_0GB 0x08 /* Supported Link Speed 16.0GT/s */ 146#define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 147#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 148#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 149#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 150#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x10 /* Supported Link Speed 16.0GT/s */ 151 152#define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 153#define PCI_EXP_LNKCAP_CLKPM 0x00040000 154#define PCI_EXP_DEVSTA_TRPND 0x0020 155 156#define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 157#define IORESOURCE_IO (1 << SYS_RES_IOPORT) 158#define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 159 160enum pci_bus_speed { 161 PCI_SPEED_UNKNOWN = -1, 162 PCIE_SPEED_2_5GT, 163 PCIE_SPEED_5_0GT, 164 PCIE_SPEED_8_0GT, 165 PCIE_SPEED_16_0GT, 166}; 167 168enum pcie_link_width { 169 PCIE_LNK_WIDTH_RESRV = 0x00, 170 PCIE_LNK_X1 = 0x01, 171 PCIE_LNK_X2 = 0x02, 172 PCIE_LNK_X4 = 0x04, 173 PCIE_LNK_X8 = 0x08, 174 PCIE_LNK_X12 = 0x0c, 175 PCIE_LNK_X16 = 0x10, 176 PCIE_LNK_X32 = 0x20, 177 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 178}; 179 180typedef int pci_power_t; 181 182#define PCI_D0 PCI_POWERSTATE_D0 183#define PCI_D1 PCI_POWERSTATE_D1 184#define PCI_D2 PCI_POWERSTATE_D2 185#define PCI_D3hot PCI_POWERSTATE_D3 186#define PCI_D3cold 4 187 188#define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 189 190struct pci_dev; 191 192struct pci_driver { 193 struct list_head links; 194 char *name; 195 const struct pci_device_id *id_table; 196 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 197 void (*remove)(struct pci_dev *dev); 198 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 199 int (*resume) (struct pci_dev *dev); /* Device woken up */ 200 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 201 driver_t bsddriver; 202 devclass_t bsdclass; 203 struct device_driver driver; 204 const struct pci_error_handlers *err_handler; 205 bool isdrm; 206 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 207 const nvlist_t *pf_config); 208 void (*bsd_iov_uninit)(device_t dev); 209 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 210 const nvlist_t *vf_config); 211}; 212 213struct pci_bus { 214 struct pci_dev *self; 215 int number; 216}; 217 218extern struct list_head pci_drivers; 219extern struct list_head pci_devices; 220extern spinlock_t pci_lock; 221 222#define __devexit_p(x) x 223 224struct pci_dev { 225 struct device dev; 226 struct list_head links; 227 struct pci_driver *pdrv; 228 struct pci_bus *bus; 229 uint64_t dma_mask; 230 uint16_t device; 231 uint16_t vendor; 232 uint16_t subsystem_vendor; 233 uint16_t subsystem_device; 234 unsigned int irq; 235 unsigned int devfn; 236 uint32_t class; 237 uint8_t revision; 238 bool msi_enabled; 239}; 240 241static inline struct resource_list_entry * 242linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 243{ 244 struct pci_devinfo *dinfo; 245 struct resource_list *rl; 246 247 dinfo = device_get_ivars(pdev->dev.bsddev); 248 rl = &dinfo->resources; 249 return resource_list_find(rl, type, rid); 250} 251 252static inline struct resource_list_entry * 253linux_pci_get_bar(struct pci_dev *pdev, int bar) 254{ 255 struct resource_list_entry *rle; 256 257 bar = PCIR_BAR(bar); 258 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 259 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 260 return (rle); 261} 262 263static inline struct device * 264linux_pci_find_irq_dev(unsigned int irq) 265{ 266 struct pci_dev *pdev; 267 struct device *found; 268 269 found = NULL; 270 spin_lock(&pci_lock); 271 list_for_each_entry(pdev, &pci_devices, links) { 272 if (irq == pdev->dev.irq || 273 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 274 found = &pdev->dev; 275 break; 276 } 277 } 278 spin_unlock(&pci_lock); 279 return (found); 280} 281 282static inline unsigned long 283pci_resource_start(struct pci_dev *pdev, int bar) 284{ 285 struct resource_list_entry *rle; 286 287 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 288 return (0); 289 return rle->start; 290} 291 292static inline unsigned long 293pci_resource_len(struct pci_dev *pdev, int bar) 294{ 295 struct resource_list_entry *rle; 296 297 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 298 return (0); 299 return rle->count; 300} 301 302static inline int 303pci_resource_type(struct pci_dev *pdev, int bar) 304{ 305 struct pci_map *pm; 306 307 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 308 if (!pm) 309 return (-1); 310 311 if (PCI_BAR_IO(pm->pm_value)) 312 return (SYS_RES_IOPORT); 313 else 314 return (SYS_RES_MEMORY); 315} 316 317/* 318 * All drivers just seem to want to inspect the type not flags. 319 */ 320static inline int 321pci_resource_flags(struct pci_dev *pdev, int bar) 322{ 323 int type; 324 325 type = pci_resource_type(pdev, bar); 326 if (type < 0) 327 return (0); 328 return (1 << type); 329} 330 331static inline const char * 332pci_name(struct pci_dev *d) 333{ 334 335 return device_get_desc(d->dev.bsddev); 336} 337 338static inline void * 339pci_get_drvdata(struct pci_dev *pdev) 340{ 341 342 return dev_get_drvdata(&pdev->dev); 343} 344 345static inline void 346pci_set_drvdata(struct pci_dev *pdev, void *data) 347{ 348 349 dev_set_drvdata(&pdev->dev, data); 350} 351 352static inline int 353pci_enable_device(struct pci_dev *pdev) 354{ 355 356 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 357 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 358 return (0); 359} 360 361static inline void 362pci_disable_device(struct pci_dev *pdev) 363{ 364 365 pci_disable_busmaster(pdev->dev.bsddev); 366} 367 368static inline int 369pci_set_master(struct pci_dev *pdev) 370{ 371 372 pci_enable_busmaster(pdev->dev.bsddev); 373 return (0); 374} 375 376static inline int 377pci_set_power_state(struct pci_dev *pdev, int state) 378{ 379 380 pci_set_powerstate(pdev->dev.bsddev, state); 381 return (0); 382} 383 384static inline int 385pci_clear_master(struct pci_dev *pdev) 386{ 387 388 pci_disable_busmaster(pdev->dev.bsddev); 389 return (0); 390} 391 392static inline int 393pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 394{ 395 int rid; 396 int type; 397 398 type = pci_resource_type(pdev, bar); 399 if (type < 0) 400 return (-ENODEV); 401 rid = PCIR_BAR(bar); 402 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 403 RF_ACTIVE) == NULL) 404 return (-EINVAL); 405 return (0); 406} 407 408static inline void 409pci_release_region(struct pci_dev *pdev, int bar) 410{ 411 struct resource_list_entry *rle; 412 413 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 414 return; 415 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 416} 417 418static inline void 419pci_release_regions(struct pci_dev *pdev) 420{ 421 int i; 422 423 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 424 pci_release_region(pdev, i); 425} 426 427static inline int 428pci_request_regions(struct pci_dev *pdev, const char *res_name) 429{ 430 int error; 431 int i; 432 433 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 434 error = pci_request_region(pdev, i, res_name); 435 if (error && error != -ENODEV) { 436 pci_release_regions(pdev); 437 return (error); 438 } 439 } 440 return (0); 441} 442 443static inline void 444pci_disable_msix(struct pci_dev *pdev) 445{ 446 447 pci_release_msi(pdev->dev.bsddev); 448 449 /* 450 * The MSIX IRQ numbers associated with this PCI device are no 451 * longer valid and might be re-assigned. Make sure 452 * linux_pci_find_irq_dev() does no longer see them by 453 * resetting their references to zero: 454 */ 455 pdev->dev.irq_start = 0; 456 pdev->dev.irq_end = 0; 457} 458 459#define pci_disable_msi(pdev) \ 460 linux_pci_disable_msi(pdev) 461 462static inline void 463linux_pci_disable_msi(struct pci_dev *pdev) 464{ 465 466 pci_release_msi(pdev->dev.bsddev); 467 468 pdev->dev.irq_start = 0; 469 pdev->dev.irq_end = 0; 470 pdev->irq = pdev->dev.irq; 471 pdev->msi_enabled = false; 472} 473 474static inline bus_addr_t 475pci_bus_address(struct pci_dev *pdev, int bar) 476{ 477 478 return (pci_resource_start(pdev, bar)); 479} 480 481#define PCI_CAP_ID_EXP PCIY_EXPRESS 482#define PCI_CAP_ID_PCIX PCIY_PCIX 483#define PCI_CAP_ID_AGP PCIY_AGP 484#define PCI_CAP_ID_PM PCIY_PMG 485 486#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 487#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 488#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 489#define PCI_EXP_LNKCTL PCIER_LINK_CTL 490#define PCI_EXP_LNKSTA PCIER_LINK_STA 491 492static inline int 493pci_find_capability(struct pci_dev *pdev, int capid) 494{ 495 int reg; 496 497 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 498 return (0); 499 return (reg); 500} 501 502static inline int pci_pcie_cap(struct pci_dev *dev) 503{ 504 return pci_find_capability(dev, PCI_CAP_ID_EXP); 505} 506 507 508static inline int 509pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 510{ 511 512 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 513 return (0); 514} 515 516static inline int 517pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 518{ 519 520 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 521 return (0); 522} 523 524static inline int 525pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 526{ 527 528 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 529 return (0); 530} 531 532static inline int 533pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 534{ 535 536 pci_write_config(pdev->dev.bsddev, where, val, 1); 537 return (0); 538} 539 540static inline int 541pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 542{ 543 544 pci_write_config(pdev->dev.bsddev, where, val, 2); 545 return (0); 546} 547 548static inline int 549pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 550{ 551 552 pci_write_config(pdev->dev.bsddev, where, val, 4); 553 return (0); 554} 555 556int linux_pci_register_driver(struct pci_driver *pdrv); 557int linux_pci_register_drm_driver(struct pci_driver *pdrv); 558void linux_pci_unregister_driver(struct pci_driver *pdrv); 559 560#define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 561#define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 562 563struct msix_entry { 564 int entry; 565 int vector; 566}; 567 568/* 569 * Enable msix, positive errors indicate actual number of available 570 * vectors. Negative errors are failures. 571 * 572 * NB: define added to prevent this definition of pci_enable_msix from 573 * clashing with the native FreeBSD version. 574 */ 575#define pci_enable_msix(...) \ 576 linux_pci_enable_msix(__VA_ARGS__) 577 578static inline int 579pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 580{ 581 struct resource_list_entry *rle; 582 int error; 583 int avail; 584 int i; 585 586 avail = pci_msix_count(pdev->dev.bsddev); 587 if (avail < nreq) { 588 if (avail == 0) 589 return -EINVAL; 590 return avail; 591 } 592 avail = nreq; 593 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 594 return error; 595 /* 596 * Handle case where "pci_alloc_msix()" may allocate less 597 * interrupts than available and return with no error: 598 */ 599 if (avail < nreq) { 600 pci_release_msi(pdev->dev.bsddev); 601 return avail; 602 } 603 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 604 pdev->dev.irq_start = rle->start; 605 pdev->dev.irq_end = rle->start + avail; 606 for (i = 0; i < nreq; i++) 607 entries[i].vector = pdev->dev.irq_start + i; 608 return (0); 609} 610 611#define pci_enable_msix_range(...) \ 612 linux_pci_enable_msix_range(__VA_ARGS__) 613 614static inline int 615pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 616 int minvec, int maxvec) 617{ 618 int nvec = maxvec; 619 int rc; 620 621 if (maxvec < minvec) 622 return (-ERANGE); 623 624 do { 625 rc = pci_enable_msix(dev, entries, nvec); 626 if (rc < 0) { 627 return (rc); 628 } else if (rc > 0) { 629 if (rc < minvec) 630 return (-ENOSPC); 631 nvec = rc; 632 } 633 } while (rc); 634 return (nvec); 635} 636 637#define pci_enable_msi(pdev) \ 638 linux_pci_enable_msi(pdev) 639 640static inline int 641pci_enable_msi(struct pci_dev *pdev) 642{ 643 struct resource_list_entry *rle; 644 int error; 645 int avail; 646 647 avail = pci_msi_count(pdev->dev.bsddev); 648 if (avail < 1) 649 return -EINVAL; 650 651 avail = 1; /* this function only enable one MSI IRQ */ 652 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 653 return error; 654 655 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 656 pdev->dev.irq_start = rle->start; 657 pdev->dev.irq_end = rle->start + avail; 658 pdev->irq = rle->start; 659 pdev->msi_enabled = true; 660 return (0); 661} 662 663static inline int 664pci_channel_offline(struct pci_dev *pdev) 665{ 666 667 return (pci_get_vendor(pdev->dev.bsddev) == PCIV_INVALID); 668} 669 670static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 671{ 672 return -ENODEV; 673} 674static inline void pci_disable_sriov(struct pci_dev *dev) 675{ 676} 677 678#define DEFINE_PCI_DEVICE_TABLE(_table) \ 679 const struct pci_device_id _table[] __devinitdata 680 681 682/* XXX This should not be necessary. */ 683#define pcix_set_mmrbc(d, v) 0 684#define pcix_get_max_mmrbc(d) 0 685#define pcie_set_readrq(d, v) 0 686 687#define PCI_DMA_BIDIRECTIONAL 0 688#define PCI_DMA_TODEVICE 1 689#define PCI_DMA_FROMDEVICE 2 690#define PCI_DMA_NONE 3 691 692#define pci_pool dma_pool 693#define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 694#define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 695#define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 696#define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 697 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 698#define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 699 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 700 _size, _vaddr, _dma_handle) 701#define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 702 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 703 _sg, _nents, (enum dma_data_direction)_dir) 704#define pci_map_single(_hwdev, _ptr, _size, _dir) \ 705 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 706 (_ptr), (_size), (enum dma_data_direction)_dir) 707#define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 708 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 709 _addr, _size, (enum dma_data_direction)_dir) 710#define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 711 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 712 _sg, _nents, (enum dma_data_direction)_dir) 713#define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 714 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 715 _offset, _size, (enum dma_data_direction)_dir) 716#define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 717 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 718 _dma_address, _size, (enum dma_data_direction)_dir) 719#define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 720#define pci_dma_mapping_error(_pdev, _dma_addr) \ 721 dma_mapping_error(&(_pdev)->dev, _dma_addr) 722#define pci_set_consistent_dma_mask(_pdev, _mask) \ 723 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 724#define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 725#define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 726#define pci_unmap_addr dma_unmap_addr 727#define pci_unmap_addr_set dma_unmap_addr_set 728#define pci_unmap_len dma_unmap_len 729#define pci_unmap_len_set dma_unmap_len_set 730 731typedef unsigned int __bitwise pci_channel_state_t; 732typedef unsigned int __bitwise pci_ers_result_t; 733 734enum pci_channel_state { 735 pci_channel_io_normal = 1, 736 pci_channel_io_frozen = 2, 737 pci_channel_io_perm_failure = 3, 738}; 739 740enum pci_ers_result { 741 PCI_ERS_RESULT_NONE = 1, 742 PCI_ERS_RESULT_CAN_RECOVER = 2, 743 PCI_ERS_RESULT_NEED_RESET = 3, 744 PCI_ERS_RESULT_DISCONNECT = 4, 745 PCI_ERS_RESULT_RECOVERED = 5, 746}; 747 748 749/* PCI bus error event callbacks */ 750struct pci_error_handlers { 751 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 752 enum pci_channel_state error); 753 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 754 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 755 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 756 void (*resume)(struct pci_dev *dev); 757}; 758 759/* FreeBSD does not support SRIOV - yet */ 760static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 761{ 762 return dev; 763} 764 765static inline bool pci_is_pcie(struct pci_dev *dev) 766{ 767 return !!pci_pcie_cap(dev); 768} 769 770static inline u16 pcie_flags_reg(struct pci_dev *dev) 771{ 772 int pos; 773 u16 reg16; 774 775 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 776 if (!pos) 777 return 0; 778 779 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 780 781 return reg16; 782} 783 784 785static inline int pci_pcie_type(struct pci_dev *dev) 786{ 787 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 788} 789 790static inline int pcie_cap_version(struct pci_dev *dev) 791{ 792 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 793} 794 795static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 796{ 797 int type = pci_pcie_type(dev); 798 799 return pcie_cap_version(dev) > 1 || 800 type == PCI_EXP_TYPE_ROOT_PORT || 801 type == PCI_EXP_TYPE_ENDPOINT || 802 type == PCI_EXP_TYPE_LEG_END; 803} 804 805static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 806{ 807 return true; 808} 809 810static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 811{ 812 int type = pci_pcie_type(dev); 813 814 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 815 (type == PCI_EXP_TYPE_DOWNSTREAM && 816 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 817} 818 819static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 820{ 821 int type = pci_pcie_type(dev); 822 823 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 824 type == PCI_EXP_TYPE_RC_EC; 825} 826 827static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 828{ 829 if (!pci_is_pcie(dev)) 830 return false; 831 832 switch (pos) { 833 case PCI_EXP_FLAGS_TYPE: 834 return true; 835 case PCI_EXP_DEVCAP: 836 case PCI_EXP_DEVCTL: 837 case PCI_EXP_DEVSTA: 838 return pcie_cap_has_devctl(dev); 839 case PCI_EXP_LNKCAP: 840 case PCI_EXP_LNKCTL: 841 case PCI_EXP_LNKSTA: 842 return pcie_cap_has_lnkctl(dev); 843 case PCI_EXP_SLTCAP: 844 case PCI_EXP_SLTCTL: 845 case PCI_EXP_SLTSTA: 846 return pcie_cap_has_sltctl(dev); 847 case PCI_EXP_RTCTL: 848 case PCI_EXP_RTCAP: 849 case PCI_EXP_RTSTA: 850 return pcie_cap_has_rtctl(dev); 851 case PCI_EXP_DEVCAP2: 852 case PCI_EXP_DEVCTL2: 853 case PCI_EXP_LNKCAP2: 854 case PCI_EXP_LNKCTL2: 855 case PCI_EXP_LNKSTA2: 856 return pcie_cap_version(dev) > 1; 857 default: 858 return false; 859 } 860} 861 862static inline int 863pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 864{ 865 if (pos & 3) 866 return -EINVAL; 867 868 if (!pcie_capability_reg_implemented(dev, pos)) 869 return -EINVAL; 870 871 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 872} 873 874static inline int 875pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 876{ 877 if (pos & 3) 878 return -EINVAL; 879 880 if (!pcie_capability_reg_implemented(dev, pos)) 881 return -EINVAL; 882 883 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 884} 885 886static inline int 887pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 888{ 889 if (pos & 1) 890 return -EINVAL; 891 892 if (!pcie_capability_reg_implemented(dev, pos)) 893 return 0; 894 895 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 896} 897 898static inline int pcie_get_minimum_link(struct pci_dev *dev, 899 enum pci_bus_speed *speed, enum pcie_link_width *width) 900{ 901 *speed = PCI_SPEED_UNKNOWN; 902 *width = PCIE_LNK_WIDTH_UNKNOWN; 903 return (0); 904} 905 906static inline int 907pci_num_vf(struct pci_dev *dev) 908{ 909 return (0); 910} 911 912static inline enum pci_bus_speed 913pcie_get_speed_cap(struct pci_dev *dev) 914{ 915 device_t root; 916 uint32_t lnkcap, lnkcap2; 917 int error, pos; 918 919 root = device_get_parent(dev->dev.bsddev); 920 if (root == NULL) 921 return (PCI_SPEED_UNKNOWN); 922 root = device_get_parent(root); 923 if (root == NULL) 924 return (PCI_SPEED_UNKNOWN); 925 root = device_get_parent(root); 926 if (root == NULL) 927 return (PCI_SPEED_UNKNOWN); 928 929 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 930 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 931 return (PCI_SPEED_UNKNOWN); 932 933 if ((error = pci_find_cap(root, PCIY_EXPRESS, &pos)) != 0) 934 return (PCI_SPEED_UNKNOWN); 935 936 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 937 938 if (lnkcap2) { /* PCIe r3.0-compliant */ 939 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 940 return (PCIE_SPEED_2_5GT); 941 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 942 return (PCIE_SPEED_5_0GT); 943 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 944 return (PCIE_SPEED_8_0GT); 945 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 946 return (PCIE_SPEED_16_0GT); 947 } else { /* pre-r3.0 */ 948 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 949 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 950 return (PCIE_SPEED_2_5GT); 951 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 952 return (PCIE_SPEED_5_0GT); 953 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 954 return (PCIE_SPEED_8_0GT); 955 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 956 return (PCIE_SPEED_16_0GT); 957 } 958 return (PCI_SPEED_UNKNOWN); 959} 960 961static inline enum pcie_link_width 962pcie_get_width_cap(struct pci_dev *dev) 963{ 964 uint32_t lnkcap; 965 966 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 967 if (lnkcap) 968 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 969 970 return (PCIE_LNK_WIDTH_UNKNOWN); 971} 972 973static inline int 974pcie_get_mps(struct pci_dev *dev) 975{ 976 return (pci_get_max_payload(dev->dev.bsddev)); 977} 978 979static inline uint32_t 980PCIE_SPEED2MBS_ENC(enum pci_bus_speed spd) 981{ 982 983 switch(spd) { 984 case PCIE_SPEED_16_0GT: 985 return (16000 * 128 / 130); 986 case PCIE_SPEED_8_0GT: 987 return (8000 * 128 / 130); 988 case PCIE_SPEED_5_0GT: 989 return (5000 * 8 / 10); 990 case PCIE_SPEED_2_5GT: 991 return (2500 * 8 / 10); 992 default: 993 return (0); 994 } 995} 996 997static inline uint32_t 998pcie_bandwidth_available(struct pci_dev *pdev, 999 struct pci_dev **limiting, 1000 enum pci_bus_speed *speed, 1001 enum pcie_link_width *width) 1002{ 1003 enum pci_bus_speed nspeed = pcie_get_speed_cap(pdev); 1004 enum pcie_link_width nwidth = pcie_get_width_cap(pdev); 1005 1006 if (speed) 1007 *speed = nspeed; 1008 if (width) 1009 *width = nwidth; 1010 1011 return (nwidth * PCIE_SPEED2MBS_ENC(nspeed)); 1012} 1013 1014#endif /* _LINUX_PCI_H_ */ 1015