pci.h revision 359527
1/*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/compat/linuxkpi/common/include/linux/pci.h 359527 2020-04-01 17:19:27Z kib $ 30 */ 31#ifndef _LINUX_PCI_H_ 32#define _LINUX_PCI_H_ 33 34#define CONFIG_PCI_MSI 35 36#include <linux/types.h> 37 38#include <sys/param.h> 39#include <sys/bus.h> 40#include <sys/nv.h> 41#include <sys/pciio.h> 42#include <sys/rman.h> 43#include <sys/bus.h> 44#include <dev/pci/pcivar.h> 45#include <dev/pci/pcireg.h> 46#include <dev/pci/pci_private.h> 47 48#include <machine/resource.h> 49 50#include <linux/list.h> 51#include <linux/dmapool.h> 52#include <linux/dma-mapping.h> 53#include <linux/compiler.h> 54#include <linux/errno.h> 55#include <asm/atomic.h> 56#include <linux/device.h> 57 58struct pci_device_id { 59 uint32_t vendor; 60 uint32_t device; 61 uint32_t subvendor; 62 uint32_t subdevice; 63 uint32_t class; 64 uint32_t class_mask; 65 uintptr_t driver_data; 66}; 67 68#define MODULE_DEVICE_TABLE(bus, table) 69 70#define PCI_BASE_CLASS_DISPLAY 0x03 71#define PCI_CLASS_DISPLAY_VGA 0x0300 72#define PCI_CLASS_DISPLAY_OTHER 0x0380 73#define PCI_BASE_CLASS_BRIDGE 0x06 74#define PCI_CLASS_BRIDGE_ISA 0x0601 75 76#define PCI_ANY_ID -1U 77#define PCI_VENDOR_ID_APPLE 0x106b 78#define PCI_VENDOR_ID_ASUSTEK 0x1043 79#define PCI_VENDOR_ID_ATI 0x1002 80#define PCI_VENDOR_ID_DELL 0x1028 81#define PCI_VENDOR_ID_HP 0x103c 82#define PCI_VENDOR_ID_IBM 0x1014 83#define PCI_VENDOR_ID_INTEL 0x8086 84#define PCI_VENDOR_ID_MELLANOX 0x15b3 85#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 86#define PCI_VENDOR_ID_SERVERWORKS 0x1166 87#define PCI_VENDOR_ID_SONY 0x104d 88#define PCI_VENDOR_ID_TOPSPIN 0x1867 89#define PCI_VENDOR_ID_VIA 0x1106 90#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 91#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 92#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 93#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 94#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 95#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 96#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 97#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 98#define PCI_SUBDEVICE_ID_QEMU 0x1100 99 100#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 101#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 102#define PCI_FUNC(devfn) ((devfn) & 0x07) 103#define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 104 105#define PCI_VDEVICE(_vendor, _device) \ 106 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 107 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 108#define PCI_DEVICE(_vendor, _device) \ 109 .vendor = (_vendor), .device = (_device), \ 110 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 111 112#define to_pci_dev(n) container_of(n, struct pci_dev, dev) 113 114#define PCI_VENDOR_ID PCIR_DEVVENDOR 115#define PCI_COMMAND PCIR_COMMAND 116#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 117#define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 118#define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 119#define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 120#define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 121#define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 122#define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 123#define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 124#define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 125#define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 126#define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 127#define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 128#define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 129#define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 130#define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 131#define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 132#define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 133#define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 134#define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 135#define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 136#define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 137#define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 138#define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 139#define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 140#define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 141#define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 142#define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 143#define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 144#define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 145#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 146#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 147#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 148 149#define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 150#define PCI_EXP_LNKCAP_CLKPM 0x00040000 151#define PCI_EXP_DEVSTA_TRPND 0x0020 152 153#define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 154#define IORESOURCE_IO (1 << SYS_RES_IOPORT) 155#define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 156 157enum pci_bus_speed { 158 PCI_SPEED_UNKNOWN = -1, 159 PCIE_SPEED_2_5GT, 160 PCIE_SPEED_5_0GT, 161 PCIE_SPEED_8_0GT, 162}; 163 164enum pcie_link_width { 165 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 166}; 167 168typedef int pci_power_t; 169 170#define PCI_D0 PCI_POWERSTATE_D0 171#define PCI_D1 PCI_POWERSTATE_D1 172#define PCI_D2 PCI_POWERSTATE_D2 173#define PCI_D3hot PCI_POWERSTATE_D3 174#define PCI_D3cold 4 175 176#define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 177 178struct pci_dev; 179 180struct pci_driver { 181 struct list_head links; 182 char *name; 183 const struct pci_device_id *id_table; 184 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 185 void (*remove)(struct pci_dev *dev); 186 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 187 int (*resume) (struct pci_dev *dev); /* Device woken up */ 188 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 189 driver_t bsddriver; 190 devclass_t bsdclass; 191 struct device_driver driver; 192 const struct pci_error_handlers *err_handler; 193 bool isdrm; 194 int (*bsd_iov_init)(device_t dev, uint16_t num_vfs, 195 const nvlist_t *pf_config); 196 void (*bsd_iov_uninit)(device_t dev); 197 int (*bsd_iov_add_vf)(device_t dev, uint16_t vfnum, 198 const nvlist_t *vf_config); 199}; 200 201struct pci_bus { 202 struct pci_dev *self; 203 int number; 204}; 205 206extern struct list_head pci_drivers; 207extern struct list_head pci_devices; 208extern spinlock_t pci_lock; 209 210#define __devexit_p(x) x 211 212struct pci_dev { 213 struct device dev; 214 struct list_head links; 215 struct pci_driver *pdrv; 216 struct pci_bus *bus; 217 uint64_t dma_mask; 218 uint16_t device; 219 uint16_t vendor; 220 uint16_t subsystem_vendor; 221 uint16_t subsystem_device; 222 unsigned int irq; 223 unsigned int devfn; 224 uint32_t class; 225 uint8_t revision; 226 bool msi_enabled; 227}; 228 229static inline struct resource_list_entry * 230linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 231{ 232 struct pci_devinfo *dinfo; 233 struct resource_list *rl; 234 235 dinfo = device_get_ivars(pdev->dev.bsddev); 236 rl = &dinfo->resources; 237 return resource_list_find(rl, type, rid); 238} 239 240static inline struct resource_list_entry * 241linux_pci_get_bar(struct pci_dev *pdev, int bar) 242{ 243 struct resource_list_entry *rle; 244 245 bar = PCIR_BAR(bar); 246 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 247 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 248 return (rle); 249} 250 251static inline struct device * 252linux_pci_find_irq_dev(unsigned int irq) 253{ 254 struct pci_dev *pdev; 255 struct device *found; 256 257 found = NULL; 258 spin_lock(&pci_lock); 259 list_for_each_entry(pdev, &pci_devices, links) { 260 if (irq == pdev->dev.irq || 261 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 262 found = &pdev->dev; 263 break; 264 } 265 } 266 spin_unlock(&pci_lock); 267 return (found); 268} 269 270static inline unsigned long 271pci_resource_start(struct pci_dev *pdev, int bar) 272{ 273 struct resource_list_entry *rle; 274 275 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 276 return (0); 277 return rle->start; 278} 279 280static inline unsigned long 281pci_resource_len(struct pci_dev *pdev, int bar) 282{ 283 struct resource_list_entry *rle; 284 285 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 286 return (0); 287 return rle->count; 288} 289 290static inline int 291pci_resource_type(struct pci_dev *pdev, int bar) 292{ 293 struct pci_map *pm; 294 295 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 296 if (!pm) 297 return (-1); 298 299 if (PCI_BAR_IO(pm->pm_value)) 300 return (SYS_RES_IOPORT); 301 else 302 return (SYS_RES_MEMORY); 303} 304 305/* 306 * All drivers just seem to want to inspect the type not flags. 307 */ 308static inline int 309pci_resource_flags(struct pci_dev *pdev, int bar) 310{ 311 int type; 312 313 type = pci_resource_type(pdev, bar); 314 if (type < 0) 315 return (0); 316 return (1 << type); 317} 318 319static inline const char * 320pci_name(struct pci_dev *d) 321{ 322 323 return device_get_desc(d->dev.bsddev); 324} 325 326static inline void * 327pci_get_drvdata(struct pci_dev *pdev) 328{ 329 330 return dev_get_drvdata(&pdev->dev); 331} 332 333static inline void 334pci_set_drvdata(struct pci_dev *pdev, void *data) 335{ 336 337 dev_set_drvdata(&pdev->dev, data); 338} 339 340static inline int 341pci_enable_device(struct pci_dev *pdev) 342{ 343 344 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 345 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 346 return (0); 347} 348 349static inline void 350pci_disable_device(struct pci_dev *pdev) 351{ 352 353 pci_disable_busmaster(pdev->dev.bsddev); 354} 355 356static inline int 357pci_set_master(struct pci_dev *pdev) 358{ 359 360 pci_enable_busmaster(pdev->dev.bsddev); 361 return (0); 362} 363 364static inline int 365pci_set_power_state(struct pci_dev *pdev, int state) 366{ 367 368 pci_set_powerstate(pdev->dev.bsddev, state); 369 return (0); 370} 371 372static inline int 373pci_clear_master(struct pci_dev *pdev) 374{ 375 376 pci_disable_busmaster(pdev->dev.bsddev); 377 return (0); 378} 379 380static inline int 381pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 382{ 383 int rid; 384 int type; 385 386 type = pci_resource_type(pdev, bar); 387 if (type < 0) 388 return (-ENODEV); 389 rid = PCIR_BAR(bar); 390 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 391 RF_ACTIVE) == NULL) 392 return (-EINVAL); 393 return (0); 394} 395 396static inline void 397pci_release_region(struct pci_dev *pdev, int bar) 398{ 399 struct resource_list_entry *rle; 400 401 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 402 return; 403 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 404} 405 406static inline void 407pci_release_regions(struct pci_dev *pdev) 408{ 409 int i; 410 411 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 412 pci_release_region(pdev, i); 413} 414 415static inline int 416pci_request_regions(struct pci_dev *pdev, const char *res_name) 417{ 418 int error; 419 int i; 420 421 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 422 error = pci_request_region(pdev, i, res_name); 423 if (error && error != -ENODEV) { 424 pci_release_regions(pdev); 425 return (error); 426 } 427 } 428 return (0); 429} 430 431static inline void 432pci_disable_msix(struct pci_dev *pdev) 433{ 434 435 pci_release_msi(pdev->dev.bsddev); 436 437 /* 438 * The MSIX IRQ numbers associated with this PCI device are no 439 * longer valid and might be re-assigned. Make sure 440 * linux_pci_find_irq_dev() does no longer see them by 441 * resetting their references to zero: 442 */ 443 pdev->dev.irq_start = 0; 444 pdev->dev.irq_end = 0; 445} 446 447#define pci_disable_msi(pdev) \ 448 linux_pci_disable_msi(pdev) 449 450static inline void 451linux_pci_disable_msi(struct pci_dev *pdev) 452{ 453 454 pci_release_msi(pdev->dev.bsddev); 455 456 pdev->dev.irq_start = 0; 457 pdev->dev.irq_end = 0; 458 pdev->irq = pdev->dev.irq; 459 pdev->msi_enabled = false; 460} 461 462static inline bus_addr_t 463pci_bus_address(struct pci_dev *pdev, int bar) 464{ 465 466 return (pci_resource_start(pdev, bar)); 467} 468 469#define PCI_CAP_ID_EXP PCIY_EXPRESS 470#define PCI_CAP_ID_PCIX PCIY_PCIX 471#define PCI_CAP_ID_AGP PCIY_AGP 472#define PCI_CAP_ID_PM PCIY_PMG 473 474#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 475#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 476#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 477#define PCI_EXP_LNKCTL PCIER_LINK_CTL 478#define PCI_EXP_LNKSTA PCIER_LINK_STA 479 480static inline int 481pci_find_capability(struct pci_dev *pdev, int capid) 482{ 483 int reg; 484 485 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 486 return (0); 487 return (reg); 488} 489 490static inline int pci_pcie_cap(struct pci_dev *dev) 491{ 492 return pci_find_capability(dev, PCI_CAP_ID_EXP); 493} 494 495 496static inline int 497pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 498{ 499 500 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 501 return (0); 502} 503 504static inline int 505pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 506{ 507 508 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 509 return (0); 510} 511 512static inline int 513pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 514{ 515 516 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 517 return (0); 518} 519 520static inline int 521pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 522{ 523 524 pci_write_config(pdev->dev.bsddev, where, val, 1); 525 return (0); 526} 527 528static inline int 529pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 530{ 531 532 pci_write_config(pdev->dev.bsddev, where, val, 2); 533 return (0); 534} 535 536static inline int 537pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 538{ 539 540 pci_write_config(pdev->dev.bsddev, where, val, 4); 541 return (0); 542} 543 544int linux_pci_register_driver(struct pci_driver *pdrv); 545int linux_pci_register_drm_driver(struct pci_driver *pdrv); 546void linux_pci_unregister_driver(struct pci_driver *pdrv); 547 548#define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 549#define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 550 551struct msix_entry { 552 int entry; 553 int vector; 554}; 555 556/* 557 * Enable msix, positive errors indicate actual number of available 558 * vectors. Negative errors are failures. 559 * 560 * NB: define added to prevent this definition of pci_enable_msix from 561 * clashing with the native FreeBSD version. 562 */ 563#define pci_enable_msix(...) \ 564 linux_pci_enable_msix(__VA_ARGS__) 565 566static inline int 567pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 568{ 569 struct resource_list_entry *rle; 570 int error; 571 int avail; 572 int i; 573 574 avail = pci_msix_count(pdev->dev.bsddev); 575 if (avail < nreq) { 576 if (avail == 0) 577 return -EINVAL; 578 return avail; 579 } 580 avail = nreq; 581 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 582 return error; 583 /* 584 * Handle case where "pci_alloc_msix()" may allocate less 585 * interrupts than available and return with no error: 586 */ 587 if (avail < nreq) { 588 pci_release_msi(pdev->dev.bsddev); 589 return avail; 590 } 591 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 592 pdev->dev.irq_start = rle->start; 593 pdev->dev.irq_end = rle->start + avail; 594 for (i = 0; i < nreq; i++) 595 entries[i].vector = pdev->dev.irq_start + i; 596 return (0); 597} 598 599#define pci_enable_msix_range(...) \ 600 linux_pci_enable_msix_range(__VA_ARGS__) 601 602static inline int 603pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 604 int minvec, int maxvec) 605{ 606 int nvec = maxvec; 607 int rc; 608 609 if (maxvec < minvec) 610 return (-ERANGE); 611 612 do { 613 rc = pci_enable_msix(dev, entries, nvec); 614 if (rc < 0) { 615 return (rc); 616 } else if (rc > 0) { 617 if (rc < minvec) 618 return (-ENOSPC); 619 nvec = rc; 620 } 621 } while (rc); 622 return (nvec); 623} 624 625#define pci_enable_msi(pdev) \ 626 linux_pci_enable_msi(pdev) 627 628static inline int 629pci_enable_msi(struct pci_dev *pdev) 630{ 631 struct resource_list_entry *rle; 632 int error; 633 int avail; 634 635 avail = pci_msi_count(pdev->dev.bsddev); 636 if (avail < 1) 637 return -EINVAL; 638 639 avail = 1; /* this function only enable one MSI IRQ */ 640 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 641 return error; 642 643 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 644 pdev->dev.irq_start = rle->start; 645 pdev->dev.irq_end = rle->start + avail; 646 pdev->irq = rle->start; 647 pdev->msi_enabled = true; 648 return (0); 649} 650 651static inline int 652pci_channel_offline(struct pci_dev *pdev) 653{ 654 655 return (pci_get_vendor(pdev->dev.bsddev) == PCIV_INVALID); 656} 657 658static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 659{ 660 return -ENODEV; 661} 662static inline void pci_disable_sriov(struct pci_dev *dev) 663{ 664} 665 666#define DEFINE_PCI_DEVICE_TABLE(_table) \ 667 const struct pci_device_id _table[] __devinitdata 668 669 670/* XXX This should not be necessary. */ 671#define pcix_set_mmrbc(d, v) 0 672#define pcix_get_max_mmrbc(d) 0 673#define pcie_set_readrq(d, v) 0 674 675#define PCI_DMA_BIDIRECTIONAL 0 676#define PCI_DMA_TODEVICE 1 677#define PCI_DMA_FROMDEVICE 2 678#define PCI_DMA_NONE 3 679 680#define pci_pool dma_pool 681#define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 682#define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 683#define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 684#define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 685 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 686#define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 687 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 688 _size, _vaddr, _dma_handle) 689#define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 690 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 691 _sg, _nents, (enum dma_data_direction)_dir) 692#define pci_map_single(_hwdev, _ptr, _size, _dir) \ 693 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 694 (_ptr), (_size), (enum dma_data_direction)_dir) 695#define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 696 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 697 _addr, _size, (enum dma_data_direction)_dir) 698#define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 699 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 700 _sg, _nents, (enum dma_data_direction)_dir) 701#define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 702 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 703 _offset, _size, (enum dma_data_direction)_dir) 704#define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 705 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 706 _dma_address, _size, (enum dma_data_direction)_dir) 707#define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 708#define pci_dma_mapping_error(_pdev, _dma_addr) \ 709 dma_mapping_error(&(_pdev)->dev, _dma_addr) 710#define pci_set_consistent_dma_mask(_pdev, _mask) \ 711 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 712#define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 713#define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 714#define pci_unmap_addr dma_unmap_addr 715#define pci_unmap_addr_set dma_unmap_addr_set 716#define pci_unmap_len dma_unmap_len 717#define pci_unmap_len_set dma_unmap_len_set 718 719typedef unsigned int __bitwise pci_channel_state_t; 720typedef unsigned int __bitwise pci_ers_result_t; 721 722enum pci_channel_state { 723 pci_channel_io_normal = 1, 724 pci_channel_io_frozen = 2, 725 pci_channel_io_perm_failure = 3, 726}; 727 728enum pci_ers_result { 729 PCI_ERS_RESULT_NONE = 1, 730 PCI_ERS_RESULT_CAN_RECOVER = 2, 731 PCI_ERS_RESULT_NEED_RESET = 3, 732 PCI_ERS_RESULT_DISCONNECT = 4, 733 PCI_ERS_RESULT_RECOVERED = 5, 734}; 735 736 737/* PCI bus error event callbacks */ 738struct pci_error_handlers { 739 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 740 enum pci_channel_state error); 741 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 742 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 743 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 744 void (*resume)(struct pci_dev *dev); 745}; 746 747/* FreeBSD does not support SRIOV - yet */ 748static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 749{ 750 return dev; 751} 752 753static inline bool pci_is_pcie(struct pci_dev *dev) 754{ 755 return !!pci_pcie_cap(dev); 756} 757 758static inline u16 pcie_flags_reg(struct pci_dev *dev) 759{ 760 int pos; 761 u16 reg16; 762 763 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 764 if (!pos) 765 return 0; 766 767 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 768 769 return reg16; 770} 771 772 773static inline int pci_pcie_type(struct pci_dev *dev) 774{ 775 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 776} 777 778static inline int pcie_cap_version(struct pci_dev *dev) 779{ 780 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 781} 782 783static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 784{ 785 int type = pci_pcie_type(dev); 786 787 return pcie_cap_version(dev) > 1 || 788 type == PCI_EXP_TYPE_ROOT_PORT || 789 type == PCI_EXP_TYPE_ENDPOINT || 790 type == PCI_EXP_TYPE_LEG_END; 791} 792 793static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 794{ 795 return true; 796} 797 798static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 799{ 800 int type = pci_pcie_type(dev); 801 802 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 803 (type == PCI_EXP_TYPE_DOWNSTREAM && 804 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 805} 806 807static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 808{ 809 int type = pci_pcie_type(dev); 810 811 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 812 type == PCI_EXP_TYPE_RC_EC; 813} 814 815static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 816{ 817 if (!pci_is_pcie(dev)) 818 return false; 819 820 switch (pos) { 821 case PCI_EXP_FLAGS_TYPE: 822 return true; 823 case PCI_EXP_DEVCAP: 824 case PCI_EXP_DEVCTL: 825 case PCI_EXP_DEVSTA: 826 return pcie_cap_has_devctl(dev); 827 case PCI_EXP_LNKCAP: 828 case PCI_EXP_LNKCTL: 829 case PCI_EXP_LNKSTA: 830 return pcie_cap_has_lnkctl(dev); 831 case PCI_EXP_SLTCAP: 832 case PCI_EXP_SLTCTL: 833 case PCI_EXP_SLTSTA: 834 return pcie_cap_has_sltctl(dev); 835 case PCI_EXP_RTCTL: 836 case PCI_EXP_RTCAP: 837 case PCI_EXP_RTSTA: 838 return pcie_cap_has_rtctl(dev); 839 case PCI_EXP_DEVCAP2: 840 case PCI_EXP_DEVCTL2: 841 case PCI_EXP_LNKCAP2: 842 case PCI_EXP_LNKCTL2: 843 case PCI_EXP_LNKSTA2: 844 return pcie_cap_version(dev) > 1; 845 default: 846 return false; 847 } 848} 849 850static inline int 851pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 852{ 853 if (pos & 3) 854 return -EINVAL; 855 856 if (!pcie_capability_reg_implemented(dev, pos)) 857 return -EINVAL; 858 859 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 860} 861 862static inline int 863pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 864{ 865 if (pos & 3) 866 return -EINVAL; 867 868 if (!pcie_capability_reg_implemented(dev, pos)) 869 return -EINVAL; 870 871 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 872} 873 874static inline int 875pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 876{ 877 if (pos & 1) 878 return -EINVAL; 879 880 if (!pcie_capability_reg_implemented(dev, pos)) 881 return 0; 882 883 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 884} 885 886static inline int pcie_get_minimum_link(struct pci_dev *dev, 887 enum pci_bus_speed *speed, enum pcie_link_width *width) 888{ 889 *speed = PCI_SPEED_UNKNOWN; 890 *width = PCIE_LNK_WIDTH_UNKNOWN; 891 return (0); 892} 893 894static inline int 895pci_num_vf(struct pci_dev *dev) 896{ 897 return (0); 898} 899 900#endif /* _LINUX_PCI_H_ */ 901