pci.h revision 351841
1/*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/compat/linuxkpi/common/include/linux/pci.h 351841 2019-09-05 09:30:55Z hselasky $ 30 */ 31#ifndef _LINUX_PCI_H_ 32#define _LINUX_PCI_H_ 33 34#define CONFIG_PCI_MSI 35 36#include <linux/types.h> 37 38#include <sys/param.h> 39#include <sys/bus.h> 40#include <sys/pciio.h> 41#include <sys/rman.h> 42#include <dev/pci/pcivar.h> 43#include <dev/pci/pcireg.h> 44#include <dev/pci/pci_private.h> 45 46#include <machine/resource.h> 47 48#include <linux/list.h> 49#include <linux/dmapool.h> 50#include <linux/dma-mapping.h> 51#include <linux/compiler.h> 52#include <linux/errno.h> 53#include <asm/atomic.h> 54#include <linux/device.h> 55 56struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64}; 65 66#define MODULE_DEVICE_TABLE(bus, table) 67 68#define PCI_BASE_CLASS_DISPLAY 0x03 69#define PCI_CLASS_DISPLAY_VGA 0x0300 70#define PCI_CLASS_DISPLAY_OTHER 0x0380 71#define PCI_BASE_CLASS_BRIDGE 0x06 72#define PCI_CLASS_BRIDGE_ISA 0x0601 73 74#define PCI_ANY_ID -1U 75#define PCI_VENDOR_ID_APPLE 0x106b 76#define PCI_VENDOR_ID_ASUSTEK 0x1043 77#define PCI_VENDOR_ID_ATI 0x1002 78#define PCI_VENDOR_ID_DELL 0x1028 79#define PCI_VENDOR_ID_HP 0x103c 80#define PCI_VENDOR_ID_IBM 0x1014 81#define PCI_VENDOR_ID_INTEL 0x8086 82#define PCI_VENDOR_ID_MELLANOX 0x15b3 83#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84#define PCI_VENDOR_ID_SERVERWORKS 0x1166 85#define PCI_VENDOR_ID_SONY 0x104d 86#define PCI_VENDOR_ID_TOPSPIN 0x1867 87#define PCI_VENDOR_ID_VIA 0x1106 88#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96#define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100#define PCI_FUNC(devfn) ((devfn) & 0x07) 101#define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 102 103#define PCI_VDEVICE(_vendor, _device) \ 104 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106#define PCI_DEVICE(_vendor, _device) \ 107 .vendor = (_vendor), .device = (_device), \ 108 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 109 110#define to_pci_dev(n) container_of(n, struct pci_dev, dev) 111 112#define PCI_VENDOR_ID PCIR_DEVVENDOR 113#define PCI_COMMAND PCIR_COMMAND 114#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 115#define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 116#define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 117#define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 118#define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 119#define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 120#define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 121#define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 122#define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 123#define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 124#define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 125#define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 126#define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 127#define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 128#define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 129#define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 130#define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 131#define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 132#define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 133#define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 134#define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 135#define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 136#define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 137#define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 138#define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 139#define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 140#define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 141#define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 142#define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 143#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 144#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 145#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 146 147#define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 148#define PCI_EXP_LNKCAP_CLKPM 0x00040000 149#define PCI_EXP_DEVSTA_TRPND 0x0020 150 151#define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 152#define IORESOURCE_IO (1 << SYS_RES_IOPORT) 153#define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 154 155enum pci_bus_speed { 156 PCI_SPEED_UNKNOWN = -1, 157 PCIE_SPEED_2_5GT, 158 PCIE_SPEED_5_0GT, 159 PCIE_SPEED_8_0GT, 160}; 161 162enum pcie_link_width { 163 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 164}; 165 166typedef int pci_power_t; 167 168#define PCI_D0 PCI_POWERSTATE_D0 169#define PCI_D1 PCI_POWERSTATE_D1 170#define PCI_D2 PCI_POWERSTATE_D2 171#define PCI_D3hot PCI_POWERSTATE_D3 172#define PCI_D3cold 4 173 174#define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 175 176struct pci_dev; 177 178struct pci_driver { 179 struct list_head links; 180 char *name; 181 const struct pci_device_id *id_table; 182 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 183 void (*remove)(struct pci_dev *dev); 184 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 185 int (*resume) (struct pci_dev *dev); /* Device woken up */ 186 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 187 driver_t bsddriver; 188 devclass_t bsdclass; 189 struct device_driver driver; 190 const struct pci_error_handlers *err_handler; 191 bool isdrm; 192}; 193 194struct pci_bus { 195 struct pci_dev *self; 196 int number; 197}; 198 199extern struct list_head pci_drivers; 200extern struct list_head pci_devices; 201extern spinlock_t pci_lock; 202 203#define __devexit_p(x) x 204 205struct pci_dev { 206 struct device dev; 207 struct list_head links; 208 struct pci_driver *pdrv; 209 struct pci_bus *bus; 210 uint64_t dma_mask; 211 uint16_t device; 212 uint16_t vendor; 213 uint16_t subsystem_vendor; 214 uint16_t subsystem_device; 215 unsigned int irq; 216 unsigned int devfn; 217 uint32_t class; 218 uint8_t revision; 219 bool msi_enabled; 220}; 221 222static inline struct resource_list_entry * 223linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 224{ 225 struct pci_devinfo *dinfo; 226 struct resource_list *rl; 227 228 dinfo = device_get_ivars(pdev->dev.bsddev); 229 rl = &dinfo->resources; 230 return resource_list_find(rl, type, rid); 231} 232 233static inline struct resource_list_entry * 234linux_pci_get_bar(struct pci_dev *pdev, int bar) 235{ 236 struct resource_list_entry *rle; 237 238 bar = PCIR_BAR(bar); 239 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 240 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 241 return (rle); 242} 243 244static inline struct device * 245linux_pci_find_irq_dev(unsigned int irq) 246{ 247 struct pci_dev *pdev; 248 struct device *found; 249 250 found = NULL; 251 spin_lock(&pci_lock); 252 list_for_each_entry(pdev, &pci_devices, links) { 253 if (irq == pdev->dev.irq || 254 (irq >= pdev->dev.irq_start && irq < pdev->dev.irq_end)) { 255 found = &pdev->dev; 256 break; 257 } 258 } 259 spin_unlock(&pci_lock); 260 return (found); 261} 262 263static inline unsigned long 264pci_resource_start(struct pci_dev *pdev, int bar) 265{ 266 struct resource_list_entry *rle; 267 268 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 269 return (0); 270 return rle->start; 271} 272 273static inline unsigned long 274pci_resource_len(struct pci_dev *pdev, int bar) 275{ 276 struct resource_list_entry *rle; 277 278 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 279 return (0); 280 return rle->count; 281} 282 283static inline int 284pci_resource_type(struct pci_dev *pdev, int bar) 285{ 286 struct pci_map *pm; 287 288 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 289 if (!pm) 290 return (-1); 291 292 if (PCI_BAR_IO(pm->pm_value)) 293 return (SYS_RES_IOPORT); 294 else 295 return (SYS_RES_MEMORY); 296} 297 298/* 299 * All drivers just seem to want to inspect the type not flags. 300 */ 301static inline int 302pci_resource_flags(struct pci_dev *pdev, int bar) 303{ 304 int type; 305 306 type = pci_resource_type(pdev, bar); 307 if (type < 0) 308 return (0); 309 return (1 << type); 310} 311 312static inline const char * 313pci_name(struct pci_dev *d) 314{ 315 316 return device_get_desc(d->dev.bsddev); 317} 318 319static inline void * 320pci_get_drvdata(struct pci_dev *pdev) 321{ 322 323 return dev_get_drvdata(&pdev->dev); 324} 325 326static inline void 327pci_set_drvdata(struct pci_dev *pdev, void *data) 328{ 329 330 dev_set_drvdata(&pdev->dev, data); 331} 332 333static inline int 334pci_enable_device(struct pci_dev *pdev) 335{ 336 337 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 338 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 339 return (0); 340} 341 342static inline void 343pci_disable_device(struct pci_dev *pdev) 344{ 345 346 pci_disable_busmaster(pdev->dev.bsddev); 347} 348 349static inline int 350pci_set_master(struct pci_dev *pdev) 351{ 352 353 pci_enable_busmaster(pdev->dev.bsddev); 354 return (0); 355} 356 357static inline int 358pci_set_power_state(struct pci_dev *pdev, int state) 359{ 360 361 pci_set_powerstate(pdev->dev.bsddev, state); 362 return (0); 363} 364 365static inline int 366pci_clear_master(struct pci_dev *pdev) 367{ 368 369 pci_disable_busmaster(pdev->dev.bsddev); 370 return (0); 371} 372 373static inline int 374pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 375{ 376 int rid; 377 int type; 378 379 type = pci_resource_type(pdev, bar); 380 if (type < 0) 381 return (-ENODEV); 382 rid = PCIR_BAR(bar); 383 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 384 RF_ACTIVE) == NULL) 385 return (-EINVAL); 386 return (0); 387} 388 389static inline void 390pci_release_region(struct pci_dev *pdev, int bar) 391{ 392 struct resource_list_entry *rle; 393 394 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 395 return; 396 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 397} 398 399static inline void 400pci_release_regions(struct pci_dev *pdev) 401{ 402 int i; 403 404 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 405 pci_release_region(pdev, i); 406} 407 408static inline int 409pci_request_regions(struct pci_dev *pdev, const char *res_name) 410{ 411 int error; 412 int i; 413 414 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 415 error = pci_request_region(pdev, i, res_name); 416 if (error && error != -ENODEV) { 417 pci_release_regions(pdev); 418 return (error); 419 } 420 } 421 return (0); 422} 423 424static inline void 425pci_disable_msix(struct pci_dev *pdev) 426{ 427 428 pci_release_msi(pdev->dev.bsddev); 429 430 /* 431 * The MSIX IRQ numbers associated with this PCI device are no 432 * longer valid and might be re-assigned. Make sure 433 * linux_pci_find_irq_dev() does no longer see them by 434 * resetting their references to zero: 435 */ 436 pdev->dev.irq_start = 0; 437 pdev->dev.irq_end = 0; 438} 439 440#define pci_disable_msi(pdev) \ 441 linux_pci_disable_msi(pdev) 442 443static inline void 444linux_pci_disable_msi(struct pci_dev *pdev) 445{ 446 447 pci_release_msi(pdev->dev.bsddev); 448 449 pdev->dev.irq_start = 0; 450 pdev->dev.irq_end = 0; 451 pdev->irq = pdev->dev.irq; 452 pdev->msi_enabled = false; 453} 454 455static inline bus_addr_t 456pci_bus_address(struct pci_dev *pdev, int bar) 457{ 458 459 return (pci_resource_start(pdev, bar)); 460} 461 462#define PCI_CAP_ID_EXP PCIY_EXPRESS 463#define PCI_CAP_ID_PCIX PCIY_PCIX 464#define PCI_CAP_ID_AGP PCIY_AGP 465#define PCI_CAP_ID_PM PCIY_PMG 466 467#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 468#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 469#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 470#define PCI_EXP_LNKCTL PCIER_LINK_CTL 471#define PCI_EXP_LNKSTA PCIER_LINK_STA 472 473static inline int 474pci_find_capability(struct pci_dev *pdev, int capid) 475{ 476 int reg; 477 478 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 479 return (0); 480 return (reg); 481} 482 483static inline int pci_pcie_cap(struct pci_dev *dev) 484{ 485 return pci_find_capability(dev, PCI_CAP_ID_EXP); 486} 487 488 489static inline int 490pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 491{ 492 493 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 494 return (0); 495} 496 497static inline int 498pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 499{ 500 501 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 502 return (0); 503} 504 505static inline int 506pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 507{ 508 509 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 510 return (0); 511} 512 513static inline int 514pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 515{ 516 517 pci_write_config(pdev->dev.bsddev, where, val, 1); 518 return (0); 519} 520 521static inline int 522pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 523{ 524 525 pci_write_config(pdev->dev.bsddev, where, val, 2); 526 return (0); 527} 528 529static inline int 530pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 531{ 532 533 pci_write_config(pdev->dev.bsddev, where, val, 4); 534 return (0); 535} 536 537int linux_pci_register_driver(struct pci_driver *pdrv); 538int linux_pci_register_drm_driver(struct pci_driver *pdrv); 539void linux_pci_unregister_driver(struct pci_driver *pdrv); 540 541#define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 542#define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 543 544struct msix_entry { 545 int entry; 546 int vector; 547}; 548 549/* 550 * Enable msix, positive errors indicate actual number of available 551 * vectors. Negative errors are failures. 552 * 553 * NB: define added to prevent this definition of pci_enable_msix from 554 * clashing with the native FreeBSD version. 555 */ 556#define pci_enable_msix(...) \ 557 linux_pci_enable_msix(__VA_ARGS__) 558 559static inline int 560pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 561{ 562 struct resource_list_entry *rle; 563 int error; 564 int avail; 565 int i; 566 567 avail = pci_msix_count(pdev->dev.bsddev); 568 if (avail < nreq) { 569 if (avail == 0) 570 return -EINVAL; 571 return avail; 572 } 573 avail = nreq; 574 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 575 return error; 576 /* 577 * Handle case where "pci_alloc_msix()" may allocate less 578 * interrupts than available and return with no error: 579 */ 580 if (avail < nreq) { 581 pci_release_msi(pdev->dev.bsddev); 582 return avail; 583 } 584 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 585 pdev->dev.irq_start = rle->start; 586 pdev->dev.irq_end = rle->start + avail; 587 for (i = 0; i < nreq; i++) 588 entries[i].vector = pdev->dev.irq_start + i; 589 return (0); 590} 591 592#define pci_enable_msix_range(...) \ 593 linux_pci_enable_msix_range(__VA_ARGS__) 594 595static inline int 596pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 597 int minvec, int maxvec) 598{ 599 int nvec = maxvec; 600 int rc; 601 602 if (maxvec < minvec) 603 return (-ERANGE); 604 605 do { 606 rc = pci_enable_msix(dev, entries, nvec); 607 if (rc < 0) { 608 return (rc); 609 } else if (rc > 0) { 610 if (rc < minvec) 611 return (-ENOSPC); 612 nvec = rc; 613 } 614 } while (rc); 615 return (nvec); 616} 617 618#define pci_enable_msi(pdev) \ 619 linux_pci_enable_msi(pdev) 620 621static inline int 622pci_enable_msi(struct pci_dev *pdev) 623{ 624 struct resource_list_entry *rle; 625 int error; 626 int avail; 627 628 avail = pci_msi_count(pdev->dev.bsddev); 629 if (avail < 1) 630 return -EINVAL; 631 632 avail = 1; /* this function only enable one MSI IRQ */ 633 if ((error = -pci_alloc_msi(pdev->dev.bsddev, &avail)) != 0) 634 return error; 635 636 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 637 pdev->dev.irq_start = rle->start; 638 pdev->dev.irq_end = rle->start + avail; 639 pdev->irq = rle->start; 640 pdev->msi_enabled = true; 641 return (0); 642} 643 644static inline int 645pci_channel_offline(struct pci_dev *pdev) 646{ 647 648 return (pci_get_vendor(pdev->dev.bsddev) == PCIV_INVALID); 649} 650 651static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 652{ 653 return -ENODEV; 654} 655static inline void pci_disable_sriov(struct pci_dev *dev) 656{ 657} 658 659#define DEFINE_PCI_DEVICE_TABLE(_table) \ 660 const struct pci_device_id _table[] __devinitdata 661 662 663/* XXX This should not be necessary. */ 664#define pcix_set_mmrbc(d, v) 0 665#define pcix_get_max_mmrbc(d) 0 666#define pcie_set_readrq(d, v) 0 667 668#define PCI_DMA_BIDIRECTIONAL 0 669#define PCI_DMA_TODEVICE 1 670#define PCI_DMA_FROMDEVICE 2 671#define PCI_DMA_NONE 3 672 673#define pci_pool dma_pool 674#define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 675#define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 676#define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 677#define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 678 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 679#define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 680 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 681 _size, _vaddr, _dma_handle) 682#define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 683 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 684 _sg, _nents, (enum dma_data_direction)_dir) 685#define pci_map_single(_hwdev, _ptr, _size, _dir) \ 686 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 687 (_ptr), (_size), (enum dma_data_direction)_dir) 688#define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 689 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 690 _addr, _size, (enum dma_data_direction)_dir) 691#define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 692 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 693 _sg, _nents, (enum dma_data_direction)_dir) 694#define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 695 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 696 _offset, _size, (enum dma_data_direction)_dir) 697#define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 698 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 699 _dma_address, _size, (enum dma_data_direction)_dir) 700#define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 701#define pci_dma_mapping_error(_pdev, _dma_addr) \ 702 dma_mapping_error(&(_pdev)->dev, _dma_addr) 703#define pci_set_consistent_dma_mask(_pdev, _mask) \ 704 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 705#define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 706#define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 707#define pci_unmap_addr dma_unmap_addr 708#define pci_unmap_addr_set dma_unmap_addr_set 709#define pci_unmap_len dma_unmap_len 710#define pci_unmap_len_set dma_unmap_len_set 711 712typedef unsigned int __bitwise pci_channel_state_t; 713typedef unsigned int __bitwise pci_ers_result_t; 714 715enum pci_channel_state { 716 pci_channel_io_normal = 1, 717 pci_channel_io_frozen = 2, 718 pci_channel_io_perm_failure = 3, 719}; 720 721enum pci_ers_result { 722 PCI_ERS_RESULT_NONE = 1, 723 PCI_ERS_RESULT_CAN_RECOVER = 2, 724 PCI_ERS_RESULT_NEED_RESET = 3, 725 PCI_ERS_RESULT_DISCONNECT = 4, 726 PCI_ERS_RESULT_RECOVERED = 5, 727}; 728 729 730/* PCI bus error event callbacks */ 731struct pci_error_handlers { 732 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 733 enum pci_channel_state error); 734 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 735 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 736 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 737 void (*resume)(struct pci_dev *dev); 738}; 739 740/* FreeBSD does not support SRIOV - yet */ 741static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 742{ 743 return dev; 744} 745 746static inline bool pci_is_pcie(struct pci_dev *dev) 747{ 748 return !!pci_pcie_cap(dev); 749} 750 751static inline u16 pcie_flags_reg(struct pci_dev *dev) 752{ 753 int pos; 754 u16 reg16; 755 756 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 757 if (!pos) 758 return 0; 759 760 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 761 762 return reg16; 763} 764 765 766static inline int pci_pcie_type(struct pci_dev *dev) 767{ 768 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 769} 770 771static inline int pcie_cap_version(struct pci_dev *dev) 772{ 773 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 774} 775 776static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 777{ 778 int type = pci_pcie_type(dev); 779 780 return pcie_cap_version(dev) > 1 || 781 type == PCI_EXP_TYPE_ROOT_PORT || 782 type == PCI_EXP_TYPE_ENDPOINT || 783 type == PCI_EXP_TYPE_LEG_END; 784} 785 786static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 787{ 788 return true; 789} 790 791static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 792{ 793 int type = pci_pcie_type(dev); 794 795 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 796 (type == PCI_EXP_TYPE_DOWNSTREAM && 797 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 798} 799 800static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 801{ 802 int type = pci_pcie_type(dev); 803 804 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 805 type == PCI_EXP_TYPE_RC_EC; 806} 807 808static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 809{ 810 if (!pci_is_pcie(dev)) 811 return false; 812 813 switch (pos) { 814 case PCI_EXP_FLAGS_TYPE: 815 return true; 816 case PCI_EXP_DEVCAP: 817 case PCI_EXP_DEVCTL: 818 case PCI_EXP_DEVSTA: 819 return pcie_cap_has_devctl(dev); 820 case PCI_EXP_LNKCAP: 821 case PCI_EXP_LNKCTL: 822 case PCI_EXP_LNKSTA: 823 return pcie_cap_has_lnkctl(dev); 824 case PCI_EXP_SLTCAP: 825 case PCI_EXP_SLTCTL: 826 case PCI_EXP_SLTSTA: 827 return pcie_cap_has_sltctl(dev); 828 case PCI_EXP_RTCTL: 829 case PCI_EXP_RTCAP: 830 case PCI_EXP_RTSTA: 831 return pcie_cap_has_rtctl(dev); 832 case PCI_EXP_DEVCAP2: 833 case PCI_EXP_DEVCTL2: 834 case PCI_EXP_LNKCAP2: 835 case PCI_EXP_LNKCTL2: 836 case PCI_EXP_LNKSTA2: 837 return pcie_cap_version(dev) > 1; 838 default: 839 return false; 840 } 841} 842 843static inline int 844pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 845{ 846 if (pos & 3) 847 return -EINVAL; 848 849 if (!pcie_capability_reg_implemented(dev, pos)) 850 return -EINVAL; 851 852 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 853} 854 855static inline int 856pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 857{ 858 if (pos & 3) 859 return -EINVAL; 860 861 if (!pcie_capability_reg_implemented(dev, pos)) 862 return -EINVAL; 863 864 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 865} 866 867static inline int 868pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 869{ 870 if (pos & 1) 871 return -EINVAL; 872 873 if (!pcie_capability_reg_implemented(dev, pos)) 874 return 0; 875 876 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 877} 878 879static inline int pcie_get_minimum_link(struct pci_dev *dev, 880 enum pci_bus_speed *speed, enum pcie_link_width *width) 881{ 882 *speed = PCI_SPEED_UNKNOWN; 883 *width = PCIE_LNK_WIDTH_UNKNOWN; 884 return (0); 885} 886 887static inline int 888pci_num_vf(struct pci_dev *dev) 889{ 890 return (0); 891} 892 893#endif /* _LINUX_PCI_H_ */ 894