pci.h revision 343655
1/*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/compat/linuxkpi/common/include/linux/pci.h 343655 2019-02-01 10:06:49Z hselasky $ 30 */ 31#ifndef _LINUX_PCI_H_ 32#define _LINUX_PCI_H_ 33 34#define CONFIG_PCI_MSI 35 36#include <linux/types.h> 37 38#include <sys/param.h> 39#include <sys/bus.h> 40#include <sys/pciio.h> 41#include <sys/rman.h> 42#include <dev/pci/pcivar.h> 43#include <dev/pci/pcireg.h> 44#include <dev/pci/pci_private.h> 45 46#include <machine/resource.h> 47 48#include <linux/list.h> 49#include <linux/dmapool.h> 50#include <linux/dma-mapping.h> 51#include <linux/compiler.h> 52#include <linux/errno.h> 53#include <asm/atomic.h> 54#include <linux/device.h> 55 56struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 uintptr_t driver_data; 64}; 65 66#define MODULE_DEVICE_TABLE(bus, table) 67 68#define PCI_BASE_CLASS_DISPLAY 0x03 69#define PCI_CLASS_DISPLAY_VGA 0x0300 70#define PCI_CLASS_DISPLAY_OTHER 0x0380 71#define PCI_BASE_CLASS_BRIDGE 0x06 72#define PCI_CLASS_BRIDGE_ISA 0x0601 73 74#define PCI_ANY_ID -1U 75#define PCI_VENDOR_ID_APPLE 0x106b 76#define PCI_VENDOR_ID_ASUSTEK 0x1043 77#define PCI_VENDOR_ID_ATI 0x1002 78#define PCI_VENDOR_ID_DELL 0x1028 79#define PCI_VENDOR_ID_HP 0x103c 80#define PCI_VENDOR_ID_IBM 0x1014 81#define PCI_VENDOR_ID_INTEL 0x8086 82#define PCI_VENDOR_ID_MELLANOX 0x15b3 83#define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 84#define PCI_VENDOR_ID_SERVERWORKS 0x1166 85#define PCI_VENDOR_ID_SONY 0x104d 86#define PCI_VENDOR_ID_TOPSPIN 0x1867 87#define PCI_VENDOR_ID_VIA 0x1106 88#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 89#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 90#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 91#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 92#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 93#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 94#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 95#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 96#define PCI_SUBDEVICE_ID_QEMU 0x1100 97 98#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 99#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 100#define PCI_FUNC(devfn) ((devfn) & 0x07) 101#define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 102 103#define PCI_VDEVICE(_vendor, _device) \ 104 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 105 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 106#define PCI_DEVICE(_vendor, _device) \ 107 .vendor = (_vendor), .device = (_device), \ 108 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 109 110#define to_pci_dev(n) container_of(n, struct pci_dev, dev) 111 112#define PCI_VENDOR_ID PCIR_DEVVENDOR 113#define PCI_COMMAND PCIR_COMMAND 114#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 115#define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 116#define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 117#define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 118#define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 119#define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 120#define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 121#define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 122#define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 123#define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 124#define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 125#define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 126#define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 127#define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 128#define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 129#define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 130#define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 131#define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 132#define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 133#define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 134#define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 135#define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 136#define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 137#define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 138#define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 139#define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 140#define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 141#define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 142#define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 143#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 144#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 145#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 146 147#define PCI_EXP_LNKCTL_HAWD PCIEM_LINK_CTL_HAWD 148#define PCI_EXP_LNKCAP_CLKPM 0x00040000 149#define PCI_EXP_DEVSTA_TRPND 0x0020 150 151#define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 152#define IORESOURCE_IO (1 << SYS_RES_IOPORT) 153#define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 154 155enum pci_bus_speed { 156 PCI_SPEED_UNKNOWN = -1, 157 PCIE_SPEED_2_5GT, 158 PCIE_SPEED_5_0GT, 159 PCIE_SPEED_8_0GT, 160}; 161 162enum pcie_link_width { 163 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 164}; 165 166typedef int pci_power_t; 167 168#define PCI_D0 PCI_POWERSTATE_D0 169#define PCI_D1 PCI_POWERSTATE_D1 170#define PCI_D2 PCI_POWERSTATE_D2 171#define PCI_D3hot PCI_POWERSTATE_D3 172#define PCI_D3cold 4 173 174#define PCI_POWER_ERROR PCI_POWERSTATE_UNKNOWN 175 176struct pci_dev; 177 178struct pci_driver { 179 struct list_head links; 180 char *name; 181 const struct pci_device_id *id_table; 182 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 183 void (*remove)(struct pci_dev *dev); 184 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 185 int (*resume) (struct pci_dev *dev); /* Device woken up */ 186 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 187 driver_t bsddriver; 188 devclass_t bsdclass; 189 struct device_driver driver; 190 const struct pci_error_handlers *err_handler; 191 bool isdrm; 192}; 193 194struct pci_bus { 195 struct pci_dev *self; 196 int number; 197}; 198 199extern struct list_head pci_drivers; 200extern struct list_head pci_devices; 201extern spinlock_t pci_lock; 202 203#define __devexit_p(x) x 204 205struct pci_dev { 206 struct device dev; 207 struct list_head links; 208 struct pci_driver *pdrv; 209 struct pci_bus *bus; 210 uint64_t dma_mask; 211 uint16_t device; 212 uint16_t vendor; 213 uint16_t subsystem_vendor; 214 uint16_t subsystem_device; 215 unsigned int irq; 216 unsigned int devfn; 217 uint32_t class; 218 uint8_t revision; 219}; 220 221static inline struct resource_list_entry * 222linux_pci_get_rle(struct pci_dev *pdev, int type, int rid) 223{ 224 struct pci_devinfo *dinfo; 225 struct resource_list *rl; 226 227 dinfo = device_get_ivars(pdev->dev.bsddev); 228 rl = &dinfo->resources; 229 return resource_list_find(rl, type, rid); 230} 231 232static inline struct resource_list_entry * 233linux_pci_get_bar(struct pci_dev *pdev, int bar) 234{ 235 struct resource_list_entry *rle; 236 237 bar = PCIR_BAR(bar); 238 if ((rle = linux_pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 239 rle = linux_pci_get_rle(pdev, SYS_RES_IOPORT, bar); 240 return (rle); 241} 242 243static inline struct device * 244linux_pci_find_irq_dev(unsigned int irq) 245{ 246 struct pci_dev *pdev; 247 struct device *found; 248 249 found = NULL; 250 spin_lock(&pci_lock); 251 list_for_each_entry(pdev, &pci_devices, links) { 252 if (irq == pdev->dev.irq || 253 (irq >= pdev->dev.msix && irq < pdev->dev.msix_max)) { 254 found = &pdev->dev; 255 break; 256 } 257 } 258 spin_unlock(&pci_lock); 259 return (found); 260} 261 262static inline unsigned long 263pci_resource_start(struct pci_dev *pdev, int bar) 264{ 265 struct resource_list_entry *rle; 266 267 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 268 return (0); 269 return rle->start; 270} 271 272static inline unsigned long 273pci_resource_len(struct pci_dev *pdev, int bar) 274{ 275 struct resource_list_entry *rle; 276 277 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 278 return (0); 279 return rle->count; 280} 281 282static inline int 283pci_resource_type(struct pci_dev *pdev, int bar) 284{ 285 struct pci_map *pm; 286 287 pm = pci_find_bar(pdev->dev.bsddev, PCIR_BAR(bar)); 288 if (!pm) 289 return (-1); 290 291 if (PCI_BAR_IO(pm->pm_value)) 292 return (SYS_RES_IOPORT); 293 else 294 return (SYS_RES_MEMORY); 295} 296 297/* 298 * All drivers just seem to want to inspect the type not flags. 299 */ 300static inline int 301pci_resource_flags(struct pci_dev *pdev, int bar) 302{ 303 int type; 304 305 type = pci_resource_type(pdev, bar); 306 if (type < 0) 307 return (0); 308 return (1 << type); 309} 310 311static inline const char * 312pci_name(struct pci_dev *d) 313{ 314 315 return device_get_desc(d->dev.bsddev); 316} 317 318static inline void * 319pci_get_drvdata(struct pci_dev *pdev) 320{ 321 322 return dev_get_drvdata(&pdev->dev); 323} 324 325static inline void 326pci_set_drvdata(struct pci_dev *pdev, void *data) 327{ 328 329 dev_set_drvdata(&pdev->dev, data); 330} 331 332static inline int 333pci_enable_device(struct pci_dev *pdev) 334{ 335 336 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 337 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 338 return (0); 339} 340 341static inline void 342pci_disable_device(struct pci_dev *pdev) 343{ 344 345 pci_disable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 346 pci_disable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 347 pci_disable_busmaster(pdev->dev.bsddev); 348} 349 350static inline int 351pci_set_master(struct pci_dev *pdev) 352{ 353 354 pci_enable_busmaster(pdev->dev.bsddev); 355 return (0); 356} 357 358static inline int 359pci_set_power_state(struct pci_dev *pdev, int state) 360{ 361 362 pci_set_powerstate(pdev->dev.bsddev, state); 363 return (0); 364} 365 366static inline int 367pci_clear_master(struct pci_dev *pdev) 368{ 369 370 pci_disable_busmaster(pdev->dev.bsddev); 371 return (0); 372} 373 374static inline int 375pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 376{ 377 int rid; 378 int type; 379 380 type = pci_resource_type(pdev, bar); 381 if (type < 0) 382 return (-ENODEV); 383 rid = PCIR_BAR(bar); 384 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 385 RF_ACTIVE) == NULL) 386 return (-EINVAL); 387 return (0); 388} 389 390static inline void 391pci_release_region(struct pci_dev *pdev, int bar) 392{ 393 struct resource_list_entry *rle; 394 395 if ((rle = linux_pci_get_bar(pdev, bar)) == NULL) 396 return; 397 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 398} 399 400static inline void 401pci_release_regions(struct pci_dev *pdev) 402{ 403 int i; 404 405 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 406 pci_release_region(pdev, i); 407} 408 409static inline int 410pci_request_regions(struct pci_dev *pdev, const char *res_name) 411{ 412 int error; 413 int i; 414 415 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 416 error = pci_request_region(pdev, i, res_name); 417 if (error && error != -ENODEV) { 418 pci_release_regions(pdev); 419 return (error); 420 } 421 } 422 return (0); 423} 424 425static inline void 426pci_disable_msix(struct pci_dev *pdev) 427{ 428 429 pci_release_msi(pdev->dev.bsddev); 430 431 /* 432 * The MSIX IRQ numbers associated with this PCI device are no 433 * longer valid and might be re-assigned. Make sure 434 * linux_pci_find_irq_dev() does no longer see them by 435 * resetting their references to zero: 436 */ 437 pdev->dev.msix = 0; 438 pdev->dev.msix_max = 0; 439} 440 441static inline bus_addr_t 442pci_bus_address(struct pci_dev *pdev, int bar) 443{ 444 445 return (pci_resource_start(pdev, bar)); 446} 447 448#define PCI_CAP_ID_EXP PCIY_EXPRESS 449#define PCI_CAP_ID_PCIX PCIY_PCIX 450#define PCI_CAP_ID_AGP PCIY_AGP 451#define PCI_CAP_ID_PM PCIY_PMG 452 453#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL 454#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 455#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST 456#define PCI_EXP_LNKCTL PCIER_LINK_CTL 457#define PCI_EXP_LNKSTA PCIER_LINK_STA 458 459static inline int 460pci_find_capability(struct pci_dev *pdev, int capid) 461{ 462 int reg; 463 464 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 465 return (0); 466 return (reg); 467} 468 469static inline int pci_pcie_cap(struct pci_dev *dev) 470{ 471 return pci_find_capability(dev, PCI_CAP_ID_EXP); 472} 473 474 475static inline int 476pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 477{ 478 479 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 480 return (0); 481} 482 483static inline int 484pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 485{ 486 487 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 488 return (0); 489} 490 491static inline int 492pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 493{ 494 495 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 496 return (0); 497} 498 499static inline int 500pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 501{ 502 503 pci_write_config(pdev->dev.bsddev, where, val, 1); 504 return (0); 505} 506 507static inline int 508pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 509{ 510 511 pci_write_config(pdev->dev.bsddev, where, val, 2); 512 return (0); 513} 514 515static inline int 516pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 517{ 518 519 pci_write_config(pdev->dev.bsddev, where, val, 4); 520 return (0); 521} 522 523int linux_pci_register_driver(struct pci_driver *pdrv); 524int linux_pci_register_drm_driver(struct pci_driver *pdrv); 525void linux_pci_unregister_driver(struct pci_driver *pdrv); 526 527#define pci_register_driver(pdrv) linux_pci_register_driver(pdrv) 528#define pci_unregister_driver(pdrv) linux_pci_unregister_driver(pdrv) 529 530struct msix_entry { 531 int entry; 532 int vector; 533}; 534 535/* 536 * Enable msix, positive errors indicate actual number of available 537 * vectors. Negative errors are failures. 538 * 539 * NB: define added to prevent this definition of pci_enable_msix from 540 * clashing with the native FreeBSD version. 541 */ 542#define pci_enable_msix(...) \ 543 linux_pci_enable_msix(__VA_ARGS__) 544 545static inline int 546pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 547{ 548 struct resource_list_entry *rle; 549 int error; 550 int avail; 551 int i; 552 553 avail = pci_msix_count(pdev->dev.bsddev); 554 if (avail < nreq) { 555 if (avail == 0) 556 return -EINVAL; 557 return avail; 558 } 559 avail = nreq; 560 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 561 return error; 562 /* 563 * Handle case where "pci_alloc_msix()" may allocate less 564 * interrupts than available and return with no error: 565 */ 566 if (avail < nreq) { 567 pci_release_msi(pdev->dev.bsddev); 568 return avail; 569 } 570 rle = linux_pci_get_rle(pdev, SYS_RES_IRQ, 1); 571 pdev->dev.msix = rle->start; 572 pdev->dev.msix_max = rle->start + avail; 573 for (i = 0; i < nreq; i++) 574 entries[i].vector = pdev->dev.msix + i; 575 return (0); 576} 577 578#define pci_enable_msix_range(...) \ 579 linux_pci_enable_msix_range(__VA_ARGS__) 580 581static inline int 582pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 583 int minvec, int maxvec) 584{ 585 int nvec = maxvec; 586 int rc; 587 588 if (maxvec < minvec) 589 return (-ERANGE); 590 591 do { 592 rc = pci_enable_msix(dev, entries, nvec); 593 if (rc < 0) { 594 return (rc); 595 } else if (rc > 0) { 596 if (rc < minvec) 597 return (-ENOSPC); 598 nvec = rc; 599 } 600 } while (rc); 601 return (nvec); 602} 603 604static inline int 605pci_channel_offline(struct pci_dev *pdev) 606{ 607 608 return (pci_get_vendor(pdev->dev.bsddev) == 0xffff); 609} 610 611static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 612{ 613 return -ENODEV; 614} 615static inline void pci_disable_sriov(struct pci_dev *dev) 616{ 617} 618 619#define DEFINE_PCI_DEVICE_TABLE(_table) \ 620 const struct pci_device_id _table[] __devinitdata 621 622 623/* XXX This should not be necessary. */ 624#define pcix_set_mmrbc(d, v) 0 625#define pcix_get_max_mmrbc(d) 0 626#define pcie_set_readrq(d, v) 0 627 628#define PCI_DMA_BIDIRECTIONAL 0 629#define PCI_DMA_TODEVICE 1 630#define PCI_DMA_FROMDEVICE 2 631#define PCI_DMA_NONE 3 632 633#define pci_pool dma_pool 634#define pci_pool_destroy(...) dma_pool_destroy(__VA_ARGS__) 635#define pci_pool_alloc(...) dma_pool_alloc(__VA_ARGS__) 636#define pci_pool_free(...) dma_pool_free(__VA_ARGS__) 637#define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 638 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 639#define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 640 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 641 _size, _vaddr, _dma_handle) 642#define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 643 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 644 _sg, _nents, (enum dma_data_direction)_dir) 645#define pci_map_single(_hwdev, _ptr, _size, _dir) \ 646 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 647 (_ptr), (_size), (enum dma_data_direction)_dir) 648#define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 649 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 650 _addr, _size, (enum dma_data_direction)_dir) 651#define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 652 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 653 _sg, _nents, (enum dma_data_direction)_dir) 654#define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 655 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 656 _offset, _size, (enum dma_data_direction)_dir) 657#define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 658 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 659 _dma_address, _size, (enum dma_data_direction)_dir) 660#define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 661#define pci_dma_mapping_error(_pdev, _dma_addr) \ 662 dma_mapping_error(&(_pdev)->dev, _dma_addr) 663#define pci_set_consistent_dma_mask(_pdev, _mask) \ 664 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 665#define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 666#define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 667#define pci_unmap_addr dma_unmap_addr 668#define pci_unmap_addr_set dma_unmap_addr_set 669#define pci_unmap_len dma_unmap_len 670#define pci_unmap_len_set dma_unmap_len_set 671 672typedef unsigned int __bitwise pci_channel_state_t; 673typedef unsigned int __bitwise pci_ers_result_t; 674 675enum pci_channel_state { 676 pci_channel_io_normal = 1, 677 pci_channel_io_frozen = 2, 678 pci_channel_io_perm_failure = 3, 679}; 680 681enum pci_ers_result { 682 PCI_ERS_RESULT_NONE = 1, 683 PCI_ERS_RESULT_CAN_RECOVER = 2, 684 PCI_ERS_RESULT_NEED_RESET = 3, 685 PCI_ERS_RESULT_DISCONNECT = 4, 686 PCI_ERS_RESULT_RECOVERED = 5, 687}; 688 689 690/* PCI bus error event callbacks */ 691struct pci_error_handlers { 692 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 693 enum pci_channel_state error); 694 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 695 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 696 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 697 void (*resume)(struct pci_dev *dev); 698}; 699 700/* FreeBSD does not support SRIOV - yet */ 701static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 702{ 703 return dev; 704} 705 706static inline bool pci_is_pcie(struct pci_dev *dev) 707{ 708 return !!pci_pcie_cap(dev); 709} 710 711static inline u16 pcie_flags_reg(struct pci_dev *dev) 712{ 713 int pos; 714 u16 reg16; 715 716 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 717 if (!pos) 718 return 0; 719 720 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 721 722 return reg16; 723} 724 725 726static inline int pci_pcie_type(struct pci_dev *dev) 727{ 728 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 729} 730 731static inline int pcie_cap_version(struct pci_dev *dev) 732{ 733 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 734} 735 736static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 737{ 738 int type = pci_pcie_type(dev); 739 740 return pcie_cap_version(dev) > 1 || 741 type == PCI_EXP_TYPE_ROOT_PORT || 742 type == PCI_EXP_TYPE_ENDPOINT || 743 type == PCI_EXP_TYPE_LEG_END; 744} 745 746static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 747{ 748 return true; 749} 750 751static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 752{ 753 int type = pci_pcie_type(dev); 754 755 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 756 (type == PCI_EXP_TYPE_DOWNSTREAM && 757 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 758} 759 760static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 761{ 762 int type = pci_pcie_type(dev); 763 764 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 765 type == PCI_EXP_TYPE_RC_EC; 766} 767 768static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 769{ 770 if (!pci_is_pcie(dev)) 771 return false; 772 773 switch (pos) { 774 case PCI_EXP_FLAGS_TYPE: 775 return true; 776 case PCI_EXP_DEVCAP: 777 case PCI_EXP_DEVCTL: 778 case PCI_EXP_DEVSTA: 779 return pcie_cap_has_devctl(dev); 780 case PCI_EXP_LNKCAP: 781 case PCI_EXP_LNKCTL: 782 case PCI_EXP_LNKSTA: 783 return pcie_cap_has_lnkctl(dev); 784 case PCI_EXP_SLTCAP: 785 case PCI_EXP_SLTCTL: 786 case PCI_EXP_SLTSTA: 787 return pcie_cap_has_sltctl(dev); 788 case PCI_EXP_RTCTL: 789 case PCI_EXP_RTCAP: 790 case PCI_EXP_RTSTA: 791 return pcie_cap_has_rtctl(dev); 792 case PCI_EXP_DEVCAP2: 793 case PCI_EXP_DEVCTL2: 794 case PCI_EXP_LNKCAP2: 795 case PCI_EXP_LNKCTL2: 796 case PCI_EXP_LNKSTA2: 797 return pcie_cap_version(dev) > 1; 798 default: 799 return false; 800 } 801} 802 803static inline int 804pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 805{ 806 if (pos & 3) 807 return -EINVAL; 808 809 if (!pcie_capability_reg_implemented(dev, pos)) 810 return -EINVAL; 811 812 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 813} 814 815static inline int 816pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *dst) 817{ 818 if (pos & 3) 819 return -EINVAL; 820 821 if (!pcie_capability_reg_implemented(dev, pos)) 822 return -EINVAL; 823 824 return pci_read_config_word(dev, pci_pcie_cap(dev) + pos, dst); 825} 826 827static inline int 828pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 829{ 830 if (pos & 1) 831 return -EINVAL; 832 833 if (!pcie_capability_reg_implemented(dev, pos)) 834 return 0; 835 836 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 837} 838 839static inline int pcie_get_minimum_link(struct pci_dev *dev, 840 enum pci_bus_speed *speed, enum pcie_link_width *width) 841{ 842 *speed = PCI_SPEED_UNKNOWN; 843 *width = PCIE_LNK_WIDTH_UNKNOWN; 844 return (0); 845} 846 847static inline int 848pci_num_vf(struct pci_dev *dev) 849{ 850 return (0); 851} 852 853#endif /* _LINUX_PCI_H_ */ 854