pci.h revision 306949
1/*- 2 * Copyright (c) 2010 Isilon Systems, Inc. 3 * Copyright (c) 2010 iX Systems, Inc. 4 * Copyright (c) 2010 Panasas, Inc. 5 * Copyright (c) 2013-2016 Mellanox Technologies, Ltd. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD: stable/11/sys/compat/linuxkpi/common/include/linux/pci.h 306949 2016-10-10 11:30:35Z hselasky $ 30 */ 31#ifndef _LINUX_PCI_H_ 32#define _LINUX_PCI_H_ 33 34#define CONFIG_PCI_MSI 35 36#include <linux/types.h> 37 38#include <sys/param.h> 39#include <sys/bus.h> 40#include <sys/pciio.h> 41#include <sys/rman.h> 42#include <dev/pci/pcivar.h> 43#include <dev/pci/pcireg.h> 44#include <dev/pci/pci_private.h> 45 46#include <machine/resource.h> 47 48#include <linux/list.h> 49#include <linux/dmapool.h> 50#include <linux/dma-mapping.h> 51#include <linux/compiler.h> 52#include <linux/errno.h> 53#include <asm/atomic.h> 54#include <linux/device.h> 55 56struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class_mask; 62 uintptr_t driver_data; 63}; 64 65#define MODULE_DEVICE_TABLE(bus, table) 66#define PCI_ANY_ID (-1) 67#define PCI_VENDOR_ID_MELLANOX 0x15b3 68#define PCI_VENDOR_ID_TOPSPIN 0x1867 69#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 70#define PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE 0x5a46 71#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 72#define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 73#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c 74#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 75 76#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 77#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 78#define PCI_FUNC(devfn) ((devfn) & 0x07) 79 80#define PCI_VDEVICE(_vendor, _device) \ 81 .vendor = PCI_VENDOR_ID_##_vendor, .device = (_device), \ 82 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 83#define PCI_DEVICE(_vendor, _device) \ 84 .vendor = (_vendor), .device = (_device), \ 85 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 86 87#define to_pci_dev(n) container_of(n, struct pci_dev, dev) 88 89#define PCI_VENDOR_ID PCIR_DEVVENDOR 90#define PCI_COMMAND PCIR_COMMAND 91#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL /* Device Control */ 92#define PCI_EXP_LNKCTL PCIER_LINK_CTL /* Link Control */ 93#define PCI_EXP_FLAGS_TYPE PCIEM_FLAGS_TYPE /* Device/Port type */ 94#define PCI_EXP_DEVCAP PCIER_DEVICE_CAP /* Device capabilities */ 95#define PCI_EXP_DEVSTA PCIER_DEVICE_STA /* Device Status */ 96#define PCI_EXP_LNKCAP PCIER_LINK_CAP /* Link Capabilities */ 97#define PCI_EXP_LNKSTA PCIER_LINK_STA /* Link Status */ 98#define PCI_EXP_SLTCAP PCIER_SLOT_CAP /* Slot Capabilities */ 99#define PCI_EXP_SLTCTL PCIER_SLOT_CTL /* Slot Control */ 100#define PCI_EXP_SLTSTA PCIER_SLOT_STA /* Slot Status */ 101#define PCI_EXP_RTCTL PCIER_ROOT_CTL /* Root Control */ 102#define PCI_EXP_RTCAP PCIER_ROOT_CAP /* Root Capabilities */ 103#define PCI_EXP_RTSTA PCIER_ROOT_STA /* Root Status */ 104#define PCI_EXP_DEVCAP2 PCIER_DEVICE_CAP2 /* Device Capabilities 2 */ 105#define PCI_EXP_DEVCTL2 PCIER_DEVICE_CTL2 /* Device Control 2 */ 106#define PCI_EXP_LNKCAP2 PCIER_LINK_CAP2 /* Link Capabilities 2 */ 107#define PCI_EXP_LNKCTL2 PCIER_LINK_CTL2 /* Link Control 2 */ 108#define PCI_EXP_LNKSTA2 PCIER_LINK_STA2 /* Link Status 2 */ 109#define PCI_EXP_FLAGS PCIER_FLAGS /* Capabilities register */ 110#define PCI_EXP_FLAGS_VERS PCIEM_FLAGS_VERSION /* Capability version */ 111#define PCI_EXP_TYPE_ROOT_PORT PCIEM_TYPE_ROOT_PORT /* Root Port */ 112#define PCI_EXP_TYPE_ENDPOINT PCIEM_TYPE_ENDPOINT /* Express Endpoint */ 113#define PCI_EXP_TYPE_LEG_END PCIEM_TYPE_LEGACY_ENDPOINT /* Legacy Endpoint */ 114#define PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT /* Downstream Port */ 115#define PCI_EXP_FLAGS_SLOT PCIEM_FLAGS_SLOT /* Slot implemented */ 116#define PCI_EXP_TYPE_RC_EC PCIEM_TYPE_ROOT_EC /* Root Complex Event Collector */ 117#define PCI_EXP_LNKCAP_SLS_2_5GB 0x01 /* Supported Link Speed 2.5GT/s */ 118#define PCI_EXP_LNKCAP_SLS_5_0GB 0x02 /* Supported Link Speed 5.0GT/s */ 119#define PCI_EXP_LNKCAP_MLW 0x03f0 /* Maximum Link Width */ 120#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x02 /* Supported Link Speed 2.5GT/s */ 121#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x04 /* Supported Link Speed 5.0GT/s */ 122#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x08 /* Supported Link Speed 8.0GT/s */ 123 124#define IORESOURCE_MEM (1 << SYS_RES_MEMORY) 125#define IORESOURCE_IO (1 << SYS_RES_IOPORT) 126#define IORESOURCE_IRQ (1 << SYS_RES_IRQ) 127 128enum pci_bus_speed { 129 PCI_SPEED_UNKNOWN = -1, 130 PCIE_SPEED_2_5GT, 131 PCIE_SPEED_5_0GT, 132 PCIE_SPEED_8_0GT, 133}; 134 135enum pcie_link_width { 136 PCIE_LNK_WIDTH_UNKNOWN = -1, 137}; 138 139struct pci_dev; 140 141struct pci_driver { 142 struct list_head links; 143 char *name; 144 const struct pci_device_id *id_table; 145 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 146 void (*remove)(struct pci_dev *dev); 147 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 148 int (*resume) (struct pci_dev *dev); /* Device woken up */ 149 void (*shutdown) (struct pci_dev *dev); /* Device shutdown */ 150 driver_t driver; 151 devclass_t bsdclass; 152 const struct pci_error_handlers *err_handler; 153}; 154 155extern struct list_head pci_drivers; 156extern struct list_head pci_devices; 157extern spinlock_t pci_lock; 158 159#define __devexit_p(x) x 160 161struct pci_dev { 162 struct device dev; 163 struct list_head links; 164 struct pci_driver *pdrv; 165 uint64_t dma_mask; 166 uint16_t device; 167 uint16_t vendor; 168 unsigned int irq; 169 unsigned int devfn; 170 u8 revision; 171}; 172 173static inline struct resource_list_entry * 174_pci_get_rle(struct pci_dev *pdev, int type, int rid) 175{ 176 struct pci_devinfo *dinfo; 177 struct resource_list *rl; 178 179 dinfo = device_get_ivars(pdev->dev.bsddev); 180 rl = &dinfo->resources; 181 return resource_list_find(rl, type, rid); 182} 183 184static inline struct resource_list_entry * 185_pci_get_bar(struct pci_dev *pdev, int bar) 186{ 187 struct resource_list_entry *rle; 188 189 bar = PCIR_BAR(bar); 190 if ((rle = _pci_get_rle(pdev, SYS_RES_MEMORY, bar)) == NULL) 191 rle = _pci_get_rle(pdev, SYS_RES_IOPORT, bar); 192 return (rle); 193} 194 195static inline struct device * 196_pci_find_irq_dev(unsigned int irq) 197{ 198 struct pci_dev *pdev; 199 200 spin_lock(&pci_lock); 201 list_for_each_entry(pdev, &pci_devices, links) { 202 if (irq == pdev->dev.irq) 203 break; 204 if (irq >= pdev->dev.msix && irq < pdev->dev.msix_max) 205 break; 206 } 207 spin_unlock(&pci_lock); 208 if (pdev) 209 return &pdev->dev; 210 return (NULL); 211} 212 213static inline unsigned long 214pci_resource_start(struct pci_dev *pdev, int bar) 215{ 216 struct resource_list_entry *rle; 217 218 if ((rle = _pci_get_bar(pdev, bar)) == NULL) 219 return (0); 220 return rle->start; 221} 222 223static inline unsigned long 224pci_resource_len(struct pci_dev *pdev, int bar) 225{ 226 struct resource_list_entry *rle; 227 228 if ((rle = _pci_get_bar(pdev, bar)) == NULL) 229 return (0); 230 return rle->count; 231} 232 233static inline int 234pci_resource_type(struct pci_dev *pdev, int bar) 235{ 236 struct resource_list_entry *rle; 237 238 if ((rle = _pci_get_bar(pdev, bar)) == NULL) 239 return (-1); 240 return (rle->type); 241} 242 243/* 244 * All drivers just seem to want to inspect the type not flags. 245 */ 246static inline int 247pci_resource_flags(struct pci_dev *pdev, int bar) 248{ 249 int type; 250 251 type = pci_resource_type(pdev, bar); 252 if (type < 0) 253 return (0); 254 return (1 << type); 255} 256 257static inline const char * 258pci_name(struct pci_dev *d) 259{ 260 261 return device_get_desc(d->dev.bsddev); 262} 263 264static inline void * 265pci_get_drvdata(struct pci_dev *pdev) 266{ 267 268 return dev_get_drvdata(&pdev->dev); 269} 270 271static inline void 272pci_set_drvdata(struct pci_dev *pdev, void *data) 273{ 274 275 dev_set_drvdata(&pdev->dev, data); 276} 277 278static inline int 279pci_enable_device(struct pci_dev *pdev) 280{ 281 282 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 283 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 284 return (0); 285} 286 287static inline void 288pci_disable_device(struct pci_dev *pdev) 289{ 290} 291 292static inline int 293pci_set_master(struct pci_dev *pdev) 294{ 295 296 pci_enable_busmaster(pdev->dev.bsddev); 297 return (0); 298} 299 300static inline int 301pci_clear_master(struct pci_dev *pdev) 302{ 303 304 pci_disable_busmaster(pdev->dev.bsddev); 305 return (0); 306} 307 308static inline int 309pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 310{ 311 int rid; 312 int type; 313 314 type = pci_resource_type(pdev, bar); 315 if (type < 0) 316 return (-ENODEV); 317 rid = PCIR_BAR(bar); 318 if (bus_alloc_resource_any(pdev->dev.bsddev, type, &rid, 319 RF_ACTIVE) == NULL) 320 return (-EINVAL); 321 return (0); 322} 323 324static inline void 325pci_release_region(struct pci_dev *pdev, int bar) 326{ 327 struct resource_list_entry *rle; 328 329 if ((rle = _pci_get_bar(pdev, bar)) == NULL) 330 return; 331 bus_release_resource(pdev->dev.bsddev, rle->type, rle->rid, rle->res); 332} 333 334static inline void 335pci_release_regions(struct pci_dev *pdev) 336{ 337 int i; 338 339 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 340 pci_release_region(pdev, i); 341} 342 343static inline int 344pci_request_regions(struct pci_dev *pdev, const char *res_name) 345{ 346 int error; 347 int i; 348 349 for (i = 0; i <= PCIR_MAX_BAR_0; i++) { 350 error = pci_request_region(pdev, i, res_name); 351 if (error && error != -ENODEV) { 352 pci_release_regions(pdev); 353 return (error); 354 } 355 } 356 return (0); 357} 358 359static inline void 360pci_disable_msix(struct pci_dev *pdev) 361{ 362 363 pci_release_msi(pdev->dev.bsddev); 364} 365 366#define PCI_CAP_ID_EXP PCIY_EXPRESS 367#define PCI_CAP_ID_PCIX PCIY_PCIX 368 369 370static inline int 371pci_find_capability(struct pci_dev *pdev, int capid) 372{ 373 int reg; 374 375 if (pci_find_cap(pdev->dev.bsddev, capid, ®)) 376 return (0); 377 return (reg); 378} 379 380static inline int pci_pcie_cap(struct pci_dev *dev) 381{ 382 return pci_find_capability(dev, PCI_CAP_ID_EXP); 383} 384 385 386static inline int 387pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 388{ 389 390 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 391 return (0); 392} 393 394static inline int 395pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 396{ 397 398 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 399 return (0); 400} 401 402static inline int 403pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 404{ 405 406 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 407 return (0); 408} 409 410static inline int 411pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 412{ 413 414 pci_write_config(pdev->dev.bsddev, where, val, 1); 415 return (0); 416} 417 418static inline int 419pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 420{ 421 422 pci_write_config(pdev->dev.bsddev, where, val, 2); 423 return (0); 424} 425 426static inline int 427pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 428{ 429 430 pci_write_config(pdev->dev.bsddev, where, val, 4); 431 return (0); 432} 433 434extern int pci_register_driver(struct pci_driver *pdrv); 435extern void pci_unregister_driver(struct pci_driver *pdrv); 436 437struct msix_entry { 438 int entry; 439 int vector; 440}; 441 442/* 443 * Enable msix, positive errors indicate actual number of available 444 * vectors. Negative errors are failures. 445 * 446 * NB: define added to prevent this definition of pci_enable_msix from 447 * clashing with the native FreeBSD version. 448 */ 449#define pci_enable_msix linux_pci_enable_msix 450static inline int 451pci_enable_msix(struct pci_dev *pdev, struct msix_entry *entries, int nreq) 452{ 453 struct resource_list_entry *rle; 454 int error; 455 int avail; 456 int i; 457 458 avail = pci_msix_count(pdev->dev.bsddev); 459 if (avail < nreq) { 460 if (avail == 0) 461 return -EINVAL; 462 return avail; 463 } 464 avail = nreq; 465 if ((error = -pci_alloc_msix(pdev->dev.bsddev, &avail)) != 0) 466 return error; 467 /* 468 * Handle case where "pci_alloc_msix()" may allocate less 469 * interrupts than available and return with no error: 470 */ 471 if (avail < nreq) { 472 pci_release_msi(pdev->dev.bsddev); 473 return avail; 474 } 475 rle = _pci_get_rle(pdev, SYS_RES_IRQ, 1); 476 pdev->dev.msix = rle->start; 477 pdev->dev.msix_max = rle->start + avail; 478 for (i = 0; i < nreq; i++) 479 entries[i].vector = pdev->dev.msix + i; 480 return (0); 481} 482 483#define pci_enable_msix_range linux_pci_enable_msix_range 484static inline int 485pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, 486 int minvec, int maxvec) 487{ 488 int nvec = maxvec; 489 int rc; 490 491 if (maxvec < minvec) 492 return (-ERANGE); 493 494 do { 495 rc = pci_enable_msix(dev, entries, nvec); 496 if (rc < 0) { 497 return (rc); 498 } else if (rc > 0) { 499 if (rc < minvec) 500 return (-ENOSPC); 501 nvec = rc; 502 } 503 } while (rc); 504 return (nvec); 505} 506 507static inline int pci_channel_offline(struct pci_dev *pdev) 508{ 509 return false; 510} 511 512static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) 513{ 514 return -ENODEV; 515} 516static inline void pci_disable_sriov(struct pci_dev *dev) 517{ 518} 519 520#define DEFINE_PCI_DEVICE_TABLE(_table) \ 521 const struct pci_device_id _table[] __devinitdata 522 523 524/* XXX This should not be necessary. */ 525#define pcix_set_mmrbc(d, v) 0 526#define pcix_get_max_mmrbc(d) 0 527#define pcie_set_readrq(d, v) 0 528 529#define PCI_DMA_BIDIRECTIONAL 0 530#define PCI_DMA_TODEVICE 1 531#define PCI_DMA_FROMDEVICE 2 532#define PCI_DMA_NONE 3 533 534#define pci_pool dma_pool 535#define pci_pool_destroy dma_pool_destroy 536#define pci_pool_alloc dma_pool_alloc 537#define pci_pool_free dma_pool_free 538#define pci_pool_create(_name, _pdev, _size, _align, _alloc) \ 539 dma_pool_create(_name, &(_pdev)->dev, _size, _align, _alloc) 540#define pci_free_consistent(_hwdev, _size, _vaddr, _dma_handle) \ 541 dma_free_coherent((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 542 _size, _vaddr, _dma_handle) 543#define pci_map_sg(_hwdev, _sg, _nents, _dir) \ 544 dma_map_sg((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 545 _sg, _nents, (enum dma_data_direction)_dir) 546#define pci_map_single(_hwdev, _ptr, _size, _dir) \ 547 dma_map_single((_hwdev) == NULL ? NULL : &(_hwdev->dev), \ 548 (_ptr), (_size), (enum dma_data_direction)_dir) 549#define pci_unmap_single(_hwdev, _addr, _size, _dir) \ 550 dma_unmap_single((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 551 _addr, _size, (enum dma_data_direction)_dir) 552#define pci_unmap_sg(_hwdev, _sg, _nents, _dir) \ 553 dma_unmap_sg((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 554 _sg, _nents, (enum dma_data_direction)_dir) 555#define pci_map_page(_hwdev, _page, _offset, _size, _dir) \ 556 dma_map_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, _page,\ 557 _offset, _size, (enum dma_data_direction)_dir) 558#define pci_unmap_page(_hwdev, _dma_address, _size, _dir) \ 559 dma_unmap_page((_hwdev) == NULL ? NULL : &(_hwdev)->dev, \ 560 _dma_address, _size, (enum dma_data_direction)_dir) 561#define pci_set_dma_mask(_pdev, mask) dma_set_mask(&(_pdev)->dev, (mask)) 562#define pci_dma_mapping_error(_pdev, _dma_addr) \ 563 dma_mapping_error(&(_pdev)->dev, _dma_addr) 564#define pci_set_consistent_dma_mask(_pdev, _mask) \ 565 dma_set_coherent_mask(&(_pdev)->dev, (_mask)) 566#define DECLARE_PCI_UNMAP_ADDR(x) DEFINE_DMA_UNMAP_ADDR(x); 567#define DECLARE_PCI_UNMAP_LEN(x) DEFINE_DMA_UNMAP_LEN(x); 568#define pci_unmap_addr dma_unmap_addr 569#define pci_unmap_addr_set dma_unmap_addr_set 570#define pci_unmap_len dma_unmap_len 571#define pci_unmap_len_set dma_unmap_len_set 572 573typedef unsigned int __bitwise pci_channel_state_t; 574typedef unsigned int __bitwise pci_ers_result_t; 575 576enum pci_channel_state { 577 pci_channel_io_normal = 1, 578 pci_channel_io_frozen = 2, 579 pci_channel_io_perm_failure = 3, 580}; 581 582enum pci_ers_result { 583 PCI_ERS_RESULT_NONE = 1, 584 PCI_ERS_RESULT_CAN_RECOVER = 2, 585 PCI_ERS_RESULT_NEED_RESET = 3, 586 PCI_ERS_RESULT_DISCONNECT = 4, 587 PCI_ERS_RESULT_RECOVERED = 5, 588}; 589 590 591/* PCI bus error event callbacks */ 592struct pci_error_handlers { 593 pci_ers_result_t (*error_detected)(struct pci_dev *dev, 594 enum pci_channel_state error); 595 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); 596 pci_ers_result_t (*link_reset)(struct pci_dev *dev); 597 pci_ers_result_t (*slot_reset)(struct pci_dev *dev); 598 void (*resume)(struct pci_dev *dev); 599}; 600 601/* FreeBSD does not support SRIOV - yet */ 602static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 603{ 604 return dev; 605} 606 607static inline bool pci_is_pcie(struct pci_dev *dev) 608{ 609 return !!pci_pcie_cap(dev); 610} 611 612static inline u16 pcie_flags_reg(struct pci_dev *dev) 613{ 614 int pos; 615 u16 reg16; 616 617 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 618 if (!pos) 619 return 0; 620 621 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 622 623 return reg16; 624} 625 626 627static inline int pci_pcie_type(struct pci_dev *dev) 628{ 629 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 630} 631 632static inline int pcie_cap_version(struct pci_dev *dev) 633{ 634 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 635} 636 637static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 638{ 639 int type = pci_pcie_type(dev); 640 641 return pcie_cap_version(dev) > 1 || 642 type == PCI_EXP_TYPE_ROOT_PORT || 643 type == PCI_EXP_TYPE_ENDPOINT || 644 type == PCI_EXP_TYPE_LEG_END; 645} 646 647static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 648{ 649 return true; 650} 651 652static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 653{ 654 int type = pci_pcie_type(dev); 655 656 return pcie_cap_version(dev) > 1 || 657 type == PCI_EXP_TYPE_ROOT_PORT || 658 (type == PCI_EXP_TYPE_DOWNSTREAM && 659 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 660} 661 662static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 663{ 664 int type = pci_pcie_type(dev); 665 666 return pcie_cap_version(dev) > 1 || 667 type == PCI_EXP_TYPE_ROOT_PORT || 668 type == PCI_EXP_TYPE_RC_EC; 669} 670 671static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 672{ 673 if (!pci_is_pcie(dev)) 674 return false; 675 676 switch (pos) { 677 case PCI_EXP_FLAGS_TYPE: 678 return true; 679 case PCI_EXP_DEVCAP: 680 case PCI_EXP_DEVCTL: 681 case PCI_EXP_DEVSTA: 682 return pcie_cap_has_devctl(dev); 683 case PCI_EXP_LNKCAP: 684 case PCI_EXP_LNKCTL: 685 case PCI_EXP_LNKSTA: 686 return pcie_cap_has_lnkctl(dev); 687 case PCI_EXP_SLTCAP: 688 case PCI_EXP_SLTCTL: 689 case PCI_EXP_SLTSTA: 690 return pcie_cap_has_sltctl(dev); 691 case PCI_EXP_RTCTL: 692 case PCI_EXP_RTCAP: 693 case PCI_EXP_RTSTA: 694 return pcie_cap_has_rtctl(dev); 695 case PCI_EXP_DEVCAP2: 696 case PCI_EXP_DEVCTL2: 697 case PCI_EXP_LNKCAP2: 698 case PCI_EXP_LNKCTL2: 699 case PCI_EXP_LNKSTA2: 700 return pcie_cap_version(dev) > 1; 701 default: 702 return false; 703 } 704} 705 706static inline int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst) 707{ 708 if (pos & 3) 709 return -EINVAL; 710 711 if (!pcie_capability_reg_implemented(dev, pos)) 712 return -EINVAL; 713 714 return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst); 715} 716 717static inline int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val) 718{ 719 if (pos & 1) 720 return -EINVAL; 721 722 if (!pcie_capability_reg_implemented(dev, pos)) 723 return 0; 724 725 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val); 726} 727 728static inline int pcie_get_minimum_link(struct pci_dev *dev, 729 enum pci_bus_speed *speed, enum pcie_link_width *width) 730{ 731 *speed = PCI_SPEED_UNKNOWN; 732 *width = PCIE_LNK_WIDTH_UNKNOWN; 733 return (0); 734} 735 736static inline int 737pci_num_vf(struct pci_dev *dev) 738{ 739 return (0); 740} 741 742#endif /* _LINUX_PCI_H_ */ 743