socfpga.dtsi revision 302408
1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: stable/11/sys/boot/fdt/dts/arm/socfpga.dtsi 276533 2015-01-02 13:15:36Z br $ 31 */ 32 33/ { 34 compatible = "altr,socfpga"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 interrupt-parent = <&GIC>; 39 40 aliases { 41 soc = &SOC; 42 rstmgr = &rstmgr; 43 l3regs = &l3regs; 44 serial0 = &serial0; 45 serial1 = &serial1; 46 }; 47 48 SOC: socfpga { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 compatible = "simple-bus"; 52 ranges; 53 bus-frequency = <0>; 54 55 GIC: interrupt-controller@fffed000 { 56 compatible = "arm,gic"; 57 reg = < 0xfffed000 0x1000 >, /* Distributor */ 58 < 0xfffec100 0x100 >; /* CPU Interface */ 59 interrupt-controller; 60 #interrupt-cells = <1>; 61 }; 62 63 mp_tmr@40002100 { 64 compatible = "arm,mpcore-timers"; 65 clock-frequency = <200000000>; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 reg = < 0xfffec200 0x100 >, /* Global Timer */ 69 < 0xfffec600 0x100 >; /* Private Timer */ 70 interrupts = < 27 29 >; 71 interrupt-parent = < &GIC >; 72 }; 73 74 sysmgr: sysmgr@ffd08000 { 75 compatible = "altr,sys-mgr"; 76 reg = <0xffd08000 0x1000>; 77 }; 78 79 clkmgr: clkmgr@ffd04000 { 80 compatible = "altr,clk-mgr"; 81 reg = <0xffd04000 0x1000>; 82 }; 83 84 rstmgr: rstmgr@ffd05000 { 85 compatible = "altr,rst-mgr"; 86 reg = <0xffd05000 0x1000>; 87 }; 88 89 l3regs: l3regs@ff800000 { 90 compatible = "altr,l3regs"; 91 reg = <0xff800000 0x1000>; 92 }; 93 94 fpgamgr: fpgamgr@ff706000 { 95 compatible = "altr,fpga-mgr"; 96 reg = <0xff706000 0x1000>, /* FPGAMGRREGS */ 97 <0xffb90000 0x1000>; /* FPGAMGRDATA */ 98 interrupts = < 207 >; 99 interrupt-parent = <&GIC>; 100 }; 101 102 gpio0: gpio@ff708000 { 103 compatible = "snps,dw-apb-gpio"; 104 reg = <0xff708000 0x1000>; 105 porta: gpio-controller@0 { 106 compatible = "snps,dw-apb-gpio-port"; 107 gpio-controller; 108 snps,nr-gpios = <29>; 109 }; 110 }; 111 112 gpio1: gpio@ff709000 { 113 compatible = "snps,dw-apb-gpio"; 114 reg = <0xff709000 0x1000>; 115 portb: gpio-controller@0 { 116 compatible = "snps,dw-apb-gpio-port"; 117 gpio-controller; 118 snps,nr-gpios = <29>; 119 }; 120 }; 121 122 gpio2: gpio@ff70a000 { 123 compatible = "snps,dw-apb-gpio"; 124 reg = <0xff70a000 0x1000>; 125 portc: gpio-controller@0 { 126 compatible = "snps,dw-apb-gpio-port"; 127 gpio-controller; 128 snps,nr-gpios = <27>; 129 }; 130 }; 131 132 serial0: serial@ffc02000 { 133 compatible = "ns16550"; 134 reg = <0xffc02000 0x1000>; 135 reg-shift = <2>; 136 interrupts = <194>; 137 interrupt-parent = <&GIC>; 138 current-speed = <115200>; 139 clock-frequency = < 100000000 >; 140 status = "disabled"; 141 }; 142 143 serial1: serial@ffc03000 { 144 compatible = "ns16550"; 145 reg = <0xffc03000 0x1000>; 146 reg-shift = <2>; 147 interrupts = <195>; 148 interrupt-parent = <&GIC>; 149 current-speed = <115200>; 150 clock-frequency = < 100000000 >; 151 status = "disabled"; 152 }; 153 154 usb0: usb@ffb00000 { 155 compatible = "synopsys,designware-hs-otg2"; 156 reg = <0xffb00000 0xffff>; 157 interrupts = <157>; 158 interrupt-parent = <&GIC>; 159 status = "disabled"; 160 }; 161 162 usb1: usb@ffb40000 { 163 compatible = "synopsys,designware-hs-otg2"; 164 reg = <0xffb40000 0xffff>; 165 interrupts = <160>; 166 interrupt-parent = <&GIC>; 167 dr_mode = "host"; 168 status = "disabled"; 169 }; 170 171 gmac0: ethernet@ff700000 { 172 compatible = "altr,socfpga-stmmac", 173 "snps,dwmac-3.70a", "snps,dwmac"; 174 reg = <0xff700000 0x2000>; 175 interrupts = <147>; 176 interrupt-parent = <&GIC>; 177 phy-mode = "rgmii"; 178 status = "disabled"; 179 }; 180 181 gmac1: ethernet@ff702000 { 182 compatible = "altr,socfpga-stmmac", 183 "snps,dwmac-3.70a", "snps,dwmac"; 184 reg = <0xff702000 0x2000>; 185 interrupts = <152>; 186 interrupt-parent = <&GIC>; 187 phy-mode = "rgmii"; 188 status = "disabled"; 189 }; 190 191 mmc: dwmmc@ff704000 { 192 compatible = "altr,socfpga-dw-mshc"; 193 reg = <0xff704000 0x1000>; 194 interrupts = <171>; 195 interrupt-parent = <&GIC>; 196 fifo-depth = <0x400>; 197 status = "disabled"; 198 }; 199 }; 200}; 201