socfpga.dtsi revision 271431 
1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 271431 2014-09-11 18:12:28Z br $
31 */
32
33/ {
34	compatible = "altr,socfpga";
35	#address-cells = <1>;
36	#size-cells = <1>;
37
38	interrupt-parent = <&GIC>;
39
40	aliases {
41		soc = &SOC;
42		rstmgr = &rstmgr;
43		l3regs = &l3regs;
44		serial0 = &serial0;
45		serial1 = &serial1;
46	};
47
48	SOC: socfpga {
49		#address-cells = <1>;
50		#size-cells = <1>;
51		compatible = "simple-bus";
52		ranges;
53		bus-frequency = <0>;
54
55		GIC: interrupt-controller@fffed000 {
56			compatible = "arm,gic";
57			reg = < 0xfffed000 0x1000 >, /* Distributor */
58			      < 0xfffec100 0x100 >; /* CPU Interface */
59			interrupt-controller;
60			#interrupt-cells = <1>;
61		};
62
63		mp_tmr@40002100 {
64			compatible = "arm,mpcore-timers";
65			clock-frequency = <200000000>;
66			#address-cells = <1>;
67			#size-cells = <0>;
68			reg = < 0xfffec200 0x100 >, /* Global Timer */
69			      < 0xfffec600 0x100 >; /* Private Timer */
70			interrupts = < 27 29 >;
71			interrupt-parent = < &GIC >;
72		};
73
74		rstmgr: rstmgr@ffd05000 {
75			compatible = "altr,rst-mgr";
76			reg = <0xffd05000 0x1000>;
77		};
78
79		l3regs: l3regs@ff800000 {
80			compatible = "altr,l3regs";
81			reg = <0xff800000 0x1000>;
82		};
83
84		fpgamgr: fpgamgr@ff706000 {
85			compatible = "altr,fpga-mgr";
86			reg = <0xff706000 0x1000>, /* FPGAMGRREGS */
87			      <0xffb90000 0x1000>; /* FPGAMGRDATA */
88			interrupts = < 207 >;
89			interrupt-parent = <&GIC>;
90		};
91
92		serial0: serial@ffc02000 {
93			compatible = "ns16550";
94			reg = <0xffc02000 0x1000>;
95			reg-shift = <2>;
96			interrupts = <194>;
97			interrupt-parent = <&GIC>;
98			current-speed = <115200>;
99			clock-frequency = < 100000000 >;
100			status = "disabled";
101		};
102
103		serial1: serial@ffc03000 {
104			compatible = "ns16550";
105			reg = <0xffc03000 0x1000>;
106			reg-shift = <2>;
107			interrupts = <195>;
108			interrupt-parent = <&GIC>;
109			current-speed = <115200>;
110			clock-frequency = < 100000000 >;
111			status = "disabled";
112		};
113
114		usb0: usb@ffb00000 {
115			compatible = "synopsys,designware-hs-otg2";
116			reg = <0xffb00000 0xffff>;
117			interrupts = <157>;
118			interrupt-parent = <&GIC>;
119			status = "disabled";
120		};
121
122		usb1: usb@ffb40000 {
123			compatible = "synopsys,designware-hs-otg2";
124			reg = <0xffb40000 0xffff>;
125			interrupts = <160>;
126			interrupt-parent = <&GIC>;
127			dr_mode = "host";
128			status = "disabled";
129		};
130	};
131};
132