socfpga.dtsi revision 271186 
1/*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 271186 2014-09-06 08:48:57Z br $
31 */
32
33/ {
34	compatible = "altr,socfpga";
35	#address-cells = <1>;
36	#size-cells = <1>;
37
38	interrupt-parent = <&GIC>;
39
40	aliases {
41		soc = &SOC;
42		serial0 = &serial0;
43		serial1 = &serial1;
44	};
45
46	SOC: socfpga {
47		#address-cells = <1>;
48		#size-cells = <1>;
49		compatible = "simple-bus";
50		ranges;
51		bus-frequency = <0>;
52
53		GIC: interrupt-controller@fffed000 {
54			compatible = "arm,gic";
55			reg = < 0xfffed000 0x1000 >, /* Distributor */
56			      < 0xfffec100 0x100 >; /* CPU Interface */
57			interrupt-controller;
58			#interrupt-cells = <1>;
59		};
60
61		mp_tmr@40002100 {
62			compatible = "arm,mpcore-timers";
63			clock-frequency = <200000000>;
64			#address-cells = <1>;
65			#size-cells = <0>;
66			reg = < 0xfffec200 0x100 >, /* Global Timer */
67			      < 0xfffec600 0x100 >; /* Private Timer */
68			interrupts = < 27 29 >;
69			interrupt-parent = < &GIC >;
70		};
71
72		fpgamgr: fpgamgr@ff706000 {
73			compatible = "altr,fpga-mgr";
74			reg = <0xff706000 0x1000>, /* FPGAMGRREGS */
75			      <0xffb90000 0x1000>; /* FPGAMGRDATA */
76			interrupts = < 207 >;
77			interrupt-parent = <&GIC>;
78		};
79
80		serial0: serial@ffc02000 {
81			compatible = "ns16550";
82			reg = <0xffc02000 0x1000>;
83			reg-shift = <2>;
84			interrupts = <194>;
85			interrupt-parent = <&GIC>;
86			current-speed = <115200>;
87			clock-frequency = < 100000000 >;
88			status = "disabled";
89		};
90
91		serial1: serial@ffc03000 {
92			compatible = "ns16550";
93			reg = <0xffc03000 0x1000>;
94			reg-shift = <2>;
95			interrupts = <195>;
96			interrupt-parent = <&GIC>;
97			current-speed = <115200>;
98			clock-frequency = < 100000000 >;
99			status = "disabled";
100		};
101
102		usb0: usb@ffb00000 {
103			compatible = "synopsys,designware-hs-otg2";
104			reg = <0xffb00000 0xffff>;
105			interrupts = <157>;
106			interrupt-parent = <&GIC>;
107			status = "disabled";
108		};
109
110		usb1: usb@ffb40000 {
111			compatible = "synopsys,designware-hs-otg2";
112			reg = <0xffb40000 0xffff>;
113			interrupts = <160>;
114			interrupt-parent = <&GIC>;
115			dr_mode = "host";
116			status = "disabled";
117		};
118	};
119};
120