socfpga.dtsi revision 271093
1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD: head/sys/boot/fdt/dts/arm/socfpga.dtsi 271093 2014-09-04 12:44:40Z br $ 31 */ 32 33/ { 34 compatible = "altr,socfpga"; 35 #address-cells = <1>; 36 #size-cells = <1>; 37 38 interrupt-parent = <&GIC>; 39 40 aliases { 41 soc = &SOC; 42 serial0 = &serial0; 43 serial1 = &serial1; 44 }; 45 46 SOC: socfpga { 47 #address-cells = <1>; 48 #size-cells = <1>; 49 compatible = "simple-bus"; 50 ranges; 51 bus-frequency = <0>; 52 53 GIC: interrupt-controller@fffed000 { 54 compatible = "arm,gic"; 55 reg = < 0xfffed000 0x1000 >, /* Distributor */ 56 < 0xfffec100 0x100 >; /* CPU Interface */ 57 interrupt-controller; 58 #interrupt-cells = <1>; 59 }; 60 61 mp_tmr@40002100 { 62 compatible = "arm,mpcore-timers"; 63 clock-frequency = <200000000>; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 reg = < 0xfffec200 0x100 >, /* Global Timer */ 67 < 0xfffec600 0x100 >; /* Private Timer */ 68 interrupts = < 27 29 >; 69 interrupt-parent = < &GIC >; 70 }; 71 72 serial0: serial@ffc02000 { 73 compatible = "ns16550"; 74 reg = <0xffc02000 0x1000>; 75 reg-shift = <2>; 76 interrupts = <194>; 77 interrupt-parent = <&GIC>; 78 current-speed = <115200>; 79 clock-frequency = < 100000000 >; 80 status = "disabled"; 81 }; 82 83 serial1: serial@ffc03000 { 84 compatible = "ns16550"; 85 reg = <0xffc03000 0x1000>; 86 reg-shift = <2>; 87 interrupts = <195>; 88 interrupt-parent = <&GIC>; 89 current-speed = <115200>; 90 clock-frequency = < 100000000 >; 91 status = "disabled"; 92 }; 93 94 usb0: usb@ffb00000 { 95 compatible = "synopsys,designware-hs-otg2"; 96 reg = <0xffb00000 0xffff>; 97 interrupts = <157>; 98 interrupt-parent = <&GIC>; 99 status = "disabled"; 100 }; 101 102 usb1: usb@ffb40000 { 103 compatible = "synopsys,designware-hs-otg2"; 104 reg = <0xffb40000 0xffff>; 105 interrupts = <160>; 106 interrupt-parent = <&GIC>; 107 dr_mode = "host"; 108 status = "disabled"; 109 }; 110 }; 111}; 112