1281413Sganbold/*- 2281413Sganbold * Copyright (c) 2015 John Wehle <john@feith.com> 3281413Sganbold * All rights reserved. 4281413Sganbold * 5281413Sganbold * Redistribution and use in source and binary forms, with or without 6281413Sganbold * modification, are permitted provided that the following conditions 7281413Sganbold * are met: 8281413Sganbold * 1. Redistributions of source code must retain the above copyright 9281413Sganbold * notice, this list of conditions and the following disclaimer. 10281413Sganbold * 2. Redistributions in binary form must reproduce the above copyright 11281413Sganbold * notice, this list of conditions and the following disclaimer in the 12281413Sganbold * documentation and/or other materials provided with the distribution. 13281413Sganbold * 14281413Sganbold * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15281413Sganbold * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16281413Sganbold * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17281413Sganbold * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18281413Sganbold * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19281413Sganbold * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20281413Sganbold * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21281413Sganbold * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22281413Sganbold * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23281413Sganbold * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24281413Sganbold * SUCH DAMAGE. 25281413Sganbold * 26281413Sganbold * $FreeBSD$ 27281413Sganbold */ 28281413Sganbold 29281413Sganbold/include/ "meson.dtsi" 30281413Sganbold 31281413Sganbold/ { 32281413Sganbold model = "Amlogic Meson8b SoC"; 33281413Sganbold compatible = "amlogic,meson8b"; 34281413Sganbold 35281413Sganbold interrupt-parent = <&gic>; 36281413Sganbold 37281413Sganbold cpus { 38281413Sganbold #address-cells = <1>; 39281413Sganbold #size-cells = <0>; 40281413Sganbold 41281413Sganbold cpu@200 { 42281413Sganbold device_type = "cpu"; 43281413Sganbold compatible = "arm,cortex-a5"; 44281413Sganbold next-level-cache = <&L2>; 45281413Sganbold reg = <0x200>; 46281413Sganbold }; 47281413Sganbold 48281413Sganbold cpu@201 { 49281413Sganbold device_type = "cpu"; 50281413Sganbold compatible = "arm,cortex-a5"; 51281413Sganbold next-level-cache = <&L2>; 52281413Sganbold reg = <0x201>; 53281413Sganbold }; 54281413Sganbold 55281413Sganbold cpu@202 { 56281413Sganbold device_type = "cpu"; 57281413Sganbold compatible = "arm,cortex-a5"; 58281413Sganbold next-level-cache = <&L2>; 59281413Sganbold reg = <0x202>; 60281413Sganbold }; 61281413Sganbold 62281413Sganbold cpu@203 { 63281413Sganbold device_type = "cpu"; 64281413Sganbold compatible = "arm,cortex-a5"; 65281413Sganbold next-level-cache = <&L2>; 66281413Sganbold reg = <0x203>; 67281413Sganbold }; 68281413Sganbold }; 69281413Sganbold 70281413Sganbold clk81: clk@0 { 71281413Sganbold #clock-cells = <0>; 72281413Sganbold compatible = "fixed-clock"; 73281413Sganbold clock-frequency = <0>; 74281413Sganbold }; 75281413Sganbold}; 76281413Sganbold 77281413Sganbold&L2 { 78281413Sganbold interrupts = <0 143 1>; 79281413Sganbold}; 80