dockstar.dts revision 262614
1/* 2 * Copyright (c) 2010 The FreeBSD Foundation 3 * All rights reserved. 4 * 5 * This software was developed by Semihalf under sponsorship from 6 * the FreeBSD Foundation. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Seagate DockStar (Marvell SheevaPlug based) Device Tree Source. 30 * 31 * $FreeBSD: head/sys/boot/fdt/dts/arm/dockstar.dts 262614 2014-02-28 18:29:09Z imp $ 32 */ 33 34/dts-v1/; 35 36/ { 37 model = "seagate,DockStar"; 38 compatible = "DockStar"; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 42 aliases { 43 ethernet0 = &enet0; 44 mpp = &MPP; 45 serial0 = &serial0; 46 serial1 = &serial1; 47 soc = &SOC; 48 sram = &SRAM; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 cpu@0 { 56 device_type = "cpu"; 57 compatible = "ARM,88FR131"; 58 reg = <0x0>; 59 d-cache-line-size = <32>; // 32 bytes 60 i-cache-line-size = <32>; // 32 bytes 61 d-cache-size = <0x4000>; // L1, 16K 62 i-cache-size = <0x4000>; // L1, 16K 63 timebase-frequency = <0>; 64 bus-frequency = <0>; 65 clock-frequency = <0>; 66 }; 67 }; 68 69 memory { 70 device_type = "memory"; 71 reg = <0x0 0x8000000>; // 128M at 0x0 72 }; 73 74 localbus@f1000000 { 75 #address-cells = <2>; 76 #size-cells = <1>; 77 compatible = "mrvl,lbc"; 78 79 /* This reflects CPU decode windows setup for NAND access. */ 80 ranges = <0x0 0x2f 0xf9300000 0x00100000>; 81 82 nand@0,0 { 83 #address-cells = <1>; 84 #size-cells = <1>; 85 compatible = "mrvl,nfc"; 86 reg = <0x0 0x0 0x00100000>; 87 bank-width = <2>; 88 device-width = <1>; 89 }; 90 }; 91 92 SOC: soc88f6281@f1000000 { 93 #address-cells = <1>; 94 #size-cells = <1>; 95 compatible = "simple-bus"; 96 ranges = <0x0 0xf1000000 0x00100000>; 97 bus-frequency = <0>; 98 99 PIC: pic@20200 { 100 interrupt-controller; 101 #address-cells = <0>; 102 #interrupt-cells = <1>; 103 reg = <0x20200 0x3c>; 104 compatible = "mrvl,pic"; 105 }; 106 107 timer@20300 { 108 compatible = "mrvl,timer"; 109 reg = <0x20300 0x30>; 110 interrupts = <1>; 111 interrupt-parent = <&PIC>; 112 mrvl,has-wdt; 113 }; 114 115 MPP: mpp@10000 { 116 #pin-cells = <2>; 117 compatible = "mrvl,mpp"; 118 reg = <0x10000 0x34>; 119 pin-count = <50>; 120 pin-map = < 121 0 1 /* MPP[0]: NF_IO[2] */ 122 1 1 /* MPP[1]: NF_IO[3] */ 123 2 1 /* MPP[2]: NF_IO[4] */ 124 3 1 /* MPP[3]: NF_IO[5] */ 125 4 1 /* MPP[4]: NF_IO[6] */ 126 5 1 /* MPP[5]: NF_IO[7] */ 127 6 1 /* MPP[6]: SYSRST_OUTn */ 128 8 2 /* MPP[8]: UA0_RTS */ 129 9 2 /* MPP[9]: UA0_CTS */ 130 10 3 /* MPP[10]: UA0_TXD */ 131 11 3 /* MPP[11]: UA0_RXD */ 132 12 1 /* MPP[12]: SD_CLK */ 133 13 1 /* MPP[13]: SD_CMD */ 134 14 1 /* MPP[14]: SD_D[0] */ 135 15 1 /* MPP[15]: SD_D[1] */ 136 16 1 /* MPP[16]: SD_D[2] */ 137 17 1 /* MPP[17]: SD_D[3] */ 138 18 1 /* MPP[18]: NF_IO[0] */ 139 19 1 /* MPP[19]: NF_IO[1] */ 140 29 1 >; /* MPP[29]: TSMP[9] */ 141 }; 142 143 GPIO: gpio@10100 { 144 #gpio-cells = <3>; 145 compatible = "mrvl,gpio"; 146 reg = <0x10100 0x20>; 147 gpio-controller; 148 interrupts = <35 36 37 38 39 40 41>; 149 interrupt-parent = <&PIC>; 150 }; 151 152 rtc@10300 { 153 compatible = "mrvl,rtc"; 154 reg = <0x10300 0x08>; 155 }; 156 157 twsi@11000 { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 compatible = "mrvl,twsi"; 161 reg = <0x11000 0x20>; 162 interrupts = <43>; 163 interrupt-parent = <&PIC>; 164 }; 165 166 enet0: ethernet@72000 { 167 #address-cells = <1>; 168 #size-cells = <1>; 169 model = "V2"; 170 compatible = "mrvl,ge"; 171 reg = <0x72000 0x2000>; 172 ranges = <0x0 0x72000 0x2000>; 173 local-mac-address = [ 00 00 00 00 00 00 ]; 174 interrupts = <12 13 14 11 46>; 175 interrupt-parent = <&PIC>; 176 phy-handle = <&phy0>; 177 178 mdio@0 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 compatible = "mrvl,mdio"; 182 183 phy0: ethernet-phy@0 { 184 reg = <0x0>; 185 }; 186 }; 187 }; 188 189 serial0: serial@12000 { 190 compatible = "ns16550"; 191 reg = <0x12000 0x20>; 192 reg-shift = <2>; 193 clock-frequency = <0>; 194 interrupts = <33>; 195 interrupt-parent = <&PIC>; 196 }; 197 198 serial1: serial@12100 { 199 compatible = "ns16550"; 200 reg = <0x12100 0x20>; 201 reg-shift = <2>; 202 clock-frequency = <0>; 203 interrupts = <34>; 204 interrupt-parent = <&PIC>; 205 }; 206 207 crypto@30000 { 208 compatible = "mrvl,cesa"; 209 reg = <0x30000 0x10000>; 210 interrupts = <22>; 211 interrupt-parent = <&PIC>; 212 213 sram-handle = <&SRAM>; 214 }; 215 216 usb@50000 { 217 compatible = "mrvl,usb-ehci", "usb-ehci"; 218 reg = <0x50000 0x1000>; 219 interrupts = <48 19>; 220 interrupt-parent = <&PIC>; 221 }; 222 223 xor@60000 { 224 compatible = "mrvl,xor"; 225 reg = <0x60000 0x1000>; 226 interrupts = <5 6 7 8>; 227 interrupt-parent = <&PIC>; 228 }; 229 }; 230 231 SRAM: sram@fd000000 { 232 compatible = "mrvl,cesa-sram"; 233 reg = <0xfd000000 0x00100000>; 234 }; 235 236 chosen { 237 stdin = "serial0"; 238 stdout = "serial0"; 239 }; 240}; 241