beaglebone.dts revision 245673
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/sys/boot/fdt/dts/beaglebone.dts 245673 2013-01-19 17:22:12Z kientzle $ 27 */ 28 29/dts-v1/; 30 31/ { 32 model = "beaglebone"; 33 compatible = "beaglebone", "ti,am335x"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 37 interrupt-parent = <&AINTC>; 38 39 aliases { 40 soc = &SOC; 41 uart0 = &uart0; 42 }; 43 44 memory { 45 device_type = "memory"; 46 reg = < 0x80000000 0x10000000 >; /* 256MB RAM */ 47 }; 48 49 SOC: am335x { 50 #address-cells = <1>; 51 #size-cells = <1>; 52 compatible = "simple-bus"; 53 ranges; 54 bus-frequency = <0>; 55 56 AINTC: interrupt-controller@48200000 { 57 compatible = "ti,aintc"; 58 interrupt-controller; 59 #address-cells = <0>; 60 #interrupt-cells = <1>; 61 reg = < 0x48200000 0x1000 >; 62 }; 63 64 scm@44e10000 { 65 compatible = "ti,scm"; 66 reg = < 0x44e10000 0x2000 >; 67 /* Set of triplets < padname, muxname, padstate> */ 68 scm-pad-config = 69 /* I2C0 */ 70 "I2C0_SDA", "I2C0_SDA","i2c", 71 "I2C0_SCL", "I2C0_SCL","i2c", 72 /* Ethernet */ 73 "MII1_RX_ER", "gmii1_rxerr", "input_pulldown", 74 "MII1_TX_EN", "gmii1_txen", "output", 75 "MII1_RX_DV", "gmii1_rxdv", "input_pulldown", 76 "MII1_TXD3", "gmii1_txd3", "output", 77 "MII1_TXD2", "gmii1_txd2", "output", 78 "MII1_TXD1", "gmii1_txd1", "output", 79 "MII1_TXD0", "gmii1_txd0", "output", 80 "MII1_TX_CLK", "gmii1_txclk", "input_pulldown", 81 "MII1_RX_CLK", "gmii1_rxclk", "input_pulldown", 82 "MII1_RXD3", "gmii1_rxd3", "input_pulldown", 83 "MII1_RXD2", "gmii1_rxd2", "input_pulldown", 84 "MII1_RXD1", "gmii1_rxd1", "input_pulldown", 85 "MII1_RXD0", "gmii1_rxd0", "input_pulldown", 86 "MDIO", "mdio_data", "input_pullup", 87 "MDC", "mdio_clk", "output_pullup", 88 /* MMCSD0 */ 89 "MMC0_CMD", "mmc0_cmd", "input_pullup", 90 "MMC0_CLK", "mmc0_clk", "input_pullup", 91 "MMC0_DAT0", "mmc0_dat0", "input_pullup", 92 "MMC0_DAT1", "mmc0_dat1", "input_pullup", 93 "MMC0_DAT2", "mmc0_dat2", "input_pullup", 94 "MMC0_DAT3", "mmc0_dat3", "input_pullup"; 95 }; 96 97 prcm@44E00000 { 98 compatible = "am335x,prcm"; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 reg = < 0x44E00000 0x1300 >; 102 }; 103 104 dmtimers@44E05000 { 105 compatible = "ti,am335x-dmtimer"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 reg = < 0x44E05000 0x1000 109 0x44E31000 0x1000 110 0x48040000 0x1000 111 0x48042000 0x1000 112 0x48044000 0x1000 113 0x48046000 0x1000 114 0x48048000 0x1000 115 0x4804A000 0x1000 >; 116 interrupts = < 66 67 68 69 92 93 94 95 >; 117 interrupt-parent = <&AINTC>; 118 }; 119 120 GPIO: gpio { 121 #gpio-cells = <3>; 122 compatible = "ti,gpio"; 123 gpio-controller; 124 reg =< 0x44E07000 0x1000 125 0x4804C000 0x1000 126 0x481AC000 0x1000 127 0x481AE000 0x1000 >; 128 interrupts = < 96 97 98 99 32 33 62 63 >; 129 interrupt-parent = <&AINTC>; 130 }; 131 132 133 uart0: serial@44E09000 { 134 compatible = "ns16550"; 135 reg = <0x44E09000 0x1000>; 136 reg-shift = <2>; 137 interrupts = < 72 >; 138 interrupt-parent = <&AINTC>; 139 clock-frequency = < 48000000 >; /* FIXME */ 140 }; 141 142 edma3@49000000 { 143 compatible = "ti,edma3"; 144 reg =< 0x49000000 0x100000 /* Channel Controller Regs */ 145 0x49800000 0x100000 /* Transfer Controller 0 Regs */ 146 0x49900000 0x100000 /* Transfer Controller 1 Regs */ 147 0x49a00000 0x100000 >; /* Transfer Controller 2 Regs */ 148 interrupts = <12 13 14>; 149 interrupt-parent = <&AINTC>; 150 }; 151 152 mmchs0@4809C000 { 153 compatible = "ti,mmchs"; 154 reg =<0x48060000 0x1000 >; 155 interrupts = <64>; 156 interrupt-parent = <&AINTC>; 157 mmchs-device-id = <0>; 158 }; 159 160 enet0: ethernet@4A100000 { 161 #address-cells = <1>; 162 #size-cells = <1>; 163 compatible = "ti,cpsw"; 164 reg = <0x4A100000 0x3000>; 165 interrupts = <40 41 42 43>; 166 interrupt-parent = <&AINTC>; 167 phy-handle = <&phy0>; 168 mdio@0 { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 compatible = "ti,cpsw-mdio"; 172 phy0: ethernet-phy@0 { 173 reg = <0x0>; 174 }; 175 }; 176 }; 177 178 i2c0: i2c@44e0b000 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 compatible = "ti,i2c"; 182 reg =< 0x44e0b000 0x1000 >; 183 interrupts = <70>; 184 interrupt-parent = <&AINTC>; 185 i2c-device-id = <0>; 186 pmic@24 { 187 compatible = "ti,am335x-pmic"; 188 reg = <0x24>; 189 }; 190 }; 191 }; 192 193 chosen { 194 stdin = "uart0"; 195 stdout = "uart0"; 196 }; 197}; 198