armreg.h revision 305530
1/*-
2 * Copyright (c) 2013, 2014 Andrew Turner
3 * Copyright (c) 2015 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * This software was developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: stable/11/sys/arm64/include/armreg.h 305530 2016-09-07 12:28:30Z andrew $
31 */
32
33#ifndef _MACHINE_ARMREG_H_
34#define	_MACHINE_ARMREG_H_
35
36#define	INSN_SIZE		4
37
38#define	READ_SPECIALREG(reg)						\
39({	uint64_t val;							\
40	__asm __volatile("mrs	%0, " __STRING(reg) : "=&r" (val));	\
41	val;								\
42})
43#define	WRITE_SPECIALREG(reg, val)					\
44	__asm __volatile("msr	" __STRING(reg) ", %0" : : "r"((uint64_t)val))
45
46/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
47#define	CNTHCTL_EVNTI_MASK	(0xf << 4) /* Bit to trigger event stream */
48#define	CNTHCTL_EVNTDIR		(1 << 3) /* Control transition trigger bit */
49#define	CNTHCTL_EVNTEN		(1 << 2) /* Enable event stream */
50#define	CNTHCTL_EL1PCEN		(1 << 1) /* Allow EL0/1 physical timer access */
51#define	CNTHCTL_EL1PCTEN	(1 << 0) /*Allow EL0/1 physical counter access*/
52
53/* CPACR_EL1 */
54#define	CPACR_FPEN_MASK		(0x3 << 20)
55#define	 CPACR_FPEN_TRAP_ALL1	(0x0 << 20) /* Traps from EL0 and EL1 */
56#define	 CPACR_FPEN_TRAP_EL0	(0x1 << 20) /* Traps from EL0 */
57#define	 CPACR_FPEN_TRAP_ALL2	(0x2 << 20) /* Traps from EL0 and EL1 */
58#define	 CPACR_FPEN_TRAP_NONE	(0x3 << 20) /* No traps */
59#define	CPACR_TTA		(0x1 << 28)
60
61/* CTR_EL0 - Cache Type Register */
62#define	CTR_DLINE_SHIFT		16
63#define	CTR_DLINE_MASK		(0xf << CTR_DLINE_SHIFT)
64#define	CTR_DLINE_SIZE(reg)	(((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
65#define	CTR_ILINE_SHIFT		0
66#define	CTR_ILINE_MASK		(0xf << CTR_ILINE_SHIFT)
67#define	CTR_ILINE_SIZE(reg)	(((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
68
69/* DCZID_EL0 - Data Cache Zero ID register */
70#define DCZID_DZP		(1 << 4) /* DC ZVA prohibited if non-0 */
71#define DCZID_BS_SHIFT		0
72#define DCZID_BS_MASK		(0xf << DCZID_BS_SHIFT)
73#define	DCZID_BS_SIZE(reg)	(((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
74
75/* ESR_ELx */
76#define	ESR_ELx_ISS_MASK	0x00ffffff
77#define	 ISS_INSN_FnV		(0x01 << 10)
78#define	 ISS_INSN_EA		(0x01 << 9)
79#define	 ISS_INSN_S1PTW		(0x01 << 7)
80#define	 ISS_INSN_IFSC_MASK	(0x1f << 0)
81#define	 ISS_DATA_ISV		(0x01 << 24)
82#define	 ISS_DATA_SAS_MASK	(0x03 << 22)
83#define	 ISS_DATA_SSE		(0x01 << 21)
84#define	 ISS_DATA_SRT_MASK	(0x1f << 16)
85#define	 ISS_DATA_SF		(0x01 << 15)
86#define	 ISS_DATA_AR		(0x01 << 14)
87#define	 ISS_DATA_FnV		(0x01 << 10)
88#define	 ISS_DATa_EA		(0x01 << 9)
89#define	 ISS_DATa_CM		(0x01 << 8)
90#define	 ISS_INSN_S1PTW		(0x01 << 7)
91#define	 ISS_DATa_WnR		(0x01 << 6)
92#define	 ISS_DATA_DFSC_MASK	(0x1f << 0)
93#define	ESR_ELx_IL		(0x01 << 25)
94#define	ESR_ELx_EC_SHIFT	26
95#define	ESR_ELx_EC_MASK		(0x3f << 26)
96#define	ESR_ELx_EXCEPTION(esr)	(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
97#define	 EXCP_UNKNOWN		0x00	/* Unkwn exception */
98#define	 EXCP_FP_SIMD		0x07	/* VFP/SIMD trap */
99#define	 EXCP_ILL_STATE		0x0e	/* Illegal execution state */
100#define	 EXCP_SVC		0x15	/* SVC trap */
101#define	 EXCP_MSR		0x18	/* MSR/MRS trap */
102#define	 EXCP_INSN_ABORT_L	0x20	/* Instruction abort, from lower EL */
103#define	 EXCP_INSN_ABORT	0x21	/* Instruction abort, from same EL */
104#define	 EXCP_PC_ALIGN		0x22	/* PC alignment fault */
105#define	 EXCP_DATA_ABORT_L	0x24	/* Data abort, from lower EL */
106#define	 EXCP_DATA_ABORT	0x25	/* Data abort, from same EL */
107#define	 EXCP_SP_ALIGN		0x26	/* SP slignment fault */
108#define	 EXCP_TRAP_FP		0x2c	/* Trapped FP exception */
109#define	 EXCP_SERROR		0x2f	/* SError interrupt */
110#define	 EXCP_SOFTSTP_EL0	0x32	/* Software Step, from lower EL */
111#define	 EXCP_SOFTSTP_EL1	0x33	/* Software Step, from same EL */
112#define	 EXCP_WATCHPT_EL1	0x35	/* Watchpoint, from same EL */
113#define	 EXCP_BRK		0x3c	/* Breakpoint */
114
115/* ICC_CTLR_EL1 */
116#define	ICC_CTLR_EL1_EOIMODE	(1U << 1)
117
118/* ICC_IAR1_EL1 */
119#define	ICC_IAR1_EL1_SPUR	(0x03ff)
120
121/* ICC_IGRPEN0_EL1 */
122#define	ICC_IGRPEN0_EL1_EN	(1U << 0)
123
124/* ICC_PMR_EL1 */
125#define	ICC_PMR_EL1_PRIO_MASK	(0xFFUL)
126
127/* ICC_SGI1R_EL1 */
128#define	ICC_SGI1R_EL1_TL_MASK		0xffffUL
129#define	ICC_SGI1R_EL1_AFF1_SHIFT	16
130#define	ICC_SGI1R_EL1_SGIID_SHIFT	24
131#define	ICC_SGI1R_EL1_AFF2_SHIFT	32
132#define	ICC_SGI1R_EL1_AFF3_SHIFT	48
133#define	ICC_SGI1R_EL1_SGIID_MASK	0xfUL
134#define	ICC_SGI1R_EL1_IRM		(0x1UL << 40)
135
136/* ICC_SRE_EL1 */
137#define	ICC_SRE_EL1_SRE		(1U << 0)
138
139/* ICC_SRE_EL2 */
140#define	ICC_SRE_EL2_SRE		(1U << 0)
141#define	ICC_SRE_EL2_EN		(1U << 3)
142
143/* ID_AA64DFR0_EL1 */
144#define	ID_AA64DFR0_MASK		0xf0f0ffff
145#define	ID_AA64DFR0_DEBUG_VER_SHIFT	0
146#define	ID_AA64DFR0_DEBUG_VER_MASK	(0xf << ID_AA64DFR0_DEBUG_VER_SHIFT)
147#define	ID_AA64DFR0_DEBUG_VER(x)	((x) & ID_AA64DFR0_DEBUG_VER_MASK)
148#define	 ID_AA64DFR0_DEBUG_VER_8	(0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT)
149#define	 ID_AA64DFR0_DEBUG_VER_8_VHE	(0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT)
150#define	ID_AA64DFR0_TRACE_VER_SHIFT	4
151#define	ID_AA64DFR0_TRACE_VER_MASK	(0xf << ID_AA64DFR0_TRACE_VER_SHIFT)
152#define	ID_AA64DFR0_TRACE_VER(x)	((x) & ID_AA64DFR0_TRACE_VER_MASK)
153#define	 ID_AA64DFR0_TRACE_VER_NONE	(0x0 << ID_AA64DFR0_TRACE_VER_SHIFT)
154#define	 ID_AA64DFR0_TRACE_VER_IMPL	(0x1 << ID_AA64DFR0_TRACE_VER_SHIFT)
155#define	ID_AA64DFR0_PMU_VER_SHIFT	8
156#define	ID_AA64DFR0_PMU_VER_MASK	(0xf << ID_AA64DFR0_PMU_VER_SHIFT)
157#define	ID_AA64DFR0_PMU_VER(x)		((x) & ID_AA64DFR0_PMU_VER_MASK)
158#define	 ID_AA64DFR0_PMU_VER_NONE	(0x0 << ID_AA64DFR0_PMU_VER_SHIFT)
159#define	 ID_AA64DFR0_PMU_VER_3		(0x1 << ID_AA64DFR0_PMU_VER_SHIFT)
160#define	 ID_AA64DFR0_PMU_VER_3_1	(0x4 << ID_AA64DFR0_PMU_VER_SHIFT)
161#define	 ID_AA64DFR0_PMU_VER_IMPL	(0xf << ID_AA64DFR0_PMU_VER_SHIFT)
162#define	ID_AA64DFR0_BRPS_SHIFT		12
163#define	ID_AA64DFR0_BRPS_MASK		(0xf << ID_AA64DFR0_BRPS_SHIFT)
164#define	ID_AA64DFR0_BRPS(x)		\
165    ((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1)
166#define	ID_AA64DFR0_WRPS_SHIFT		20
167#define	ID_AA64DFR0_WRPS_MASK		(0xf << ID_AA64DFR0_WRPS_SHIFT)
168#define	ID_AA64DFR0_WRPS(x)		\
169    ((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1)
170#define	ID_AA64DFR0_CTX_CMPS_SHIFT	28
171#define	ID_AA64DFR0_CTX_CMPS_MASK	(0xf << ID_AA64DFR0_CTX_CMPS_SHIFT)
172#define	ID_AA64DFR0_CTX_CMPS(x)		\
173    ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
174
175/* ID_AA64ISAR0_EL1 */
176#define	ID_AA64ISAR0_MASK		0xf0fffff0
177#define	ID_AA64ISAR0_AES_SHIFT		4
178#define	ID_AA64ISAR0_AES_MASK		(0xf << ID_AA64ISAR0_AES_SHIFT)
179#define	ID_AA64ISAR0_AES(x)		((x) & ID_AA64ISAR0_AES_MASK)
180#define	 ID_AA64ISAR0_AES_NONE		(0x0 << ID_AA64ISAR0_AES_SHIFT)
181#define	 ID_AA64ISAR0_AES_BASE		(0x1 << ID_AA64ISAR0_AES_SHIFT)
182#define	 ID_AA64ISAR0_AES_PMULL		(0x2 << ID_AA64ISAR0_AES_SHIFT)
183#define	ID_AA64ISAR0_SHA1_SHIFT		8
184#define	ID_AA64ISAR0_SHA1_MASK		(0xf << ID_AA64ISAR0_SHA1_SHIFT)
185#define	ID_AA64ISAR0_SHA1(x)		((x) & ID_AA64ISAR0_SHA1_MASK)
186#define	 ID_AA64ISAR0_SHA1_NONE		(0x0 << ID_AA64ISAR0_SHA1_SHIFT)
187#define	 ID_AA64ISAR0_SHA1_BASE		(0x1 << ID_AA64ISAR0_SHA1_SHIFT)
188#define	ID_AA64ISAR0_SHA2_SHIFT		12
189#define	ID_AA64ISAR0_SHA2_MASK		(0xf << ID_AA64ISAR0_SHA2_SHIFT)
190#define	ID_AA64ISAR0_SHA2(x)		((x) & ID_AA64ISAR0_SHA2_MASK)
191#define	 ID_AA64ISAR0_SHA2_NONE		(0x0 << ID_AA64ISAR0_SHA2_SHIFT)
192#define	 ID_AA64ISAR0_SHA2_BASE		(0x1 << ID_AA64ISAR0_SHA2_SHIFT)
193#define	ID_AA64ISAR0_CRC32_SHIFT	16
194#define	ID_AA64ISAR0_CRC32_MASK		(0xf << ID_AA64ISAR0_CRC32_SHIFT)
195#define	ID_AA64ISAR0_CRC32(x)		((x) & ID_AA64ISAR0_CRC32_MASK)
196#define	 ID_AA64ISAR0_CRC32_NONE	(0x0 << ID_AA64ISAR0_CRC32_SHIFT)
197#define	 ID_AA64ISAR0_CRC32_BASE	(0x1 << ID_AA64ISAR0_CRC32_SHIFT)
198#define	ID_AA64ISAR0_ATOMIC_SHIFT	20
199#define	ID_AA64ISAR0_ATOMIC_MASK	(0xf << ID_AA64ISAR0_ATOMIC_SHIFT)
200#define	ID_AA64ISAR0_ATOMIC(x)		((x) & ID_AA64ISAR0_ATOMIC_MASK)
201#define	 ID_AA64ISAR0_ATOMIC_NONE	(0x0 << ID_AA64ISAR0_ATOMIC_SHIFT)
202#define	 ID_AA64ISAR0_ATOMIC_IMPL	(0x2 << ID_AA64ISAR0_ATOMIC_SHIFT)
203#define	ID_AA64ISAR0_RDM_SHIFT		28
204#define	ID_AA64ISAR0_RDM_MASK		(0xf << ID_AA64ISAR0_RDM_SHIFT)
205#define	ID_AA64ISAR0_RDM(x)		((x) & ID_AA64ISAR0_RDM_MASK)
206#define	 ID_AA64ISAR0_RDM_NONE		(0x0 << ID_AA64ISAR0_RDM_SHIFT)
207#define	 ID_AA64ISAR0_RDM_IMPL		(0x1 << ID_AA64ISAR0_RDM_SHIFT)
208
209/* ID_AA64MMFR0_EL1 */
210#define	ID_AA64MMFR0_MASK		0xffffffff
211#define	ID_AA64MMFR0_PA_RANGE_SHIFT	0
212#define	ID_AA64MMFR0_PA_RANGE_MASK	(0xf << ID_AA64MMFR0_PA_RANGE_SHIFT)
213#define	ID_AA64MMFR0_PA_RANGE(x)	((x) & ID_AA64MMFR0_PA_RANGE_MASK)
214#define	 ID_AA64MMFR0_PA_RANGE_4G	(0x0 << ID_AA64MMFR0_PA_RANGE_SHIFT)
215#define	 ID_AA64MMFR0_PA_RANGE_64G	(0x1 << ID_AA64MMFR0_PA_RANGE_SHIFT)
216#define	 ID_AA64MMFR0_PA_RANGE_1T	(0x2 << ID_AA64MMFR0_PA_RANGE_SHIFT)
217#define	 ID_AA64MMFR0_PA_RANGE_4T	(0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT)
218#define	 ID_AA64MMFR0_PA_RANGE_16T	(0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT)
219#define	 ID_AA64MMFR0_PA_RANGE_256T	(0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT)
220#define	ID_AA64MMFR0_ASID_BITS_SHIFT	4
221#define	ID_AA64MMFR0_ASID_BITS_MASK	(0xf << ID_AA64MMFR0_ASID_BITS_SHIFT)
222#define	ID_AA64MMFR0_ASID_BITS(x)	((x) & ID_AA64MMFR0_ASID_BITS_MASK)
223#define	 ID_AA64MMFR0_ASID_BITS_8	(0x0 << ID_AA64MMFR0_ASID_BITS_SHIFT)
224#define	 ID_AA64MMFR0_ASID_BITS_16	(0x2 << ID_AA64MMFR0_ASID_BITS_SHIFT)
225#define	ID_AA64MMFR0_BIGEND_SHIFT	8
226#define	ID_AA64MMFR0_BIGEND_MASK	(0xf << ID_AA64MMFR0_BIGEND_SHIFT)
227#define	ID_AA64MMFR0_BIGEND(x)		((x) & ID_AA64MMFR0_BIGEND_MASK)
228#define	 ID_AA64MMFR0_BIGEND_FIXED	(0x0 << ID_AA64MMFR0_BIGEND_SHIFT)
229#define	 ID_AA64MMFR0_BIGEND_MIXED	(0x1 << ID_AA64MMFR0_BIGEND_SHIFT)
230#define	ID_AA64MMFR0_S_NS_MEM_SHIFT	12
231#define	ID_AA64MMFR0_S_NS_MEM_MASK	(0xf << ID_AA64MMFR0_S_NS_MEM_SHIFT)
232#define	ID_AA64MMFR0_S_NS_MEM(x)	((x) & ID_AA64MMFR0_S_NS_MEM_MASK)
233#define	 ID_AA64MMFR0_S_NS_MEM_NONE	(0x0 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
234#define	 ID_AA64MMFR0_S_NS_MEM_DISTINCT	(0x1 << ID_AA64MMFR0_S_NS_MEM_SHIFT)
235#define	ID_AA64MMFR0_BIGEND_EL0_SHIFT	16
236#define	ID_AA64MMFR0_BIGEND_EL0_MASK	(0xf << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
237#define	ID_AA64MMFR0_BIGEND_EL0(x)	((x) & ID_AA64MMFR0_BIGEND_EL0_MASK)
238#define	 ID_AA64MMFR0_BIGEND_EL0_FIXED	(0x0 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
239#define	 ID_AA64MMFR0_BIGEND_EL0_MIXED	(0x1 << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
240#define	ID_AA64MMFR0_TGRAN16_SHIFT	20
241#define	ID_AA64MMFR0_TGRAN16_MASK	(0xf << ID_AA64MMFR0_TGRAN16_SHIFT)
242#define	ID_AA64MMFR0_TGRAN16(x)		((x) & ID_AA64MMFR0_TGRAN16_MASK)
243#define	 ID_AA64MMFR0_TGRAN16_NONE	(0x0 << ID_AA64MMFR0_TGRAN16_SHIFT)
244#define	 ID_AA64MMFR0_TGRAN16_IMPL	(0x1 << ID_AA64MMFR0_TGRAN16_SHIFT)
245#define	ID_AA64MMFR0_TGRAN64_SHIFT	24
246#define	ID_AA64MMFR0_TGRAN64_MASK	(0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
247#define	ID_AA64MMFR0_TGRAN64(x)		((x) & ID_AA64MMFR0_TGRAN64_MASK)
248#define	 ID_AA64MMFR0_TGRAN64_IMPL	(0x0 << ID_AA64MMFR0_TGRAN64_SHIFT)
249#define	 ID_AA64MMFR0_TGRAN64_NONE	(0xf << ID_AA64MMFR0_TGRAN64_SHIFT)
250#define	ID_AA64MMFR0_TGRAN4_SHIFT	28
251#define	ID_AA64MMFR0_TGRAN4_MASK	(0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
252#define	ID_AA64MMFR0_TGRAN4(x)		((x) & ID_AA64MMFR0_TGRAN4_MASK)
253#define	 ID_AA64MMFR0_TGRAN4_IMPL	(0x0 << ID_AA64MMFR0_TGRAN4_SHIFT)
254#define	 ID_AA64MMFR0_TGRAN4_NONE	(0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
255
256/* ID_AA64MMFR1_EL1 */
257#define	ID_AA64MMFR1_MASK		0x00ffffff
258#define	ID_AA64MMFR1_HAFDBS_SHIFT	0
259#define	ID_AA64MMFR1_HAFDBS_MASK	(0xf << ID_AA64MMFR1_HAFDBS_SHIFT)
260#define	ID_AA64MMFR1_HAFDBS(x)		((x) & ID_AA64MMFR1_HAFDBS_MASK)
261#define	 ID_AA64MMFR1_HAFDBS_NONE	(0x0 << ID_AA64MMFR1_HAFDBS_SHIFT)
262#define	 ID_AA64MMFR1_HAFDBS_AF		(0x1 << ID_AA64MMFR1_HAFDBS_SHIFT)
263#define	 ID_AA64MMFR1_HAFDBS_AF_DBS	(0x2 << ID_AA64MMFR1_HAFDBS_SHIFT)
264#define	ID_AA64MMFR1_VMIDBITS_SHIFT	4
265#define	ID_AA64MMFR1_VMIDBITS_MASK	(0xf << ID_AA64MMFR1_VMIDBITS_SHIFT)
266#define	ID_AA64MMFR1_VMIDBITS(x)	((x) & ID_AA64MMFR1_VMIDBITS_MASK)
267#define	 ID_AA64MMFR1_VMIDBITS_8	(0x0 << ID_AA64MMFR1_VMIDBITS_SHIFT)
268#define	 ID_AA64MMFR1_VMIDBITS_16	(0x2 << ID_AA64MMFR1_VMIDBITS_SHIFT)
269#define	ID_AA64MMFR1_VH_SHIFT		8
270#define	ID_AA64MMFR1_VH_MASK		(0xf << ID_AA64MMFR1_VH_SHIFT)
271#define	ID_AA64MMFR1_VH(x)		((x) & ID_AA64MMFR1_VH_MASK)
272#define	 ID_AA64MMFR1_VH_NONE		(0x0 << ID_AA64MMFR1_VH_SHIFT)
273#define	 ID_AA64MMFR1_VH_IMPL		(0x1 << ID_AA64MMFR1_VH_SHIFT)
274#define	ID_AA64MMFR1_HPDS_SHIFT		12
275#define	ID_AA64MMFR1_HPDS_MASK		(0xf << ID_AA64MMFR1_HPDS_SHIFT)
276#define	ID_AA64MMFR1_HPDS(x)		((x) & ID_AA64MMFR1_HPDS_MASK)
277#define	 ID_AA64MMFR1_HPDS_NONE		(0x0 << ID_AA64MMFR1_HPDS_SHIFT)
278#define	 ID_AA64MMFR1_HPDS_IMPL		(0x1 << ID_AA64MMFR1_HPDS_SHIFT)
279#define	ID_AA64MMFR1_LO_SHIFT		16
280#define	ID_AA64MMFR1_LO_MASK		(0xf << ID_AA64MMFR1_LO_SHIFT)
281#define	ID_AA64MMFR1_LO(x)		((x) & ID_AA64MMFR1_LO_MASK)
282#define	 ID_AA64MMFR1_LO_NONE		(0x0 << ID_AA64MMFR1_LO_SHIFT)
283#define	 ID_AA64MMFR1_LO_IMPL		(0x1 << ID_AA64MMFR1_LO_SHIFT)
284#define	ID_AA64MMFR1_PAN_SHIFT		20
285#define	ID_AA64MMFR1_PAN_MASK		(0xf << ID_AA64MMFR1_PAN_SHIFT)
286#define	ID_AA64MMFR1_PAN(x)		((x) & ID_AA64MMFR1_PAN_MASK)
287#define	 ID_AA64MMFR1_PAN_NONE		(0x0 << ID_AA64MMFR1_PAN_SHIFT)
288#define	 ID_AA64MMFR1_PAN_IMPL		(0x1 << ID_AA64MMFR1_PAN_SHIFT)
289
290/* ID_AA64PFR0_EL1 */
291#define	ID_AA64PFR0_MASK		0x0fffffff
292#define	ID_AA64PFR0_EL0_SHIFT		0
293#define	ID_AA64PFR0_EL0_MASK		(0xf << ID_AA64PFR0_EL0_SHIFT)
294#define	ID_AA64PFR0_EL0(x)		((x) & ID_AA64PFR0_EL0_MASK)
295#define	 ID_AA64PFR0_EL0_64		(1 << ID_AA64PFR0_EL0_SHIFT)
296#define	 ID_AA64PFR0_EL0_64_32		(2 << ID_AA64PFR0_EL0_SHIFT)
297#define	ID_AA64PFR0_EL1_SHIFT		4
298#define	ID_AA64PFR0_EL1_MASK		(0xf << ID_AA64PFR0_EL1_SHIFT)
299#define	ID_AA64PFR0_EL1(x)		((x) & ID_AA64PFR0_EL1_MASK)
300#define	 ID_AA64PFR0_EL1_64		(1 << ID_AA64PFR0_EL1_SHIFT)
301#define	 ID_AA64PFR0_EL1_64_32		(2 << ID_AA64PFR0_EL1_SHIFT)
302#define	ID_AA64PFR0_EL2_SHIFT		8
303#define	ID_AA64PFR0_EL2_MASK		(0xf << ID_AA64PFR0_EL2_SHIFT)
304#define	ID_AA64PFR0_EL2(x)		((x) & ID_AA64PFR0_EL2_MASK)
305#define	 ID_AA64PFR0_EL2_NONE		(0 << ID_AA64PFR0_EL2_SHIFT)
306#define	 ID_AA64PFR0_EL2_64		(1 << ID_AA64PFR0_EL2_SHIFT)
307#define	 ID_AA64PFR0_EL2_64_32		(2 << ID_AA64PFR0_EL2_SHIFT)
308#define	ID_AA64PFR0_EL3_SHIFT		12
309#define	ID_AA64PFR0_EL3_MASK		(0xf << ID_AA64PFR0_EL3_SHIFT)
310#define	ID_AA64PFR0_EL3(x)		((x) & ID_AA64PFR0_EL3_MASK)
311#define	 ID_AA64PFR0_EL3_NONE		(0 << ID_AA64PFR0_EL3_SHIFT)
312#define	 ID_AA64PFR0_EL3_64		(1 << ID_AA64PFR0_EL3_SHIFT)
313#define	 ID_AA64PFR0_EL3_64_32		(2 << ID_AA64PFR0_EL3_SHIFT)
314#define	ID_AA64PFR0_FP_SHIFT		16
315#define	ID_AA64PFR0_FP_MASK		(0xf << ID_AA64PFR0_FP_SHIFT)
316#define	ID_AA64PFR0_FP(x)		((x) & ID_AA64PFR0_FP_MASK)
317#define	 ID_AA64PFR0_FP_IMPL		(0x0 << ID_AA64PFR0_FP_SHIFT)
318#define	 ID_AA64PFR0_FP_NONE		(0xf << ID_AA64PFR0_FP_SHIFT)
319#define	ID_AA64PFR0_ADV_SIMD_SHIFT	20
320#define	ID_AA64PFR0_ADV_SIMD_MASK	(0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
321#define	ID_AA64PFR0_ADV_SIMD(x)		((x) & ID_AA64PFR0_ADV_SIMD_MASK)
322#define	 ID_AA64PFR0_ADV_SIMD_IMPL	(0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT)
323#define	 ID_AA64PFR0_ADV_SIMD_NONE	(0xf << ID_AA64PFR0_ADV_SIMD_SHIFT)
324#define	ID_AA64PFR0_GIC_BITS		0x4 /* Number of bits in GIC field */
325#define	ID_AA64PFR0_GIC_SHIFT		24
326#define	ID_AA64PFR0_GIC_MASK		(0xf << ID_AA64PFR0_GIC_SHIFT)
327#define	ID_AA64PFR0_GIC(x)		((x) & ID_AA64PFR0_GIC_MASK)
328#define	 ID_AA64PFR0_GIC_CPUIF_NONE	(0x0 << ID_AA64PFR0_GIC_SHIFT)
329#define	 ID_AA64PFR0_GIC_CPUIF_EN	(0x1 << ID_AA64PFR0_GIC_SHIFT)
330
331/* MAIR_EL1 - Memory Attribute Indirection Register */
332#define	MAIR_ATTR_MASK(idx)	(0xff << ((n)* 8))
333#define	MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
334
335/* SCTLR_EL1 - System Control Register */
336#define	SCTLR_RES0	0xc8222400	/* Reserved, write 0 */
337#define	SCTLR_RES1	0x30d00800	/* Reserved, write 1 */
338
339#define	SCTLR_M		0x00000001
340#define	SCTLR_A		0x00000002
341#define	SCTLR_C		0x00000004
342#define	SCTLR_SA	0x00000008
343#define	SCTLR_SA0	0x00000010
344#define	SCTLR_CP15BEN	0x00000020
345#define	SCTLR_THEE	0x00000040
346#define	SCTLR_ITD	0x00000080
347#define	SCTLR_SED	0x00000100
348#define	SCTLR_UMA	0x00000200
349#define	SCTLR_I		0x00001000
350#define	SCTLR_DZE	0x00004000
351#define	SCTLR_UCT	0x00008000
352#define	SCTLR_nTWI	0x00010000
353#define	SCTLR_nTWE	0x00040000
354#define	SCTLR_WXN	0x00080000
355#define	SCTLR_EOE	0x01000000
356#define	SCTLR_EE	0x02000000
357#define	SCTLR_UCI	0x04000000
358
359/* SPSR_EL1 */
360/*
361 * When the exception is taken in AArch64:
362 * M[4]   is 0 for AArch64 mode
363 * M[3:2] is the exception level
364 * M[1]   is unused
365 * M[0]   is the SP select:
366 *         0: always SP0
367 *         1: current ELs SP
368 */
369#define	PSR_M_EL0t	0x00000000
370#define	PSR_M_EL1t	0x00000004
371#define	PSR_M_EL1h	0x00000005
372#define	PSR_M_EL2t	0x00000008
373#define	PSR_M_EL2h	0x00000009
374#define	PSR_M_MASK	0x0000001f
375
376#define	PSR_F		0x00000040
377#define	PSR_I		0x00000080
378#define	PSR_A		0x00000100
379#define	PSR_D		0x00000200
380#define	PSR_IL		0x00100000
381#define	PSR_SS		0x00200000
382#define	PSR_V		0x10000000
383#define	PSR_C		0x20000000
384#define	PSR_Z		0x40000000
385#define	PSR_N		0x80000000
386
387/* TCR_EL1 - Translation Control Register */
388#define	TCR_ASID_16	(1 << 36)
389
390#define	TCR_IPS_SHIFT	32
391#define	TCR_IPS_32BIT	(0 << TCR_IPS_SHIFT)
392#define	TCR_IPS_36BIT	(1 << TCR_IPS_SHIFT)
393#define	TCR_IPS_40BIT	(2 << TCR_IPS_SHIFT)
394#define	TCR_IPS_42BIT	(3 << TCR_IPS_SHIFT)
395#define	TCR_IPS_44BIT	(4 << TCR_IPS_SHIFT)
396#define	TCR_IPS_48BIT	(5 << TCR_IPS_SHIFT)
397
398#define	TCR_TG1_SHIFT	30
399#define	TCR_TG1_16K	(1 << TCR_TG1_SHIFT)
400#define	TCR_TG1_4K	(2 << TCR_TG1_SHIFT)
401#define	TCR_TG1_64K	(3 << TCR_TG1_SHIFT)
402
403#define	TCR_SH1_SHIFT	28
404#define	TCR_SH1_IS	(0x3UL << TCR_SH1_SHIFT)
405#define	TCR_ORGN1_SHIFT	26
406#define	TCR_ORGN1_WBWA	(0x1UL << TCR_ORGN1_SHIFT)
407#define	TCR_IRGN1_SHIFT	24
408#define	TCR_IRGN1_WBWA	(0x1UL << TCR_IRGN1_SHIFT)
409#define	TCR_SH0_SHIFT	12
410#define	TCR_SH0_IS	(0x3UL << TCR_SH0_SHIFT)
411#define	TCR_ORGN0_SHIFT	10
412#define	TCR_ORGN0_WBWA	(0x1UL << TCR_ORGN0_SHIFT)
413#define	TCR_IRGN0_SHIFT	8
414#define	TCR_IRGN0_WBWA	(0x1UL << TCR_IRGN0_SHIFT)
415
416#define	TCR_CACHE_ATTRS	((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
417				(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
418
419#ifdef SMP
420#define	TCR_SMP_ATTRS	(TCR_SH0_IS | TCR_SH1_IS)
421#else
422#define	TCR_SMP_ATTRS	0
423#endif
424
425#define	TCR_T1SZ_SHIFT	16
426#define	TCR_T0SZ_SHIFT	0
427#define	TCR_T1SZ(x)	((x) << TCR_T1SZ_SHIFT)
428#define	TCR_T0SZ(x)	((x) << TCR_T0SZ_SHIFT)
429#define	TCR_TxSZ(x)	(TCR_T1SZ(x) | TCR_T0SZ(x))
430
431/* Saved Program Status Register */
432#define	DBG_SPSR_SS	(0x1 << 21)
433
434/* Monitor Debug System Control Register */
435#define	DBG_MDSCR_SS	(0x1 << 0)
436#define	DBG_MDSCR_KDE	(0x1 << 13)
437#define	DBG_MDSCR_MDE	(0x1 << 15)
438
439/* Perfomance Monitoring Counters */
440#define	PMCR_E		(1 << 0) /* Enable all counters */
441#define	PMCR_P		(1 << 1) /* Reset all counters */
442#define	PMCR_C		(1 << 2) /* Clock counter reset */
443#define	PMCR_D		(1 << 3) /* CNTR counts every 64 clk cycles */
444#define	PMCR_X		(1 << 4) /* Export to ext. monitoring (ETM) */
445#define	PMCR_DP		(1 << 5) /* Disable CCNT if non-invasive debug*/
446#define	PMCR_LC		(1 << 6) /* Long cycle count enable */
447#define	PMCR_IMP_SHIFT	24 /* Implementer code */
448#define	PMCR_IMP_MASK	(0xff << PMCR_IMP_SHIFT)
449#define	PMCR_IDCODE_SHIFT	16 /* Identification code */
450#define	PMCR_IDCODE_MASK	(0xff << PMCR_IDCODE_SHIFT)
451#define	 PMCR_IDCODE_CORTEX_A57	0x01
452#define	 PMCR_IDCODE_CORTEX_A72	0x02
453#define	 PMCR_IDCODE_CORTEX_A53	0x03
454#define	PMCR_N_SHIFT	11       /* Number of counters implemented */
455#define	PMCR_N_MASK	(0x1f << PMCR_N_SHIFT)
456
457#endif /* !_MACHINE_ARMREG_H_ */
458