pmap.c revision 319203
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2003 Peter Wemm 9 * All rights reserved. 10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 11 * All rights reserved. 12 * Copyright (c) 2014 Andrew Turner 13 * All rights reserved. 14 * Copyright (c) 2014-2016 The FreeBSD Foundation 15 * All rights reserved. 16 * 17 * This code is derived from software contributed to Berkeley by 18 * the Systems Programming Group of the University of Utah Computer 19 * Science Department and William Jolitz of UUNET Technologies Inc. 20 * 21 * This software was developed by Andrew Turner under sponsorship from 22 * the FreeBSD Foundation. 23 * 24 * Redistribution and use in source and binary forms, with or without 25 * modification, are permitted provided that the following conditions 26 * are met: 27 * 1. Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * 2. Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in the 31 * documentation and/or other materials provided with the distribution. 32 * 3. All advertising materials mentioning features or use of this software 33 * must display the following acknowledgement: 34 * This product includes software developed by the University of 35 * California, Berkeley and its contributors. 36 * 4. Neither the name of the University nor the names of its contributors 37 * may be used to endorse or promote products derived from this software 38 * without specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 43 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 * 52 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 53 */ 54/*- 55 * Copyright (c) 2003 Networks Associates Technology, Inc. 56 * All rights reserved. 57 * 58 * This software was developed for the FreeBSD Project by Jake Burkholder, 59 * Safeport Network Services, and Network Associates Laboratories, the 60 * Security Research Division of Network Associates, Inc. under 61 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 62 * CHATS research program. 63 * 64 * Redistribution and use in source and binary forms, with or without 65 * modification, are permitted provided that the following conditions 66 * are met: 67 * 1. Redistributions of source code must retain the above copyright 68 * notice, this list of conditions and the following disclaimer. 69 * 2. Redistributions in binary form must reproduce the above copyright 70 * notice, this list of conditions and the following disclaimer in the 71 * documentation and/or other materials provided with the distribution. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 83 * SUCH DAMAGE. 84 */ 85 86#include <sys/cdefs.h> 87__FBSDID("$FreeBSD: stable/11/sys/arm64/arm64/pmap.c 319203 2017-05-30 12:44:01Z andrew $"); 88 89/* 90 * Manages physical address maps. 91 * 92 * Since the information managed by this module is 93 * also stored by the logical address mapping module, 94 * this module may throw away valid virtual-to-physical 95 * mappings at almost any time. However, invalidations 96 * of virtual-to-physical mappings must be done as 97 * requested. 98 * 99 * In order to cope with hardware architectures which 100 * make virtual-to-physical map invalidates expensive, 101 * this module may delay invalidate or reduced protection 102 * operations until such time as they are actually 103 * necessary. This module is given full information as 104 * to which processors are currently using which maps, 105 * and to when physical maps must be made correct. 106 */ 107 108#include <sys/param.h> 109#include <sys/bitstring.h> 110#include <sys/bus.h> 111#include <sys/systm.h> 112#include <sys/kernel.h> 113#include <sys/ktr.h> 114#include <sys/lock.h> 115#include <sys/malloc.h> 116#include <sys/mman.h> 117#include <sys/msgbuf.h> 118#include <sys/mutex.h> 119#include <sys/proc.h> 120#include <sys/rwlock.h> 121#include <sys/sx.h> 122#include <sys/vmem.h> 123#include <sys/vmmeter.h> 124#include <sys/sched.h> 125#include <sys/sysctl.h> 126#include <sys/_unrhdr.h> 127#include <sys/smp.h> 128 129#include <vm/vm.h> 130#include <vm/vm_param.h> 131#include <vm/vm_kern.h> 132#include <vm/vm_page.h> 133#include <vm/vm_map.h> 134#include <vm/vm_object.h> 135#include <vm/vm_extern.h> 136#include <vm/vm_pageout.h> 137#include <vm/vm_pager.h> 138#include <vm/vm_phys.h> 139#include <vm/vm_radix.h> 140#include <vm/vm_reserv.h> 141#include <vm/uma.h> 142 143#include <machine/machdep.h> 144#include <machine/md_var.h> 145#include <machine/pcb.h> 146 147#define NL0PG (PAGE_SIZE/(sizeof (pd_entry_t))) 148#define NL1PG (PAGE_SIZE/(sizeof (pd_entry_t))) 149#define NL2PG (PAGE_SIZE/(sizeof (pd_entry_t))) 150#define NL3PG (PAGE_SIZE/(sizeof (pt_entry_t))) 151 152#define NUL0E L0_ENTRIES 153#define NUL1E (NUL0E * NL1PG) 154#define NUL2E (NUL1E * NL2PG) 155 156#if !defined(DIAGNOSTIC) 157#ifdef __GNUC_GNU_INLINE__ 158#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 159#else 160#define PMAP_INLINE extern inline 161#endif 162#else 163#define PMAP_INLINE 164#endif 165 166/* 167 * These are configured by the mair_el1 register. This is set up in locore.S 168 */ 169#define DEVICE_MEMORY 0 170#define UNCACHED_MEMORY 1 171#define CACHED_MEMORY 2 172 173 174#ifdef PV_STATS 175#define PV_STAT(x) do { x ; } while (0) 176#else 177#define PV_STAT(x) do { } while (0) 178#endif 179 180#define pmap_l2_pindex(v) ((v) >> L2_SHIFT) 181#define pa_to_pvh(pa) (&pv_table[pmap_l2_pindex(pa)]) 182 183#define NPV_LIST_LOCKS MAXCPU 184 185#define PHYS_TO_PV_LIST_LOCK(pa) \ 186 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS]) 187 188#define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \ 189 struct rwlock **_lockp = (lockp); \ 190 struct rwlock *_new_lock; \ 191 \ 192 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \ 193 if (_new_lock != *_lockp) { \ 194 if (*_lockp != NULL) \ 195 rw_wunlock(*_lockp); \ 196 *_lockp = _new_lock; \ 197 rw_wlock(*_lockp); \ 198 } \ 199} while (0) 200 201#define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \ 202 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m)) 203 204#define RELEASE_PV_LIST_LOCK(lockp) do { \ 205 struct rwlock **_lockp = (lockp); \ 206 \ 207 if (*_lockp != NULL) { \ 208 rw_wunlock(*_lockp); \ 209 *_lockp = NULL; \ 210 } \ 211} while (0) 212 213#define VM_PAGE_TO_PV_LIST_LOCK(m) \ 214 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m)) 215 216struct pmap kernel_pmap_store; 217 218vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 219vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 220vm_offset_t kernel_vm_end = 0; 221 222struct msgbuf *msgbufp = NULL; 223 224/* 225 * Data for the pv entry allocation mechanism. 226 * Updates to pv_invl_gen are protected by the pv_list_locks[] 227 * elements, but reads are not. 228 */ 229static struct md_page *pv_table; 230static struct md_page pv_dummy; 231 232vm_paddr_t dmap_phys_base; /* The start of the dmap region */ 233vm_paddr_t dmap_phys_max; /* The limit of the dmap region */ 234vm_offset_t dmap_max_addr; /* The virtual address limit of the dmap */ 235 236/* This code assumes all L1 DMAP entries will be used */ 237CTASSERT((DMAP_MIN_ADDRESS & ~L0_OFFSET) == DMAP_MIN_ADDRESS); 238CTASSERT((DMAP_MAX_ADDRESS & ~L0_OFFSET) == DMAP_MAX_ADDRESS); 239 240#define DMAP_TABLES ((DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS) >> L0_SHIFT) 241extern pt_entry_t pagetable_dmap[]; 242 243static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 244 245static int superpages_enabled = 0; 246SYSCTL_INT(_vm_pmap, OID_AUTO, superpages_enabled, 247 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &superpages_enabled, 0, 248 "Are large page mappings enabled?"); 249 250/* 251 * Data for the pv entry allocation mechanism 252 */ 253static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 254static struct mtx pv_chunks_mutex; 255static struct rwlock pv_list_locks[NPV_LIST_LOCKS]; 256 257static void free_pv_chunk(struct pv_chunk *pc); 258static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 259static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp); 260static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp); 261static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 262static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 263 vm_offset_t va); 264 265static int pmap_change_attr(vm_offset_t va, vm_size_t size, int mode); 266static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode); 267static pt_entry_t *pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va); 268static pt_entry_t *pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, 269 vm_offset_t va, struct rwlock **lockp); 270static pt_entry_t *pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va); 271static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 272 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp); 273static int pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t sva, 274 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp); 275static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 276 vm_page_t m, struct rwlock **lockp); 277 278static vm_page_t _pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, 279 struct rwlock **lockp); 280 281static void _pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, 282 struct spglist *free); 283static int pmap_unuse_l3(pmap_t, vm_offset_t, pd_entry_t, struct spglist *); 284 285/* 286 * These load the old table data and store the new value. 287 * They need to be atomic as the System MMU may write to the table at 288 * the same time as the CPU. 289 */ 290#define pmap_load_store(table, entry) atomic_swap_64(table, entry) 291#define pmap_set(table, mask) atomic_set_64(table, mask) 292#define pmap_load_clear(table) atomic_swap_64(table, 0) 293#define pmap_load(table) (*table) 294 295/********************/ 296/* Inline functions */ 297/********************/ 298 299static __inline void 300pagecopy(void *s, void *d) 301{ 302 303 memcpy(d, s, PAGE_SIZE); 304} 305 306#define pmap_l0_index(va) (((va) >> L0_SHIFT) & L0_ADDR_MASK) 307#define pmap_l1_index(va) (((va) >> L1_SHIFT) & Ln_ADDR_MASK) 308#define pmap_l2_index(va) (((va) >> L2_SHIFT) & Ln_ADDR_MASK) 309#define pmap_l3_index(va) (((va) >> L3_SHIFT) & Ln_ADDR_MASK) 310 311static __inline pd_entry_t * 312pmap_l0(pmap_t pmap, vm_offset_t va) 313{ 314 315 return (&pmap->pm_l0[pmap_l0_index(va)]); 316} 317 318static __inline pd_entry_t * 319pmap_l0_to_l1(pd_entry_t *l0, vm_offset_t va) 320{ 321 pd_entry_t *l1; 322 323 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK); 324 return (&l1[pmap_l1_index(va)]); 325} 326 327static __inline pd_entry_t * 328pmap_l1(pmap_t pmap, vm_offset_t va) 329{ 330 pd_entry_t *l0; 331 332 l0 = pmap_l0(pmap, va); 333 if ((pmap_load(l0) & ATTR_DESCR_MASK) != L0_TABLE) 334 return (NULL); 335 336 return (pmap_l0_to_l1(l0, va)); 337} 338 339static __inline pd_entry_t * 340pmap_l1_to_l2(pd_entry_t *l1, vm_offset_t va) 341{ 342 pd_entry_t *l2; 343 344 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK); 345 return (&l2[pmap_l2_index(va)]); 346} 347 348static __inline pd_entry_t * 349pmap_l2(pmap_t pmap, vm_offset_t va) 350{ 351 pd_entry_t *l1; 352 353 l1 = pmap_l1(pmap, va); 354 if ((pmap_load(l1) & ATTR_DESCR_MASK) != L1_TABLE) 355 return (NULL); 356 357 return (pmap_l1_to_l2(l1, va)); 358} 359 360static __inline pt_entry_t * 361pmap_l2_to_l3(pd_entry_t *l2, vm_offset_t va) 362{ 363 pt_entry_t *l3; 364 365 l3 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l2) & ~ATTR_MASK); 366 return (&l3[pmap_l3_index(va)]); 367} 368 369/* 370 * Returns the lowest valid pde for a given virtual address. 371 * The next level may or may not point to a valid page or block. 372 */ 373static __inline pd_entry_t * 374pmap_pde(pmap_t pmap, vm_offset_t va, int *level) 375{ 376 pd_entry_t *l0, *l1, *l2, desc; 377 378 l0 = pmap_l0(pmap, va); 379 desc = pmap_load(l0) & ATTR_DESCR_MASK; 380 if (desc != L0_TABLE) { 381 *level = -1; 382 return (NULL); 383 } 384 385 l1 = pmap_l0_to_l1(l0, va); 386 desc = pmap_load(l1) & ATTR_DESCR_MASK; 387 if (desc != L1_TABLE) { 388 *level = 0; 389 return (l0); 390 } 391 392 l2 = pmap_l1_to_l2(l1, va); 393 desc = pmap_load(l2) & ATTR_DESCR_MASK; 394 if (desc != L2_TABLE) { 395 *level = 1; 396 return (l1); 397 } 398 399 *level = 2; 400 return (l2); 401} 402 403/* 404 * Returns the lowest valid pte block or table entry for a given virtual 405 * address. If there are no valid entries return NULL and set the level to 406 * the first invalid level. 407 */ 408static __inline pt_entry_t * 409pmap_pte(pmap_t pmap, vm_offset_t va, int *level) 410{ 411 pd_entry_t *l1, *l2, desc; 412 pt_entry_t *l3; 413 414 l1 = pmap_l1(pmap, va); 415 if (l1 == NULL) { 416 *level = 0; 417 return (NULL); 418 } 419 desc = pmap_load(l1) & ATTR_DESCR_MASK; 420 if (desc == L1_BLOCK) { 421 *level = 1; 422 return (l1); 423 } 424 425 if (desc != L1_TABLE) { 426 *level = 1; 427 return (NULL); 428 } 429 430 l2 = pmap_l1_to_l2(l1, va); 431 desc = pmap_load(l2) & ATTR_DESCR_MASK; 432 if (desc == L2_BLOCK) { 433 *level = 2; 434 return (l2); 435 } 436 437 if (desc != L2_TABLE) { 438 *level = 2; 439 return (NULL); 440 } 441 442 *level = 3; 443 l3 = pmap_l2_to_l3(l2, va); 444 if ((pmap_load(l3) & ATTR_DESCR_MASK) != L3_PAGE) 445 return (NULL); 446 447 return (l3); 448} 449 450static inline bool 451pmap_superpages_enabled(void) 452{ 453 454 return (superpages_enabled != 0); 455} 456 457bool 458pmap_get_tables(pmap_t pmap, vm_offset_t va, pd_entry_t **l0, pd_entry_t **l1, 459 pd_entry_t **l2, pt_entry_t **l3) 460{ 461 pd_entry_t *l0p, *l1p, *l2p; 462 463 if (pmap->pm_l0 == NULL) 464 return (false); 465 466 l0p = pmap_l0(pmap, va); 467 *l0 = l0p; 468 469 if ((pmap_load(l0p) & ATTR_DESCR_MASK) != L0_TABLE) 470 return (false); 471 472 l1p = pmap_l0_to_l1(l0p, va); 473 *l1 = l1p; 474 475 if ((pmap_load(l1p) & ATTR_DESCR_MASK) == L1_BLOCK) { 476 *l2 = NULL; 477 *l3 = NULL; 478 return (true); 479 } 480 481 if ((pmap_load(l1p) & ATTR_DESCR_MASK) != L1_TABLE) 482 return (false); 483 484 l2p = pmap_l1_to_l2(l1p, va); 485 *l2 = l2p; 486 487 if ((pmap_load(l2p) & ATTR_DESCR_MASK) == L2_BLOCK) { 488 *l3 = NULL; 489 return (true); 490 } 491 492 *l3 = pmap_l2_to_l3(l2p, va); 493 494 return (true); 495} 496 497static __inline int 498pmap_is_current(pmap_t pmap) 499{ 500 501 return ((pmap == pmap_kernel()) || 502 (pmap == curthread->td_proc->p_vmspace->vm_map.pmap)); 503} 504 505static __inline int 506pmap_l3_valid(pt_entry_t l3) 507{ 508 509 return ((l3 & ATTR_DESCR_MASK) == L3_PAGE); 510} 511 512 513/* Is a level 1 or 2entry a valid block and cacheable */ 514CTASSERT(L1_BLOCK == L2_BLOCK); 515static __inline int 516pmap_pte_valid_cacheable(pt_entry_t pte) 517{ 518 519 return (((pte & ATTR_DESCR_MASK) == L1_BLOCK) && 520 ((pte & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY))); 521} 522 523static __inline int 524pmap_l3_valid_cacheable(pt_entry_t l3) 525{ 526 527 return (((l3 & ATTR_DESCR_MASK) == L3_PAGE) && 528 ((l3 & ATTR_IDX_MASK) == ATTR_IDX(CACHED_MEMORY))); 529} 530 531#define PTE_SYNC(pte) cpu_dcache_wb_range((vm_offset_t)pte, sizeof(*pte)) 532 533/* 534 * Checks if the page is dirty. We currently lack proper tracking of this on 535 * arm64 so for now assume is a page mapped as rw was accessed it is. 536 */ 537static inline int 538pmap_page_dirty(pt_entry_t pte) 539{ 540 541 return ((pte & (ATTR_AF | ATTR_AP_RW_BIT)) == 542 (ATTR_AF | ATTR_AP(ATTR_AP_RW))); 543} 544 545static __inline void 546pmap_resident_count_inc(pmap_t pmap, int count) 547{ 548 549 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 550 pmap->pm_stats.resident_count += count; 551} 552 553static __inline void 554pmap_resident_count_dec(pmap_t pmap, int count) 555{ 556 557 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 558 KASSERT(pmap->pm_stats.resident_count >= count, 559 ("pmap %p resident count underflow %ld %d", pmap, 560 pmap->pm_stats.resident_count, count)); 561 pmap->pm_stats.resident_count -= count; 562} 563 564static pt_entry_t * 565pmap_early_page_idx(vm_offset_t l1pt, vm_offset_t va, u_int *l1_slot, 566 u_int *l2_slot) 567{ 568 pt_entry_t *l2; 569 pd_entry_t *l1; 570 571 l1 = (pd_entry_t *)l1pt; 572 *l1_slot = (va >> L1_SHIFT) & Ln_ADDR_MASK; 573 574 /* Check locore has used a table L1 map */ 575 KASSERT((l1[*l1_slot] & ATTR_DESCR_MASK) == L1_TABLE, 576 ("Invalid bootstrap L1 table")); 577 /* Find the address of the L2 table */ 578 l2 = (pt_entry_t *)init_pt_va; 579 *l2_slot = pmap_l2_index(va); 580 581 return (l2); 582} 583 584static vm_paddr_t 585pmap_early_vtophys(vm_offset_t l1pt, vm_offset_t va) 586{ 587 u_int l1_slot, l2_slot; 588 pt_entry_t *l2; 589 590 l2 = pmap_early_page_idx(l1pt, va, &l1_slot, &l2_slot); 591 592 return ((l2[l2_slot] & ~ATTR_MASK) + (va & L2_OFFSET)); 593} 594 595static void 596pmap_bootstrap_dmap(vm_offset_t kern_l1, vm_paddr_t min_pa, vm_paddr_t max_pa) 597{ 598 vm_offset_t va; 599 vm_paddr_t pa; 600 u_int l1_slot; 601 602 pa = dmap_phys_base = min_pa & ~L1_OFFSET; 603 va = DMAP_MIN_ADDRESS; 604 for (; va < DMAP_MAX_ADDRESS && pa < max_pa; 605 pa += L1_SIZE, va += L1_SIZE, l1_slot++) { 606 l1_slot = ((va - DMAP_MIN_ADDRESS) >> L1_SHIFT); 607 608 pmap_load_store(&pagetable_dmap[l1_slot], 609 (pa & ~L1_OFFSET) | ATTR_DEFAULT | ATTR_XN | 610 ATTR_IDX(CACHED_MEMORY) | L1_BLOCK); 611 } 612 613 /* Set the upper limit of the DMAP region */ 614 dmap_phys_max = pa; 615 dmap_max_addr = va; 616 617 cpu_dcache_wb_range((vm_offset_t)pagetable_dmap, 618 PAGE_SIZE * DMAP_TABLES); 619 cpu_tlb_flushID(); 620} 621 622static vm_offset_t 623pmap_bootstrap_l2(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l2_start) 624{ 625 vm_offset_t l2pt; 626 vm_paddr_t pa; 627 pd_entry_t *l1; 628 u_int l1_slot; 629 630 KASSERT((va & L1_OFFSET) == 0, ("Invalid virtual address")); 631 632 l1 = (pd_entry_t *)l1pt; 633 l1_slot = pmap_l1_index(va); 634 l2pt = l2_start; 635 636 for (; va < VM_MAX_KERNEL_ADDRESS; l1_slot++, va += L1_SIZE) { 637 KASSERT(l1_slot < Ln_ENTRIES, ("Invalid L1 index")); 638 639 pa = pmap_early_vtophys(l1pt, l2pt); 640 pmap_load_store(&l1[l1_slot], 641 (pa & ~Ln_TABLE_MASK) | L1_TABLE); 642 l2pt += PAGE_SIZE; 643 } 644 645 /* Clean the L2 page table */ 646 memset((void *)l2_start, 0, l2pt - l2_start); 647 cpu_dcache_wb_range(l2_start, l2pt - l2_start); 648 649 /* Flush the l1 table to ram */ 650 cpu_dcache_wb_range((vm_offset_t)l1, PAGE_SIZE); 651 652 return l2pt; 653} 654 655static vm_offset_t 656pmap_bootstrap_l3(vm_offset_t l1pt, vm_offset_t va, vm_offset_t l3_start) 657{ 658 vm_offset_t l2pt, l3pt; 659 vm_paddr_t pa; 660 pd_entry_t *l2; 661 u_int l2_slot; 662 663 KASSERT((va & L2_OFFSET) == 0, ("Invalid virtual address")); 664 665 l2 = pmap_l2(kernel_pmap, va); 666 l2 = (pd_entry_t *)rounddown2((uintptr_t)l2, PAGE_SIZE); 667 l2pt = (vm_offset_t)l2; 668 l2_slot = pmap_l2_index(va); 669 l3pt = l3_start; 670 671 for (; va < VM_MAX_KERNEL_ADDRESS; l2_slot++, va += L2_SIZE) { 672 KASSERT(l2_slot < Ln_ENTRIES, ("Invalid L2 index")); 673 674 pa = pmap_early_vtophys(l1pt, l3pt); 675 pmap_load_store(&l2[l2_slot], 676 (pa & ~Ln_TABLE_MASK) | L2_TABLE); 677 l3pt += PAGE_SIZE; 678 } 679 680 /* Clean the L2 page table */ 681 memset((void *)l3_start, 0, l3pt - l3_start); 682 cpu_dcache_wb_range(l3_start, l3pt - l3_start); 683 684 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE); 685 686 return l3pt; 687} 688 689/* 690 * Bootstrap the system enough to run with virtual memory. 691 */ 692void 693pmap_bootstrap(vm_offset_t l0pt, vm_offset_t l1pt, vm_paddr_t kernstart, 694 vm_size_t kernlen) 695{ 696 u_int l1_slot, l2_slot, avail_slot, map_slot, used_map_slot; 697 uint64_t kern_delta; 698 pt_entry_t *l2; 699 vm_offset_t va, freemempos; 700 vm_offset_t dpcpu, msgbufpv; 701 vm_paddr_t pa, max_pa, min_pa; 702 int i; 703 704 kern_delta = KERNBASE - kernstart; 705 physmem = 0; 706 707 printf("pmap_bootstrap %lx %lx %lx\n", l1pt, kernstart, kernlen); 708 printf("%lx\n", l1pt); 709 printf("%lx\n", (KERNBASE >> L1_SHIFT) & Ln_ADDR_MASK); 710 711 /* Set this early so we can use the pagetable walking functions */ 712 kernel_pmap_store.pm_l0 = (pd_entry_t *)l0pt; 713 PMAP_LOCK_INIT(kernel_pmap); 714 715 /* Assume the address we were loaded to is a valid physical address */ 716 min_pa = max_pa = KERNBASE - kern_delta; 717 718 /* 719 * Find the minimum physical address. physmap is sorted, 720 * but may contain empty ranges. 721 */ 722 for (i = 0; i < (physmap_idx * 2); i += 2) { 723 if (physmap[i] == physmap[i + 1]) 724 continue; 725 if (physmap[i] <= min_pa) 726 min_pa = physmap[i]; 727 if (physmap[i + 1] > max_pa) 728 max_pa = physmap[i + 1]; 729 } 730 731 /* Create a direct map region early so we can use it for pa -> va */ 732 pmap_bootstrap_dmap(l1pt, min_pa, max_pa); 733 734 va = KERNBASE; 735 pa = KERNBASE - kern_delta; 736 737 /* 738 * Start to initialise phys_avail by copying from physmap 739 * up to the physical address KERNBASE points at. 740 */ 741 map_slot = avail_slot = 0; 742 for (; map_slot < (physmap_idx * 2) && 743 avail_slot < (PHYS_AVAIL_SIZE - 2); map_slot += 2) { 744 if (physmap[map_slot] == physmap[map_slot + 1]) 745 continue; 746 747 if (physmap[map_slot] <= pa && 748 physmap[map_slot + 1] > pa) 749 break; 750 751 phys_avail[avail_slot] = physmap[map_slot]; 752 phys_avail[avail_slot + 1] = physmap[map_slot + 1]; 753 physmem += (phys_avail[avail_slot + 1] - 754 phys_avail[avail_slot]) >> PAGE_SHIFT; 755 avail_slot += 2; 756 } 757 758 /* Add the memory before the kernel */ 759 if (physmap[avail_slot] < pa && avail_slot < (PHYS_AVAIL_SIZE - 2)) { 760 phys_avail[avail_slot] = physmap[map_slot]; 761 phys_avail[avail_slot + 1] = pa; 762 physmem += (phys_avail[avail_slot + 1] - 763 phys_avail[avail_slot]) >> PAGE_SHIFT; 764 avail_slot += 2; 765 } 766 used_map_slot = map_slot; 767 768 /* 769 * Read the page table to find out what is already mapped. 770 * This assumes we have mapped a block of memory from KERNBASE 771 * using a single L1 entry. 772 */ 773 l2 = pmap_early_page_idx(l1pt, KERNBASE, &l1_slot, &l2_slot); 774 775 /* Sanity check the index, KERNBASE should be the first VA */ 776 KASSERT(l2_slot == 0, ("The L2 index is non-zero")); 777 778 /* Find how many pages we have mapped */ 779 for (; l2_slot < Ln_ENTRIES; l2_slot++) { 780 if ((l2[l2_slot] & ATTR_DESCR_MASK) == 0) 781 break; 782 783 /* Check locore used L2 blocks */ 784 KASSERT((l2[l2_slot] & ATTR_DESCR_MASK) == L2_BLOCK, 785 ("Invalid bootstrap L2 table")); 786 KASSERT((l2[l2_slot] & ~ATTR_MASK) == pa, 787 ("Incorrect PA in L2 table")); 788 789 va += L2_SIZE; 790 pa += L2_SIZE; 791 } 792 793 va = roundup2(va, L1_SIZE); 794 795 freemempos = KERNBASE + kernlen; 796 freemempos = roundup2(freemempos, PAGE_SIZE); 797 /* Create the l2 tables up to VM_MAX_KERNEL_ADDRESS */ 798 freemempos = pmap_bootstrap_l2(l1pt, va, freemempos); 799 /* And the l3 tables for the early devmap */ 800 freemempos = pmap_bootstrap_l3(l1pt, 801 VM_MAX_KERNEL_ADDRESS - L2_SIZE, freemempos); 802 803 cpu_tlb_flushID(); 804 805#define alloc_pages(var, np) \ 806 (var) = freemempos; \ 807 freemempos += (np * PAGE_SIZE); \ 808 memset((char *)(var), 0, ((np) * PAGE_SIZE)); 809 810 /* Allocate dynamic per-cpu area. */ 811 alloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 812 dpcpu_init((void *)dpcpu, 0); 813 814 /* Allocate memory for the msgbuf, e.g. for /sbin/dmesg */ 815 alloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 816 msgbufp = (void *)msgbufpv; 817 818 virtual_avail = roundup2(freemempos, L1_SIZE); 819 virtual_end = VM_MAX_KERNEL_ADDRESS - L2_SIZE; 820 kernel_vm_end = virtual_avail; 821 822 pa = pmap_early_vtophys(l1pt, freemempos); 823 824 /* Finish initialising physmap */ 825 map_slot = used_map_slot; 826 for (; avail_slot < (PHYS_AVAIL_SIZE - 2) && 827 map_slot < (physmap_idx * 2); map_slot += 2) { 828 if (physmap[map_slot] == physmap[map_slot + 1]) 829 continue; 830 831 /* Have we used the current range? */ 832 if (physmap[map_slot + 1] <= pa) 833 continue; 834 835 /* Do we need to split the entry? */ 836 if (physmap[map_slot] < pa) { 837 phys_avail[avail_slot] = pa; 838 phys_avail[avail_slot + 1] = physmap[map_slot + 1]; 839 } else { 840 phys_avail[avail_slot] = physmap[map_slot]; 841 phys_avail[avail_slot + 1] = physmap[map_slot + 1]; 842 } 843 physmem += (phys_avail[avail_slot + 1] - 844 phys_avail[avail_slot]) >> PAGE_SHIFT; 845 846 avail_slot += 2; 847 } 848 phys_avail[avail_slot] = 0; 849 phys_avail[avail_slot + 1] = 0; 850 851 /* 852 * Maxmem isn't the "maximum memory", it's one larger than the 853 * highest page of the physical address space. It should be 854 * called something like "Maxphyspage". 855 */ 856 Maxmem = atop(phys_avail[avail_slot - 1]); 857 858 cpu_tlb_flushID(); 859} 860 861/* 862 * Initialize a vm_page's machine-dependent fields. 863 */ 864void 865pmap_page_init(vm_page_t m) 866{ 867 868 TAILQ_INIT(&m->md.pv_list); 869 m->md.pv_memattr = VM_MEMATTR_WRITE_BACK; 870} 871 872/* 873 * Initialize the pmap module. 874 * Called by vm_init, to initialize any structures that the pmap 875 * system needs to map virtual memory. 876 */ 877void 878pmap_init(void) 879{ 880 vm_size_t s; 881 int i, pv_npg; 882 883 /* 884 * Are large page mappings enabled? 885 */ 886 TUNABLE_INT_FETCH("vm.pmap.superpages_enabled", &superpages_enabled); 887 888 /* 889 * Initialize the pv chunk list mutex. 890 */ 891 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF); 892 893 /* 894 * Initialize the pool of pv list locks. 895 */ 896 for (i = 0; i < NPV_LIST_LOCKS; i++) 897 rw_init(&pv_list_locks[i], "pmap pv list"); 898 899 /* 900 * Calculate the size of the pv head table for superpages. 901 */ 902 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, L2_SIZE); 903 904 /* 905 * Allocate memory for the pv head table for superpages. 906 */ 907 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 908 s = round_page(s); 909 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s, 910 M_WAITOK | M_ZERO); 911 for (i = 0; i < pv_npg; i++) 912 TAILQ_INIT(&pv_table[i].pv_list); 913 TAILQ_INIT(&pv_dummy.pv_list); 914} 915 916static SYSCTL_NODE(_vm_pmap, OID_AUTO, l2, CTLFLAG_RD, 0, 917 "2MB page mapping counters"); 918 919static u_long pmap_l2_demotions; 920SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, demotions, CTLFLAG_RD, 921 &pmap_l2_demotions, 0, "2MB page demotions"); 922 923static u_long pmap_l2_p_failures; 924SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, p_failures, CTLFLAG_RD, 925 &pmap_l2_p_failures, 0, "2MB page promotion failures"); 926 927static u_long pmap_l2_promotions; 928SYSCTL_ULONG(_vm_pmap_l2, OID_AUTO, promotions, CTLFLAG_RD, 929 &pmap_l2_promotions, 0, "2MB page promotions"); 930 931/* 932 * Invalidate a single TLB entry. 933 */ 934PMAP_INLINE void 935pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 936{ 937 938 sched_pin(); 939 __asm __volatile( 940 "dsb ishst \n" 941 "tlbi vaae1is, %0 \n" 942 "dsb ish \n" 943 "isb \n" 944 : : "r"(va >> PAGE_SHIFT)); 945 sched_unpin(); 946} 947 948PMAP_INLINE void 949pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 950{ 951 vm_offset_t addr; 952 953 sched_pin(); 954 dsb(ishst); 955 for (addr = sva; addr < eva; addr += PAGE_SIZE) { 956 __asm __volatile( 957 "tlbi vaae1is, %0" : : "r"(addr >> PAGE_SHIFT)); 958 } 959 __asm __volatile( 960 "dsb ish \n" 961 "isb \n"); 962 sched_unpin(); 963} 964 965PMAP_INLINE void 966pmap_invalidate_all(pmap_t pmap) 967{ 968 969 sched_pin(); 970 __asm __volatile( 971 "dsb ishst \n" 972 "tlbi vmalle1is \n" 973 "dsb ish \n" 974 "isb \n"); 975 sched_unpin(); 976} 977 978/* 979 * Routine: pmap_extract 980 * Function: 981 * Extract the physical page address associated 982 * with the given map/virtual_address pair. 983 */ 984vm_paddr_t 985pmap_extract(pmap_t pmap, vm_offset_t va) 986{ 987 pt_entry_t *pte, tpte; 988 vm_paddr_t pa; 989 int lvl; 990 991 pa = 0; 992 PMAP_LOCK(pmap); 993 /* 994 * Find the block or page map for this virtual address. pmap_pte 995 * will return either a valid block/page entry, or NULL. 996 */ 997 pte = pmap_pte(pmap, va, &lvl); 998 if (pte != NULL) { 999 tpte = pmap_load(pte); 1000 pa = tpte & ~ATTR_MASK; 1001 switch(lvl) { 1002 case 1: 1003 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK, 1004 ("pmap_extract: Invalid L1 pte found: %lx", 1005 tpte & ATTR_DESCR_MASK)); 1006 pa |= (va & L1_OFFSET); 1007 break; 1008 case 2: 1009 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK, 1010 ("pmap_extract: Invalid L2 pte found: %lx", 1011 tpte & ATTR_DESCR_MASK)); 1012 pa |= (va & L2_OFFSET); 1013 break; 1014 case 3: 1015 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE, 1016 ("pmap_extract: Invalid L3 pte found: %lx", 1017 tpte & ATTR_DESCR_MASK)); 1018 pa |= (va & L3_OFFSET); 1019 break; 1020 } 1021 } 1022 PMAP_UNLOCK(pmap); 1023 return (pa); 1024} 1025 1026/* 1027 * Routine: pmap_extract_and_hold 1028 * Function: 1029 * Atomically extract and hold the physical page 1030 * with the given pmap and virtual address pair 1031 * if that mapping permits the given protection. 1032 */ 1033vm_page_t 1034pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1035{ 1036 pt_entry_t *pte, tpte; 1037 vm_offset_t off; 1038 vm_paddr_t pa; 1039 vm_page_t m; 1040 int lvl; 1041 1042 pa = 0; 1043 m = NULL; 1044 PMAP_LOCK(pmap); 1045retry: 1046 pte = pmap_pte(pmap, va, &lvl); 1047 if (pte != NULL) { 1048 tpte = pmap_load(pte); 1049 1050 KASSERT(lvl > 0 && lvl <= 3, 1051 ("pmap_extract_and_hold: Invalid level %d", lvl)); 1052 CTASSERT(L1_BLOCK == L2_BLOCK); 1053 KASSERT((lvl == 3 && (tpte & ATTR_DESCR_MASK) == L3_PAGE) || 1054 (lvl < 3 && (tpte & ATTR_DESCR_MASK) == L1_BLOCK), 1055 ("pmap_extract_and_hold: Invalid pte at L%d: %lx", lvl, 1056 tpte & ATTR_DESCR_MASK)); 1057 if (((tpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) || 1058 ((prot & VM_PROT_WRITE) == 0)) { 1059 switch(lvl) { 1060 case 1: 1061 off = va & L1_OFFSET; 1062 break; 1063 case 2: 1064 off = va & L2_OFFSET; 1065 break; 1066 case 3: 1067 default: 1068 off = 0; 1069 } 1070 if (vm_page_pa_tryrelock(pmap, 1071 (tpte & ~ATTR_MASK) | off, &pa)) 1072 goto retry; 1073 m = PHYS_TO_VM_PAGE((tpte & ~ATTR_MASK) | off); 1074 vm_page_hold(m); 1075 } 1076 } 1077 PA_UNLOCK_COND(pa); 1078 PMAP_UNLOCK(pmap); 1079 return (m); 1080} 1081 1082vm_paddr_t 1083pmap_kextract(vm_offset_t va) 1084{ 1085 pt_entry_t *pte, tpte; 1086 vm_paddr_t pa; 1087 int lvl; 1088 1089 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) { 1090 pa = DMAP_TO_PHYS(va); 1091 } else { 1092 pa = 0; 1093 pte = pmap_pte(kernel_pmap, va, &lvl); 1094 if (pte != NULL) { 1095 tpte = pmap_load(pte); 1096 pa = tpte & ~ATTR_MASK; 1097 switch(lvl) { 1098 case 1: 1099 KASSERT((tpte & ATTR_DESCR_MASK) == L1_BLOCK, 1100 ("pmap_kextract: Invalid L1 pte found: %lx", 1101 tpte & ATTR_DESCR_MASK)); 1102 pa |= (va & L1_OFFSET); 1103 break; 1104 case 2: 1105 KASSERT((tpte & ATTR_DESCR_MASK) == L2_BLOCK, 1106 ("pmap_kextract: Invalid L2 pte found: %lx", 1107 tpte & ATTR_DESCR_MASK)); 1108 pa |= (va & L2_OFFSET); 1109 break; 1110 case 3: 1111 KASSERT((tpte & ATTR_DESCR_MASK) == L3_PAGE, 1112 ("pmap_kextract: Invalid L3 pte found: %lx", 1113 tpte & ATTR_DESCR_MASK)); 1114 pa |= (va & L3_OFFSET); 1115 break; 1116 } 1117 } 1118 } 1119 return (pa); 1120} 1121 1122/*************************************************** 1123 * Low level mapping routines..... 1124 ***************************************************/ 1125 1126static void 1127pmap_kenter(vm_offset_t sva, vm_size_t size, vm_paddr_t pa, int mode) 1128{ 1129 pd_entry_t *pde; 1130 pt_entry_t *pte, attr; 1131 vm_offset_t va; 1132 int lvl; 1133 1134 KASSERT((pa & L3_OFFSET) == 0, 1135 ("pmap_kenter: Invalid physical address")); 1136 KASSERT((sva & L3_OFFSET) == 0, 1137 ("pmap_kenter: Invalid virtual address")); 1138 KASSERT((size & PAGE_MASK) == 0, 1139 ("pmap_kenter: Mapping is not page-sized")); 1140 1141 attr = ATTR_DEFAULT | ATTR_IDX(mode) | L3_PAGE; 1142 if (mode == DEVICE_MEMORY) 1143 attr |= ATTR_XN; 1144 1145 va = sva; 1146 while (size != 0) { 1147 pde = pmap_pde(kernel_pmap, va, &lvl); 1148 KASSERT(pde != NULL, 1149 ("pmap_kenter: Invalid page entry, va: 0x%lx", va)); 1150 KASSERT(lvl == 2, ("pmap_kenter: Invalid level %d", lvl)); 1151 1152 pte = pmap_l2_to_l3(pde, va); 1153 pmap_load_store(pte, (pa & ~L3_OFFSET) | attr); 1154 PTE_SYNC(pte); 1155 1156 va += PAGE_SIZE; 1157 pa += PAGE_SIZE; 1158 size -= PAGE_SIZE; 1159 } 1160 pmap_invalidate_range(kernel_pmap, sva, va); 1161} 1162 1163void 1164pmap_kenter_device(vm_offset_t sva, vm_size_t size, vm_paddr_t pa) 1165{ 1166 1167 pmap_kenter(sva, size, pa, DEVICE_MEMORY); 1168} 1169 1170/* 1171 * Remove a page from the kernel pagetables. 1172 */ 1173PMAP_INLINE void 1174pmap_kremove(vm_offset_t va) 1175{ 1176 pt_entry_t *pte; 1177 int lvl; 1178 1179 pte = pmap_pte(kernel_pmap, va, &lvl); 1180 KASSERT(pte != NULL, ("pmap_kremove: Invalid address")); 1181 KASSERT(lvl == 3, ("pmap_kremove: Invalid pte level %d", lvl)); 1182 1183 if (pmap_l3_valid_cacheable(pmap_load(pte))) 1184 cpu_dcache_wb_range(va, L3_SIZE); 1185 pmap_load_clear(pte); 1186 PTE_SYNC(pte); 1187 pmap_invalidate_page(kernel_pmap, va); 1188} 1189 1190void 1191pmap_kremove_device(vm_offset_t sva, vm_size_t size) 1192{ 1193 pt_entry_t *pte; 1194 vm_offset_t va; 1195 int lvl; 1196 1197 KASSERT((sva & L3_OFFSET) == 0, 1198 ("pmap_kremove_device: Invalid virtual address")); 1199 KASSERT((size & PAGE_MASK) == 0, 1200 ("pmap_kremove_device: Mapping is not page-sized")); 1201 1202 va = sva; 1203 while (size != 0) { 1204 pte = pmap_pte(kernel_pmap, va, &lvl); 1205 KASSERT(pte != NULL, ("Invalid page table, va: 0x%lx", va)); 1206 KASSERT(lvl == 3, 1207 ("Invalid device pagetable level: %d != 3", lvl)); 1208 pmap_load_clear(pte); 1209 PTE_SYNC(pte); 1210 1211 va += PAGE_SIZE; 1212 size -= PAGE_SIZE; 1213 } 1214 pmap_invalidate_range(kernel_pmap, sva, va); 1215} 1216 1217/* 1218 * Used to map a range of physical addresses into kernel 1219 * virtual address space. 1220 * 1221 * The value passed in '*virt' is a suggested virtual address for 1222 * the mapping. Architectures which can support a direct-mapped 1223 * physical to virtual region can return the appropriate address 1224 * within that region, leaving '*virt' unchanged. Other 1225 * architectures should map the pages starting at '*virt' and 1226 * update '*virt' with the first usable address after the mapped 1227 * region. 1228 */ 1229vm_offset_t 1230pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1231{ 1232 return PHYS_TO_DMAP(start); 1233} 1234 1235 1236/* 1237 * Add a list of wired pages to the kva 1238 * this routine is only used for temporary 1239 * kernel mappings that do not need to have 1240 * page modification or references recorded. 1241 * Note that old mappings are simply written 1242 * over. The page *must* be wired. 1243 * Note: SMP coherent. Uses a ranged shootdown IPI. 1244 */ 1245void 1246pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1247{ 1248 pd_entry_t *pde; 1249 pt_entry_t *pte, pa; 1250 vm_offset_t va; 1251 vm_page_t m; 1252 int i, lvl; 1253 1254 va = sva; 1255 for (i = 0; i < count; i++) { 1256 pde = pmap_pde(kernel_pmap, va, &lvl); 1257 KASSERT(pde != NULL, 1258 ("pmap_qenter: Invalid page entry, va: 0x%lx", va)); 1259 KASSERT(lvl == 2, 1260 ("pmap_qenter: Invalid level %d", lvl)); 1261 1262 m = ma[i]; 1263 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_AP(ATTR_AP_RW) | 1264 ATTR_IDX(m->md.pv_memattr) | L3_PAGE; 1265 if (m->md.pv_memattr == DEVICE_MEMORY) 1266 pa |= ATTR_XN; 1267 pte = pmap_l2_to_l3(pde, va); 1268 pmap_load_store(pte, pa); 1269 PTE_SYNC(pte); 1270 1271 va += L3_SIZE; 1272 } 1273 pmap_invalidate_range(kernel_pmap, sva, va); 1274} 1275 1276/* 1277 * This routine tears out page mappings from the 1278 * kernel -- it is meant only for temporary mappings. 1279 */ 1280void 1281pmap_qremove(vm_offset_t sva, int count) 1282{ 1283 pt_entry_t *pte; 1284 vm_offset_t va; 1285 int lvl; 1286 1287 KASSERT(sva >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", sva)); 1288 1289 va = sva; 1290 while (count-- > 0) { 1291 pte = pmap_pte(kernel_pmap, va, &lvl); 1292 KASSERT(lvl == 3, 1293 ("Invalid device pagetable level: %d != 3", lvl)); 1294 if (pte != NULL) { 1295 if (pmap_l3_valid_cacheable(pmap_load(pte))) 1296 cpu_dcache_wb_range(va, L3_SIZE); 1297 pmap_load_clear(pte); 1298 PTE_SYNC(pte); 1299 } 1300 1301 va += PAGE_SIZE; 1302 } 1303 pmap_invalidate_range(kernel_pmap, sva, va); 1304} 1305 1306/*************************************************** 1307 * Page table page management routines..... 1308 ***************************************************/ 1309static __inline void 1310pmap_free_zero_pages(struct spglist *free) 1311{ 1312 vm_page_t m; 1313 1314 while ((m = SLIST_FIRST(free)) != NULL) { 1315 SLIST_REMOVE_HEAD(free, plinks.s.ss); 1316 /* Preserve the page's PG_ZERO setting. */ 1317 vm_page_free_toq(m); 1318 } 1319} 1320 1321/* 1322 * Schedule the specified unused page table page to be freed. Specifically, 1323 * add the page to the specified list of pages that will be released to the 1324 * physical memory manager after the TLB has been updated. 1325 */ 1326static __inline void 1327pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 1328 boolean_t set_PG_ZERO) 1329{ 1330 1331 if (set_PG_ZERO) 1332 m->flags |= PG_ZERO; 1333 else 1334 m->flags &= ~PG_ZERO; 1335 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 1336} 1337 1338/* 1339 * Decrements a page table page's wire count, which is used to record the 1340 * number of valid page table entries within the page. If the wire count 1341 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1342 * page table page was unmapped and FALSE otherwise. 1343 */ 1344static inline boolean_t 1345pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 1346{ 1347 1348 --m->wire_count; 1349 if (m->wire_count == 0) { 1350 _pmap_unwire_l3(pmap, va, m, free); 1351 return (TRUE); 1352 } else 1353 return (FALSE); 1354} 1355 1356static void 1357_pmap_unwire_l3(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free) 1358{ 1359 1360 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1361 /* 1362 * unmap the page table page 1363 */ 1364 if (m->pindex >= (NUL2E + NUL1E)) { 1365 /* l1 page */ 1366 pd_entry_t *l0; 1367 1368 l0 = pmap_l0(pmap, va); 1369 pmap_load_clear(l0); 1370 PTE_SYNC(l0); 1371 } else if (m->pindex >= NUL2E) { 1372 /* l2 page */ 1373 pd_entry_t *l1; 1374 1375 l1 = pmap_l1(pmap, va); 1376 pmap_load_clear(l1); 1377 PTE_SYNC(l1); 1378 } else { 1379 /* l3 page */ 1380 pd_entry_t *l2; 1381 1382 l2 = pmap_l2(pmap, va); 1383 pmap_load_clear(l2); 1384 PTE_SYNC(l2); 1385 } 1386 pmap_resident_count_dec(pmap, 1); 1387 if (m->pindex < NUL2E) { 1388 /* We just released an l3, unhold the matching l2 */ 1389 pd_entry_t *l1, tl1; 1390 vm_page_t l2pg; 1391 1392 l1 = pmap_l1(pmap, va); 1393 tl1 = pmap_load(l1); 1394 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK); 1395 pmap_unwire_l3(pmap, va, l2pg, free); 1396 } else if (m->pindex < (NUL2E + NUL1E)) { 1397 /* We just released an l2, unhold the matching l1 */ 1398 pd_entry_t *l0, tl0; 1399 vm_page_t l1pg; 1400 1401 l0 = pmap_l0(pmap, va); 1402 tl0 = pmap_load(l0); 1403 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK); 1404 pmap_unwire_l3(pmap, va, l1pg, free); 1405 } 1406 pmap_invalidate_page(pmap, va); 1407 1408 /* 1409 * This is a release store so that the ordinary store unmapping 1410 * the page table page is globally performed before TLB shoot- 1411 * down is begun. 1412 */ 1413 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1); 1414 1415 /* 1416 * Put page on a list so that it is released after 1417 * *ALL* TLB shootdown is done 1418 */ 1419 pmap_add_delayed_free_list(m, free, TRUE); 1420} 1421 1422/* 1423 * After removing an l3 entry, this routine is used to 1424 * conditionally free the page, and manage the hold/wire counts. 1425 */ 1426static int 1427pmap_unuse_l3(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde, 1428 struct spglist *free) 1429{ 1430 vm_page_t mpte; 1431 1432 if (va >= VM_MAXUSER_ADDRESS) 1433 return (0); 1434 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0")); 1435 mpte = PHYS_TO_VM_PAGE(ptepde & ~ATTR_MASK); 1436 return (pmap_unwire_l3(pmap, va, mpte, free)); 1437} 1438 1439void 1440pmap_pinit0(pmap_t pmap) 1441{ 1442 1443 PMAP_LOCK_INIT(pmap); 1444 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1445 pmap->pm_l0 = kernel_pmap->pm_l0; 1446 pmap->pm_root.rt_root = 0; 1447} 1448 1449int 1450pmap_pinit(pmap_t pmap) 1451{ 1452 vm_paddr_t l0phys; 1453 vm_page_t l0pt; 1454 1455 /* 1456 * allocate the l0 page 1457 */ 1458 while ((l0pt = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 1459 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) 1460 VM_WAIT; 1461 1462 l0phys = VM_PAGE_TO_PHYS(l0pt); 1463 pmap->pm_l0 = (pd_entry_t *)PHYS_TO_DMAP(l0phys); 1464 1465 if ((l0pt->flags & PG_ZERO) == 0) 1466 pagezero(pmap->pm_l0); 1467 1468 pmap->pm_root.rt_root = 0; 1469 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats)); 1470 1471 return (1); 1472} 1473 1474/* 1475 * This routine is called if the desired page table page does not exist. 1476 * 1477 * If page table page allocation fails, this routine may sleep before 1478 * returning NULL. It sleeps only if a lock pointer was given. 1479 * 1480 * Note: If a page allocation fails at page table level two or three, 1481 * one or two pages may be held during the wait, only to be released 1482 * afterwards. This conservative approach is easily argued to avoid 1483 * race conditions. 1484 */ 1485static vm_page_t 1486_pmap_alloc_l3(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp) 1487{ 1488 vm_page_t m, l1pg, l2pg; 1489 1490 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1491 1492 /* 1493 * Allocate a page table page. 1494 */ 1495 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1496 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1497 if (lockp != NULL) { 1498 RELEASE_PV_LIST_LOCK(lockp); 1499 PMAP_UNLOCK(pmap); 1500 VM_WAIT; 1501 PMAP_LOCK(pmap); 1502 } 1503 1504 /* 1505 * Indicate the need to retry. While waiting, the page table 1506 * page may have been allocated. 1507 */ 1508 return (NULL); 1509 } 1510 if ((m->flags & PG_ZERO) == 0) 1511 pmap_zero_page(m); 1512 1513 /* 1514 * Map the pagetable page into the process address space, if 1515 * it isn't already there. 1516 */ 1517 1518 if (ptepindex >= (NUL2E + NUL1E)) { 1519 pd_entry_t *l0; 1520 vm_pindex_t l0index; 1521 1522 l0index = ptepindex - (NUL2E + NUL1E); 1523 l0 = &pmap->pm_l0[l0index]; 1524 pmap_load_store(l0, VM_PAGE_TO_PHYS(m) | L0_TABLE); 1525 PTE_SYNC(l0); 1526 } else if (ptepindex >= NUL2E) { 1527 vm_pindex_t l0index, l1index; 1528 pd_entry_t *l0, *l1; 1529 pd_entry_t tl0; 1530 1531 l1index = ptepindex - NUL2E; 1532 l0index = l1index >> L0_ENTRIES_SHIFT; 1533 1534 l0 = &pmap->pm_l0[l0index]; 1535 tl0 = pmap_load(l0); 1536 if (tl0 == 0) { 1537 /* recurse for allocating page dir */ 1538 if (_pmap_alloc_l3(pmap, NUL2E + NUL1E + l0index, 1539 lockp) == NULL) { 1540 --m->wire_count; 1541 /* XXX: release mem barrier? */ 1542 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1543 vm_page_free_zero(m); 1544 return (NULL); 1545 } 1546 } else { 1547 l1pg = PHYS_TO_VM_PAGE(tl0 & ~ATTR_MASK); 1548 l1pg->wire_count++; 1549 } 1550 1551 l1 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l0) & ~ATTR_MASK); 1552 l1 = &l1[ptepindex & Ln_ADDR_MASK]; 1553 pmap_load_store(l1, VM_PAGE_TO_PHYS(m) | L1_TABLE); 1554 PTE_SYNC(l1); 1555 } else { 1556 vm_pindex_t l0index, l1index; 1557 pd_entry_t *l0, *l1, *l2; 1558 pd_entry_t tl0, tl1; 1559 1560 l1index = ptepindex >> Ln_ENTRIES_SHIFT; 1561 l0index = l1index >> L0_ENTRIES_SHIFT; 1562 1563 l0 = &pmap->pm_l0[l0index]; 1564 tl0 = pmap_load(l0); 1565 if (tl0 == 0) { 1566 /* recurse for allocating page dir */ 1567 if (_pmap_alloc_l3(pmap, NUL2E + l1index, 1568 lockp) == NULL) { 1569 --m->wire_count; 1570 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1571 vm_page_free_zero(m); 1572 return (NULL); 1573 } 1574 tl0 = pmap_load(l0); 1575 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK); 1576 l1 = &l1[l1index & Ln_ADDR_MASK]; 1577 } else { 1578 l1 = (pd_entry_t *)PHYS_TO_DMAP(tl0 & ~ATTR_MASK); 1579 l1 = &l1[l1index & Ln_ADDR_MASK]; 1580 tl1 = pmap_load(l1); 1581 if (tl1 == 0) { 1582 /* recurse for allocating page dir */ 1583 if (_pmap_alloc_l3(pmap, NUL2E + l1index, 1584 lockp) == NULL) { 1585 --m->wire_count; 1586 /* XXX: release mem barrier? */ 1587 atomic_subtract_int( 1588 &vm_cnt.v_wire_count, 1); 1589 vm_page_free_zero(m); 1590 return (NULL); 1591 } 1592 } else { 1593 l2pg = PHYS_TO_VM_PAGE(tl1 & ~ATTR_MASK); 1594 l2pg->wire_count++; 1595 } 1596 } 1597 1598 l2 = (pd_entry_t *)PHYS_TO_DMAP(pmap_load(l1) & ~ATTR_MASK); 1599 l2 = &l2[ptepindex & Ln_ADDR_MASK]; 1600 pmap_load_store(l2, VM_PAGE_TO_PHYS(m) | L2_TABLE); 1601 PTE_SYNC(l2); 1602 } 1603 1604 pmap_resident_count_inc(pmap, 1); 1605 1606 return (m); 1607} 1608 1609static vm_page_t 1610pmap_alloc_l3(pmap_t pmap, vm_offset_t va, struct rwlock **lockp) 1611{ 1612 vm_pindex_t ptepindex; 1613 pd_entry_t *pde, tpde; 1614#ifdef INVARIANTS 1615 pt_entry_t *pte; 1616#endif 1617 vm_page_t m; 1618 int lvl; 1619 1620 /* 1621 * Calculate pagetable page index 1622 */ 1623 ptepindex = pmap_l2_pindex(va); 1624retry: 1625 /* 1626 * Get the page directory entry 1627 */ 1628 pde = pmap_pde(pmap, va, &lvl); 1629 1630 /* 1631 * If the page table page is mapped, we just increment the hold count, 1632 * and activate it. If we get a level 2 pde it will point to a level 3 1633 * table. 1634 */ 1635 switch (lvl) { 1636 case -1: 1637 break; 1638 case 0: 1639#ifdef INVARIANTS 1640 pte = pmap_l0_to_l1(pde, va); 1641 KASSERT(pmap_load(pte) == 0, 1642 ("pmap_alloc_l3: TODO: l0 superpages")); 1643#endif 1644 break; 1645 case 1: 1646#ifdef INVARIANTS 1647 pte = pmap_l1_to_l2(pde, va); 1648 KASSERT(pmap_load(pte) == 0, 1649 ("pmap_alloc_l3: TODO: l1 superpages")); 1650#endif 1651 break; 1652 case 2: 1653 tpde = pmap_load(pde); 1654 if (tpde != 0) { 1655 m = PHYS_TO_VM_PAGE(tpde & ~ATTR_MASK); 1656 m->wire_count++; 1657 return (m); 1658 } 1659 break; 1660 default: 1661 panic("pmap_alloc_l3: Invalid level %d", lvl); 1662 } 1663 1664 /* 1665 * Here if the pte page isn't mapped, or if it has been deallocated. 1666 */ 1667 m = _pmap_alloc_l3(pmap, ptepindex, lockp); 1668 if (m == NULL && lockp != NULL) 1669 goto retry; 1670 1671 return (m); 1672} 1673 1674 1675/*************************************************** 1676 * Pmap allocation/deallocation routines. 1677 ***************************************************/ 1678 1679/* 1680 * Release any resources held by the given physical map. 1681 * Called when a pmap initialized by pmap_pinit is being released. 1682 * Should only be called if the map contains no valid mappings. 1683 */ 1684void 1685pmap_release(pmap_t pmap) 1686{ 1687 vm_page_t m; 1688 1689 KASSERT(pmap->pm_stats.resident_count == 0, 1690 ("pmap_release: pmap resident count %ld != 0", 1691 pmap->pm_stats.resident_count)); 1692 KASSERT(vm_radix_is_empty(&pmap->pm_root), 1693 ("pmap_release: pmap has reserved page table page(s)")); 1694 1695 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_l0)); 1696 1697 m->wire_count--; 1698 atomic_subtract_int(&vm_cnt.v_wire_count, 1); 1699 vm_page_free_zero(m); 1700} 1701 1702static int 1703kvm_size(SYSCTL_HANDLER_ARGS) 1704{ 1705 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS; 1706 1707 return sysctl_handle_long(oidp, &ksize, 0, req); 1708} 1709SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 1710 0, 0, kvm_size, "LU", "Size of KVM"); 1711 1712static int 1713kvm_free(SYSCTL_HANDLER_ARGS) 1714{ 1715 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 1716 1717 return sysctl_handle_long(oidp, &kfree, 0, req); 1718} 1719SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 1720 0, 0, kvm_free, "LU", "Amount of KVM free"); 1721 1722/* 1723 * grow the number of kernel page table entries, if needed 1724 */ 1725void 1726pmap_growkernel(vm_offset_t addr) 1727{ 1728 vm_paddr_t paddr; 1729 vm_page_t nkpg; 1730 pd_entry_t *l0, *l1, *l2; 1731 1732 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1733 1734 addr = roundup2(addr, L2_SIZE); 1735 if (addr - 1 >= kernel_map->max_offset) 1736 addr = kernel_map->max_offset; 1737 while (kernel_vm_end < addr) { 1738 l0 = pmap_l0(kernel_pmap, kernel_vm_end); 1739 KASSERT(pmap_load(l0) != 0, 1740 ("pmap_growkernel: No level 0 kernel entry")); 1741 1742 l1 = pmap_l0_to_l1(l0, kernel_vm_end); 1743 if (pmap_load(l1) == 0) { 1744 /* We need a new PDP entry */ 1745 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L1_SHIFT, 1746 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | 1747 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1748 if (nkpg == NULL) 1749 panic("pmap_growkernel: no memory to grow kernel"); 1750 if ((nkpg->flags & PG_ZERO) == 0) 1751 pmap_zero_page(nkpg); 1752 paddr = VM_PAGE_TO_PHYS(nkpg); 1753 pmap_load_store(l1, paddr | L1_TABLE); 1754 PTE_SYNC(l1); 1755 continue; /* try again */ 1756 } 1757 l2 = pmap_l1_to_l2(l1, kernel_vm_end); 1758 if ((pmap_load(l2) & ATTR_AF) != 0) { 1759 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET; 1760 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1761 kernel_vm_end = kernel_map->max_offset; 1762 break; 1763 } 1764 continue; 1765 } 1766 1767 nkpg = vm_page_alloc(NULL, kernel_vm_end >> L2_SHIFT, 1768 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 1769 VM_ALLOC_ZERO); 1770 if (nkpg == NULL) 1771 panic("pmap_growkernel: no memory to grow kernel"); 1772 if ((nkpg->flags & PG_ZERO) == 0) 1773 pmap_zero_page(nkpg); 1774 paddr = VM_PAGE_TO_PHYS(nkpg); 1775 pmap_load_store(l2, paddr | L2_TABLE); 1776 PTE_SYNC(l2); 1777 pmap_invalidate_page(kernel_pmap, kernel_vm_end); 1778 1779 kernel_vm_end = (kernel_vm_end + L2_SIZE) & ~L2_OFFSET; 1780 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1781 kernel_vm_end = kernel_map->max_offset; 1782 break; 1783 } 1784 } 1785} 1786 1787 1788/*************************************************** 1789 * page management routines. 1790 ***************************************************/ 1791 1792CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 1793CTASSERT(_NPCM == 3); 1794CTASSERT(_NPCPV == 168); 1795 1796static __inline struct pv_chunk * 1797pv_to_chunk(pv_entry_t pv) 1798{ 1799 1800 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 1801} 1802 1803#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 1804 1805#define PC_FREE0 0xfffffffffffffffful 1806#define PC_FREE1 0xfffffffffffffffful 1807#define PC_FREE2 0x000000fffffffffful 1808 1809static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 }; 1810 1811#if 0 1812#ifdef PV_STATS 1813static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 1814 1815SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 1816 "Current number of pv entry chunks"); 1817SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 1818 "Current number of pv entry chunks allocated"); 1819SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 1820 "Current number of pv entry chunks frees"); 1821SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 1822 "Number of times tried to get a chunk page but failed."); 1823 1824static long pv_entry_frees, pv_entry_allocs, pv_entry_count; 1825static int pv_entry_spare; 1826 1827SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 1828 "Current number of pv entry frees"); 1829SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 1830 "Current number of pv entry allocs"); 1831SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 1832 "Current number of pv entries"); 1833SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 1834 "Current number of spare pv entries"); 1835#endif 1836#endif /* 0 */ 1837 1838/* 1839 * We are in a serious low memory condition. Resort to 1840 * drastic measures to free some pages so we can allocate 1841 * another pv entry chunk. 1842 * 1843 * Returns NULL if PV entries were reclaimed from the specified pmap. 1844 * 1845 * We do not, however, unmap 2mpages because subsequent accesses will 1846 * allocate per-page pv entries until repromotion occurs, thereby 1847 * exacerbating the shortage of free pv entries. 1848 */ 1849static vm_page_t 1850reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp) 1851{ 1852 1853 panic("ARM64TODO: reclaim_pv_chunk"); 1854} 1855 1856/* 1857 * free the pv_entry back to the free list 1858 */ 1859static void 1860free_pv_entry(pmap_t pmap, pv_entry_t pv) 1861{ 1862 struct pv_chunk *pc; 1863 int idx, field, bit; 1864 1865 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1866 PV_STAT(atomic_add_long(&pv_entry_frees, 1)); 1867 PV_STAT(atomic_add_int(&pv_entry_spare, 1)); 1868 PV_STAT(atomic_subtract_long(&pv_entry_count, 1)); 1869 pc = pv_to_chunk(pv); 1870 idx = pv - &pc->pc_pventry[0]; 1871 field = idx / 64; 1872 bit = idx % 64; 1873 pc->pc_map[field] |= 1ul << bit; 1874 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 || 1875 pc->pc_map[2] != PC_FREE2) { 1876 /* 98% of the time, pc is already at the head of the list. */ 1877 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) { 1878 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1879 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1880 } 1881 return; 1882 } 1883 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1884 free_pv_chunk(pc); 1885} 1886 1887static void 1888free_pv_chunk(struct pv_chunk *pc) 1889{ 1890 vm_page_t m; 1891 1892 mtx_lock(&pv_chunks_mutex); 1893 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 1894 mtx_unlock(&pv_chunks_mutex); 1895 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV)); 1896 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1)); 1897 PV_STAT(atomic_add_int(&pc_chunk_frees, 1)); 1898 /* entire chunk is free, return it */ 1899 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc)); 1900 dump_drop_page(m->phys_addr); 1901 vm_page_unwire(m, PQ_NONE); 1902 vm_page_free(m); 1903} 1904 1905/* 1906 * Returns a new PV entry, allocating a new PV chunk from the system when 1907 * needed. If this PV chunk allocation fails and a PV list lock pointer was 1908 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is 1909 * returned. 1910 * 1911 * The given PV list lock may be released. 1912 */ 1913static pv_entry_t 1914get_pv_entry(pmap_t pmap, struct rwlock **lockp) 1915{ 1916 int bit, field; 1917 pv_entry_t pv; 1918 struct pv_chunk *pc; 1919 vm_page_t m; 1920 1921 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1922 PV_STAT(atomic_add_long(&pv_entry_allocs, 1)); 1923retry: 1924 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 1925 if (pc != NULL) { 1926 for (field = 0; field < _NPCM; field++) { 1927 if (pc->pc_map[field]) { 1928 bit = ffsl(pc->pc_map[field]) - 1; 1929 break; 1930 } 1931 } 1932 if (field < _NPCM) { 1933 pv = &pc->pc_pventry[field * 64 + bit]; 1934 pc->pc_map[field] &= ~(1ul << bit); 1935 /* If this was the last item, move it to tail */ 1936 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && 1937 pc->pc_map[2] == 0) { 1938 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 1939 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, 1940 pc_list); 1941 } 1942 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 1943 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1)); 1944 return (pv); 1945 } 1946 } 1947 /* No free items, allocate another chunk */ 1948 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1949 VM_ALLOC_WIRED); 1950 if (m == NULL) { 1951 if (lockp == NULL) { 1952 PV_STAT(pc_chunk_tryfail++); 1953 return (NULL); 1954 } 1955 m = reclaim_pv_chunk(pmap, lockp); 1956 if (m == NULL) 1957 goto retry; 1958 } 1959 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 1960 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 1961 dump_add_page(m->phys_addr); 1962 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 1963 pc->pc_pmap = pmap; 1964 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */ 1965 pc->pc_map[1] = PC_FREE1; 1966 pc->pc_map[2] = PC_FREE2; 1967 mtx_lock(&pv_chunks_mutex); 1968 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 1969 mtx_unlock(&pv_chunks_mutex); 1970 pv = &pc->pc_pventry[0]; 1971 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 1972 PV_STAT(atomic_add_long(&pv_entry_count, 1)); 1973 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1)); 1974 return (pv); 1975} 1976 1977/* 1978 * Ensure that the number of spare PV entries in the specified pmap meets or 1979 * exceeds the given count, "needed". 1980 * 1981 * The given PV list lock may be released. 1982 */ 1983static void 1984reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp) 1985{ 1986 struct pch new_tail; 1987 struct pv_chunk *pc; 1988 int avail, free; 1989 vm_page_t m; 1990 1991 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1992 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL")); 1993 1994 /* 1995 * Newly allocated PV chunks must be stored in a private list until 1996 * the required number of PV chunks have been allocated. Otherwise, 1997 * reclaim_pv_chunk() could recycle one of these chunks. In 1998 * contrast, these chunks must be added to the pmap upon allocation. 1999 */ 2000 TAILQ_INIT(&new_tail); 2001retry: 2002 avail = 0; 2003 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) { 2004 bit_count((bitstr_t *)pc->pc_map, 0, 2005 sizeof(pc->pc_map) * NBBY, &free); 2006 if (free == 0) 2007 break; 2008 avail += free; 2009 if (avail >= needed) 2010 break; 2011 } 2012 for (; avail < needed; avail += _NPCPV) { 2013 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 2014 VM_ALLOC_WIRED); 2015 if (m == NULL) { 2016 m = reclaim_pv_chunk(pmap, lockp); 2017 if (m == NULL) 2018 goto retry; 2019 } 2020 PV_STAT(atomic_add_int(&pc_chunk_count, 1)); 2021 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1)); 2022 dump_add_page(m->phys_addr); 2023 pc = (void *)PHYS_TO_DMAP(m->phys_addr); 2024 pc->pc_pmap = pmap; 2025 pc->pc_map[0] = PC_FREE0; 2026 pc->pc_map[1] = PC_FREE1; 2027 pc->pc_map[2] = PC_FREE2; 2028 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2029 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru); 2030 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV)); 2031 } 2032 if (!TAILQ_EMPTY(&new_tail)) { 2033 mtx_lock(&pv_chunks_mutex); 2034 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru); 2035 mtx_unlock(&pv_chunks_mutex); 2036 } 2037} 2038 2039/* 2040 * First find and then remove the pv entry for the specified pmap and virtual 2041 * address from the specified pv list. Returns the pv entry if found and NULL 2042 * otherwise. This operation can be performed on pv lists for either 4KB or 2043 * 2MB page mappings. 2044 */ 2045static __inline pv_entry_t 2046pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2047{ 2048 pv_entry_t pv; 2049 2050 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2051 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2052 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2053 pvh->pv_gen++; 2054 break; 2055 } 2056 } 2057 return (pv); 2058} 2059 2060/* 2061 * After demotion from a 2MB page mapping to 512 4KB page mappings, 2062 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv 2063 * entries for each of the 4KB page mappings. 2064 */ 2065static void 2066pmap_pv_demote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 2067 struct rwlock **lockp) 2068{ 2069 struct md_page *pvh; 2070 struct pv_chunk *pc; 2071 pv_entry_t pv; 2072 vm_offset_t va_last; 2073 vm_page_t m; 2074 int bit, field; 2075 2076 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2077 KASSERT((pa & L2_OFFSET) == 0, 2078 ("pmap_pv_demote_l2: pa is not 2mpage aligned")); 2079 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 2080 2081 /* 2082 * Transfer the 2mpage's pv entry for this mapping to the first 2083 * page's pv list. Once this transfer begins, the pv list lock 2084 * must not be released until the last pv entry is reinstantiated. 2085 */ 2086 pvh = pa_to_pvh(pa); 2087 va = va & ~L2_OFFSET; 2088 pv = pmap_pvh_remove(pvh, pmap, va); 2089 KASSERT(pv != NULL, ("pmap_pv_demote_l2: pv not found")); 2090 m = PHYS_TO_VM_PAGE(pa); 2091 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2092 m->md.pv_gen++; 2093 /* Instantiate the remaining Ln_ENTRIES - 1 pv entries. */ 2094 PV_STAT(atomic_add_long(&pv_entry_allocs, Ln_ENTRIES - 1)); 2095 va_last = va + L2_SIZE - PAGE_SIZE; 2096 for (;;) { 2097 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2098 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 || 2099 pc->pc_map[2] != 0, ("pmap_pv_demote_l2: missing spare")); 2100 for (field = 0; field < _NPCM; field++) { 2101 while (pc->pc_map[field]) { 2102 bit = ffsl(pc->pc_map[field]) - 1; 2103 pc->pc_map[field] &= ~(1ul << bit); 2104 pv = &pc->pc_pventry[field * 64 + bit]; 2105 va += PAGE_SIZE; 2106 pv->pv_va = va; 2107 m++; 2108 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2109 ("pmap_pv_demote_l2: page %p is not managed", m)); 2110 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2111 m->md.pv_gen++; 2112 if (va == va_last) 2113 goto out; 2114 } 2115 } 2116 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2117 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2118 } 2119out: 2120 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) { 2121 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2122 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2123 } 2124 PV_STAT(atomic_add_long(&pv_entry_count, Ln_ENTRIES - 1)); 2125 PV_STAT(atomic_subtract_int(&pv_entry_spare, Ln_ENTRIES - 1)); 2126} 2127 2128/* 2129 * First find and then destroy the pv entry for the specified pmap and virtual 2130 * address. This operation can be performed on pv lists for either 4KB or 2MB 2131 * page mappings. 2132 */ 2133static void 2134pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2135{ 2136 pv_entry_t pv; 2137 2138 pv = pmap_pvh_remove(pvh, pmap, va); 2139 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2140 free_pv_entry(pmap, pv); 2141} 2142 2143/* 2144 * Conditionally create the PV entry for a 4KB page mapping if the required 2145 * memory can be allocated without resorting to reclamation. 2146 */ 2147static boolean_t 2148pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m, 2149 struct rwlock **lockp) 2150{ 2151 pv_entry_t pv; 2152 2153 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2154 /* Pass NULL instead of the lock pointer to disable reclamation. */ 2155 if ((pv = get_pv_entry(pmap, NULL)) != NULL) { 2156 pv->pv_va = va; 2157 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 2158 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2159 m->md.pv_gen++; 2160 return (TRUE); 2161 } else 2162 return (FALSE); 2163} 2164 2165/* 2166 * pmap_remove_l3: do the things to unmap a page in a process 2167 */ 2168static int 2169pmap_remove_l3(pmap_t pmap, pt_entry_t *l3, vm_offset_t va, 2170 pd_entry_t l2e, struct spglist *free, struct rwlock **lockp) 2171{ 2172 struct md_page *pvh; 2173 pt_entry_t old_l3; 2174 vm_page_t m; 2175 2176 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2177 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(pmap_load(l3))) 2178 cpu_dcache_wb_range(va, L3_SIZE); 2179 old_l3 = pmap_load_clear(l3); 2180 PTE_SYNC(l3); 2181 pmap_invalidate_page(pmap, va); 2182 if (old_l3 & ATTR_SW_WIRED) 2183 pmap->pm_stats.wired_count -= 1; 2184 pmap_resident_count_dec(pmap, 1); 2185 if (old_l3 & ATTR_SW_MANAGED) { 2186 m = PHYS_TO_VM_PAGE(old_l3 & ~ATTR_MASK); 2187 if (pmap_page_dirty(old_l3)) 2188 vm_page_dirty(m); 2189 if (old_l3 & ATTR_AF) 2190 vm_page_aflag_set(m, PGA_REFERENCED); 2191 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m); 2192 pmap_pvh_free(&m->md, pmap, va); 2193 if (TAILQ_EMPTY(&m->md.pv_list) && 2194 (m->flags & PG_FICTITIOUS) == 0) { 2195 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2196 if (TAILQ_EMPTY(&pvh->pv_list)) 2197 vm_page_aflag_clear(m, PGA_WRITEABLE); 2198 } 2199 } 2200 return (pmap_unuse_l3(pmap, va, l2e, free)); 2201} 2202 2203/* 2204 * Remove the given range of addresses from the specified map. 2205 * 2206 * It is assumed that the start and end are properly 2207 * rounded to the page size. 2208 */ 2209void 2210pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2211{ 2212 struct rwlock *lock; 2213 vm_offset_t va, va_next; 2214 pd_entry_t *l0, *l1, *l2; 2215 pt_entry_t l3_paddr, *l3; 2216 struct spglist free; 2217 int anyvalid; 2218 2219 /* 2220 * Perform an unsynchronized read. This is, however, safe. 2221 */ 2222 if (pmap->pm_stats.resident_count == 0) 2223 return; 2224 2225 anyvalid = 0; 2226 SLIST_INIT(&free); 2227 2228 PMAP_LOCK(pmap); 2229 2230 lock = NULL; 2231 for (; sva < eva; sva = va_next) { 2232 2233 if (pmap->pm_stats.resident_count == 0) 2234 break; 2235 2236 l0 = pmap_l0(pmap, sva); 2237 if (pmap_load(l0) == 0) { 2238 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 2239 if (va_next < sva) 2240 va_next = eva; 2241 continue; 2242 } 2243 2244 l1 = pmap_l0_to_l1(l0, sva); 2245 if (pmap_load(l1) == 0) { 2246 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 2247 if (va_next < sva) 2248 va_next = eva; 2249 continue; 2250 } 2251 2252 /* 2253 * Calculate index for next page table. 2254 */ 2255 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 2256 if (va_next < sva) 2257 va_next = eva; 2258 2259 l2 = pmap_l1_to_l2(l1, sva); 2260 if (l2 == NULL) 2261 continue; 2262 2263 l3_paddr = pmap_load(l2); 2264 2265 if ((l3_paddr & ATTR_DESCR_MASK) == L2_BLOCK) { 2266 /* TODO: Add pmap_remove_l2 */ 2267 if (pmap_demote_l2_locked(pmap, l2, sva & ~L2_OFFSET, 2268 &lock) == NULL) 2269 continue; 2270 l3_paddr = pmap_load(l2); 2271 } 2272 2273 /* 2274 * Weed out invalid mappings. 2275 */ 2276 if ((l3_paddr & ATTR_DESCR_MASK) != L2_TABLE) 2277 continue; 2278 2279 /* 2280 * Limit our scan to either the end of the va represented 2281 * by the current page table page, or to the end of the 2282 * range being removed. 2283 */ 2284 if (va_next > eva) 2285 va_next = eva; 2286 2287 va = va_next; 2288 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++, 2289 sva += L3_SIZE) { 2290 if (l3 == NULL) 2291 panic("l3 == NULL"); 2292 if (pmap_load(l3) == 0) { 2293 if (va != va_next) { 2294 pmap_invalidate_range(pmap, va, sva); 2295 va = va_next; 2296 } 2297 continue; 2298 } 2299 if (va == va_next) 2300 va = sva; 2301 if (pmap_remove_l3(pmap, l3, sva, l3_paddr, &free, 2302 &lock)) { 2303 sva += L3_SIZE; 2304 break; 2305 } 2306 } 2307 if (va != va_next) 2308 pmap_invalidate_range(pmap, va, sva); 2309 } 2310 if (lock != NULL) 2311 rw_wunlock(lock); 2312 if (anyvalid) 2313 pmap_invalidate_all(pmap); 2314 PMAP_UNLOCK(pmap); 2315 pmap_free_zero_pages(&free); 2316} 2317 2318/* 2319 * Routine: pmap_remove_all 2320 * Function: 2321 * Removes this physical page from 2322 * all physical maps in which it resides. 2323 * Reflects back modify bits to the pager. 2324 * 2325 * Notes: 2326 * Original versions of this routine were very 2327 * inefficient because they iteratively called 2328 * pmap_remove (slow...) 2329 */ 2330 2331void 2332pmap_remove_all(vm_page_t m) 2333{ 2334 struct md_page *pvh; 2335 pv_entry_t pv; 2336 pmap_t pmap; 2337 struct rwlock *lock; 2338 pd_entry_t *pde, tpde; 2339 pt_entry_t *pte, tpte; 2340 vm_offset_t va; 2341 struct spglist free; 2342 int lvl, pvh_gen, md_gen; 2343 2344 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2345 ("pmap_remove_all: page %p is not managed", m)); 2346 SLIST_INIT(&free); 2347 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 2348 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : 2349 pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2350retry: 2351 rw_wlock(lock); 2352 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 2353 pmap = PV_PMAP(pv); 2354 if (!PMAP_TRYLOCK(pmap)) { 2355 pvh_gen = pvh->pv_gen; 2356 rw_wunlock(lock); 2357 PMAP_LOCK(pmap); 2358 rw_wlock(lock); 2359 if (pvh_gen != pvh->pv_gen) { 2360 rw_wunlock(lock); 2361 PMAP_UNLOCK(pmap); 2362 goto retry; 2363 } 2364 } 2365 va = pv->pv_va; 2366 pte = pmap_pte(pmap, va, &lvl); 2367 KASSERT(pte != NULL, 2368 ("pmap_remove_all: no page table entry found")); 2369 KASSERT(lvl == 2, 2370 ("pmap_remove_all: invalid pte level %d", lvl)); 2371 2372 pmap_demote_l2_locked(pmap, pte, va, &lock); 2373 PMAP_UNLOCK(pmap); 2374 } 2375 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 2376 pmap = PV_PMAP(pv); 2377 if (!PMAP_TRYLOCK(pmap)) { 2378 pvh_gen = pvh->pv_gen; 2379 md_gen = m->md.pv_gen; 2380 rw_wunlock(lock); 2381 PMAP_LOCK(pmap); 2382 rw_wlock(lock); 2383 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 2384 rw_wunlock(lock); 2385 PMAP_UNLOCK(pmap); 2386 goto retry; 2387 } 2388 } 2389 pmap_resident_count_dec(pmap, 1); 2390 2391 pde = pmap_pde(pmap, pv->pv_va, &lvl); 2392 KASSERT(pde != NULL, 2393 ("pmap_remove_all: no page directory entry found")); 2394 KASSERT(lvl == 2, 2395 ("pmap_remove_all: invalid pde level %d", lvl)); 2396 tpde = pmap_load(pde); 2397 2398 pte = pmap_l2_to_l3(pde, pv->pv_va); 2399 tpte = pmap_load(pte); 2400 if (pmap_is_current(pmap) && 2401 pmap_l3_valid_cacheable(tpte)) 2402 cpu_dcache_wb_range(pv->pv_va, L3_SIZE); 2403 pmap_load_clear(pte); 2404 PTE_SYNC(pte); 2405 pmap_invalidate_page(pmap, pv->pv_va); 2406 if (tpte & ATTR_SW_WIRED) 2407 pmap->pm_stats.wired_count--; 2408 if ((tpte & ATTR_AF) != 0) 2409 vm_page_aflag_set(m, PGA_REFERENCED); 2410 2411 /* 2412 * Update the vm_page_t clean and reference bits. 2413 */ 2414 if (pmap_page_dirty(tpte)) 2415 vm_page_dirty(m); 2416 pmap_unuse_l3(pmap, pv->pv_va, tpde, &free); 2417 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2418 m->md.pv_gen++; 2419 free_pv_entry(pmap, pv); 2420 PMAP_UNLOCK(pmap); 2421 } 2422 vm_page_aflag_clear(m, PGA_WRITEABLE); 2423 rw_wunlock(lock); 2424 pmap_free_zero_pages(&free); 2425} 2426 2427/* 2428 * Set the physical protection on the 2429 * specified range of this map as requested. 2430 */ 2431void 2432pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 2433{ 2434 vm_offset_t va, va_next; 2435 pd_entry_t *l0, *l1, *l2; 2436 pt_entry_t *l3p, l3, nbits; 2437 2438 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot)); 2439 if (prot == VM_PROT_NONE) { 2440 pmap_remove(pmap, sva, eva); 2441 return; 2442 } 2443 2444 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) == 2445 (VM_PROT_WRITE | VM_PROT_EXECUTE)) 2446 return; 2447 2448 PMAP_LOCK(pmap); 2449 for (; sva < eva; sva = va_next) { 2450 2451 l0 = pmap_l0(pmap, sva); 2452 if (pmap_load(l0) == 0) { 2453 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 2454 if (va_next < sva) 2455 va_next = eva; 2456 continue; 2457 } 2458 2459 l1 = pmap_l0_to_l1(l0, sva); 2460 if (pmap_load(l1) == 0) { 2461 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 2462 if (va_next < sva) 2463 va_next = eva; 2464 continue; 2465 } 2466 2467 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 2468 if (va_next < sva) 2469 va_next = eva; 2470 2471 l2 = pmap_l1_to_l2(l1, sva); 2472 if (pmap_load(l2) == 0) 2473 continue; 2474 2475 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) { 2476 l3p = pmap_demote_l2(pmap, l2, sva); 2477 if (l3p == NULL) 2478 continue; 2479 } 2480 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 2481 ("pmap_protect: Invalid L2 entry after demotion")); 2482 2483 if (va_next > eva) 2484 va_next = eva; 2485 2486 va = va_next; 2487 for (l3p = pmap_l2_to_l3(l2, sva); sva != va_next; l3p++, 2488 sva += L3_SIZE) { 2489 l3 = pmap_load(l3p); 2490 if (!pmap_l3_valid(l3)) 2491 continue; 2492 2493 nbits = 0; 2494 if ((prot & VM_PROT_WRITE) == 0) { 2495 if ((l3 & ATTR_SW_MANAGED) && 2496 pmap_page_dirty(l3)) { 2497 vm_page_dirty(PHYS_TO_VM_PAGE(l3 & 2498 ~ATTR_MASK)); 2499 } 2500 nbits |= ATTR_AP(ATTR_AP_RO); 2501 } 2502 if ((prot & VM_PROT_EXECUTE) == 0) 2503 nbits |= ATTR_XN; 2504 2505 pmap_set(l3p, nbits); 2506 PTE_SYNC(l3p); 2507 /* XXX: Use pmap_invalidate_range */ 2508 pmap_invalidate_page(pmap, va); 2509 } 2510 } 2511 PMAP_UNLOCK(pmap); 2512 2513 /* TODO: Only invalidate entries we are touching */ 2514 pmap_invalidate_all(pmap); 2515} 2516 2517/* 2518 * Inserts the specified page table page into the specified pmap's collection 2519 * of idle page table pages. Each of a pmap's page table pages is responsible 2520 * for mapping a distinct range of virtual addresses. The pmap's collection is 2521 * ordered by this virtual address range. 2522 */ 2523static __inline int 2524pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 2525{ 2526 2527 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2528 return (vm_radix_insert(&pmap->pm_root, mpte)); 2529} 2530 2531/* 2532 * Removes the page table page mapping the specified virtual address from the 2533 * specified pmap's collection of idle page table pages, and returns it. 2534 * Otherwise, returns NULL if there is no page table page corresponding to the 2535 * specified virtual address. 2536 */ 2537static __inline vm_page_t 2538pmap_remove_pt_page(pmap_t pmap, vm_offset_t va) 2539{ 2540 2541 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2542 return (vm_radix_remove(&pmap->pm_root, pmap_l2_pindex(va))); 2543} 2544 2545/* 2546 * Performs a break-before-make update of a pmap entry. This is needed when 2547 * either promoting or demoting pages to ensure the TLB doesn't get into an 2548 * inconsistent state. 2549 */ 2550static void 2551pmap_update_entry(pmap_t pmap, pd_entry_t *pte, pd_entry_t newpte, 2552 vm_offset_t va, vm_size_t size) 2553{ 2554 register_t intr; 2555 2556 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2557 2558 /* 2559 * Ensure we don't get switched out with the page table in an 2560 * inconsistent state. We also need to ensure no interrupts fire 2561 * as they may make use of an address we are about to invalidate. 2562 */ 2563 intr = intr_disable(); 2564 critical_enter(); 2565 2566 /* Clear the old mapping */ 2567 pmap_load_clear(pte); 2568 PTE_SYNC(pte); 2569 pmap_invalidate_range(pmap, va, va + size); 2570 2571 /* Create the new mapping */ 2572 pmap_load_store(pte, newpte); 2573 PTE_SYNC(pte); 2574 2575 critical_exit(); 2576 intr_restore(intr); 2577} 2578 2579/* 2580 * After promotion from 512 4KB page mappings to a single 2MB page mapping, 2581 * replace the many pv entries for the 4KB page mappings by a single pv entry 2582 * for the 2MB page mapping. 2583 */ 2584static void 2585pmap_pv_promote_l2(pmap_t pmap, vm_offset_t va, vm_paddr_t pa, 2586 struct rwlock **lockp) 2587{ 2588 struct md_page *pvh; 2589 pv_entry_t pv; 2590 vm_offset_t va_last; 2591 vm_page_t m; 2592 2593 KASSERT((pa & L2_OFFSET) == 0, 2594 ("pmap_pv_promote_l2: pa is not 2mpage aligned")); 2595 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa); 2596 2597 /* 2598 * Transfer the first page's pv entry for this mapping to the 2mpage's 2599 * pv list. Aside from avoiding the cost of a call to get_pv_entry(), 2600 * a transfer avoids the possibility that get_pv_entry() calls 2601 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the 2602 * mappings that is being promoted. 2603 */ 2604 m = PHYS_TO_VM_PAGE(pa); 2605 va = va & ~L2_OFFSET; 2606 pv = pmap_pvh_remove(&m->md, pmap, va); 2607 KASSERT(pv != NULL, ("pmap_pv_promote_l2: pv not found")); 2608 pvh = pa_to_pvh(pa); 2609 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2610 pvh->pv_gen++; 2611 /* Free the remaining NPTEPG - 1 pv entries. */ 2612 va_last = va + L2_SIZE - PAGE_SIZE; 2613 do { 2614 m++; 2615 va += PAGE_SIZE; 2616 pmap_pvh_free(&m->md, pmap, va); 2617 } while (va < va_last); 2618} 2619 2620/* 2621 * Tries to promote the 512, contiguous 4KB page mappings that are within a 2622 * single level 2 table entry to a single 2MB page mapping. For promotion 2623 * to occur, two conditions must be met: (1) the 4KB page mappings must map 2624 * aligned, contiguous physical memory and (2) the 4KB page mappings must have 2625 * identical characteristics. 2626 */ 2627static void 2628pmap_promote_l2(pmap_t pmap, pd_entry_t *l2, vm_offset_t va, 2629 struct rwlock **lockp) 2630{ 2631 pt_entry_t *firstl3, *l3, newl2, oldl3, pa; 2632 vm_page_t mpte; 2633 vm_offset_t sva; 2634 2635 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2636 2637 sva = va & ~L2_OFFSET; 2638 firstl3 = pmap_l2_to_l3(l2, sva); 2639 newl2 = pmap_load(firstl3); 2640 2641 /* Check the alingment is valid */ 2642 if (((newl2 & ~ATTR_MASK) & L2_OFFSET) != 0) { 2643 atomic_add_long(&pmap_l2_p_failures, 1); 2644 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 2645 " in pmap %p", va, pmap); 2646 return; 2647 } 2648 2649 pa = newl2 + L2_SIZE - PAGE_SIZE; 2650 for (l3 = firstl3 + NL3PG - 1; l3 > firstl3; l3--) { 2651 oldl3 = pmap_load(l3); 2652 if (oldl3 != pa) { 2653 atomic_add_long(&pmap_l2_p_failures, 1); 2654 CTR2(KTR_PMAP, "pmap_promote_l2: failure for va %#lx" 2655 " in pmap %p", va, pmap); 2656 return; 2657 } 2658 pa -= PAGE_SIZE; 2659 } 2660 2661 /* 2662 * Save the page table page in its current state until the L2 2663 * mapping the superpage is demoted by pmap_demote_l2() or 2664 * destroyed by pmap_remove_l3(). 2665 */ 2666 mpte = PHYS_TO_VM_PAGE(pmap_load(l2) & ~ATTR_MASK); 2667 KASSERT(mpte >= vm_page_array && 2668 mpte < &vm_page_array[vm_page_array_size], 2669 ("pmap_promote_l2: page table page is out of range")); 2670 KASSERT(mpte->pindex == pmap_l2_pindex(va), 2671 ("pmap_promote_l2: page table page's pindex is wrong")); 2672 if (pmap_insert_pt_page(pmap, mpte)) { 2673 atomic_add_long(&pmap_l2_p_failures, 1); 2674 CTR2(KTR_PMAP, 2675 "pmap_promote_l2: failure for va %#lx in pmap %p", va, 2676 pmap); 2677 return; 2678 } 2679 2680 if ((newl2 & ATTR_SW_MANAGED) != 0) 2681 pmap_pv_promote_l2(pmap, va, newl2 & ~ATTR_MASK, lockp); 2682 2683 newl2 &= ~ATTR_DESCR_MASK; 2684 newl2 |= L2_BLOCK; 2685 2686 pmap_update_entry(pmap, l2, newl2, sva, L2_SIZE); 2687 2688 atomic_add_long(&pmap_l2_promotions, 1); 2689 CTR2(KTR_PMAP, "pmap_promote_l2: success for va %#lx in pmap %p", va, 2690 pmap); 2691} 2692 2693/* 2694 * Insert the given physical page (p) at 2695 * the specified virtual address (v) in the 2696 * target physical map with the protection requested. 2697 * 2698 * If specified, the page will be wired down, meaning 2699 * that the related pte can not be reclaimed. 2700 * 2701 * NB: This is the only routine which MAY NOT lazy-evaluate 2702 * or lose information. That is, this routine must actually 2703 * insert this page into the given map NOW. 2704 */ 2705int 2706pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, 2707 u_int flags, int8_t psind __unused) 2708{ 2709 struct rwlock *lock; 2710 pd_entry_t *pde; 2711 pt_entry_t new_l3, orig_l3; 2712 pt_entry_t *l2, *l3; 2713 pv_entry_t pv; 2714 vm_paddr_t opa, pa, l1_pa, l2_pa, l3_pa; 2715 vm_page_t mpte, om, l1_m, l2_m, l3_m; 2716 boolean_t nosleep; 2717 int lvl; 2718 2719 va = trunc_page(va); 2720 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 2721 VM_OBJECT_ASSERT_LOCKED(m->object); 2722 pa = VM_PAGE_TO_PHYS(m); 2723 new_l3 = (pt_entry_t)(pa | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) | 2724 L3_PAGE); 2725 if ((prot & VM_PROT_WRITE) == 0) 2726 new_l3 |= ATTR_AP(ATTR_AP_RO); 2727 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY) 2728 new_l3 |= ATTR_XN; 2729 if ((flags & PMAP_ENTER_WIRED) != 0) 2730 new_l3 |= ATTR_SW_WIRED; 2731 if ((va >> 63) == 0) 2732 new_l3 |= ATTR_AP(ATTR_AP_USER) | ATTR_PXN; 2733 2734 CTR2(KTR_PMAP, "pmap_enter: %.16lx -> %.16lx", va, pa); 2735 2736 mpte = NULL; 2737 2738 lock = NULL; 2739 PMAP_LOCK(pmap); 2740 2741 pde = pmap_pde(pmap, va, &lvl); 2742 if (pde != NULL && lvl == 1) { 2743 l2 = pmap_l1_to_l2(pde, va); 2744 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK && 2745 (l3 = pmap_demote_l2_locked(pmap, l2, va & ~L2_OFFSET, 2746 &lock)) != NULL) { 2747 l3 = &l3[pmap_l3_index(va)]; 2748 if (va < VM_MAXUSER_ADDRESS) { 2749 mpte = PHYS_TO_VM_PAGE( 2750 pmap_load(l2) & ~ATTR_MASK); 2751 mpte->wire_count++; 2752 } 2753 goto havel3; 2754 } 2755 } 2756 2757 if (va < VM_MAXUSER_ADDRESS) { 2758 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0; 2759 mpte = pmap_alloc_l3(pmap, va, nosleep ? NULL : &lock); 2760 if (mpte == NULL && nosleep) { 2761 CTR0(KTR_PMAP, "pmap_enter: mpte == NULL"); 2762 if (lock != NULL) 2763 rw_wunlock(lock); 2764 PMAP_UNLOCK(pmap); 2765 return (KERN_RESOURCE_SHORTAGE); 2766 } 2767 pde = pmap_pde(pmap, va, &lvl); 2768 KASSERT(pde != NULL, 2769 ("pmap_enter: Invalid page entry, va: 0x%lx", va)); 2770 KASSERT(lvl == 2, 2771 ("pmap_enter: Invalid level %d", lvl)); 2772 2773 l3 = pmap_l2_to_l3(pde, va); 2774 } else { 2775 /* 2776 * If we get a level 2 pde it must point to a level 3 entry 2777 * otherwise we will need to create the intermediate tables 2778 */ 2779 if (lvl < 2) { 2780 switch(lvl) { 2781 default: 2782 case -1: 2783 /* Get the l0 pde to update */ 2784 pde = pmap_l0(pmap, va); 2785 KASSERT(pde != NULL, ("...")); 2786 2787 l1_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2788 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2789 VM_ALLOC_ZERO); 2790 if (l1_m == NULL) 2791 panic("pmap_enter: l1 pte_m == NULL"); 2792 if ((l1_m->flags & PG_ZERO) == 0) 2793 pmap_zero_page(l1_m); 2794 2795 l1_pa = VM_PAGE_TO_PHYS(l1_m); 2796 pmap_load_store(pde, l1_pa | L0_TABLE); 2797 PTE_SYNC(pde); 2798 /* FALLTHROUGH */ 2799 case 0: 2800 /* Get the l1 pde to update */ 2801 pde = pmap_l1_to_l2(pde, va); 2802 KASSERT(pde != NULL, ("...")); 2803 2804 l2_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2805 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2806 VM_ALLOC_ZERO); 2807 if (l2_m == NULL) 2808 panic("pmap_enter: l2 pte_m == NULL"); 2809 if ((l2_m->flags & PG_ZERO) == 0) 2810 pmap_zero_page(l2_m); 2811 2812 l2_pa = VM_PAGE_TO_PHYS(l2_m); 2813 pmap_load_store(pde, l2_pa | L1_TABLE); 2814 PTE_SYNC(pde); 2815 /* FALLTHROUGH */ 2816 case 1: 2817 /* Get the l2 pde to update */ 2818 pde = pmap_l1_to_l2(pde, va); 2819 2820 l3_m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2821 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2822 VM_ALLOC_ZERO); 2823 if (l3_m == NULL) 2824 panic("pmap_enter: l3 pte_m == NULL"); 2825 if ((l3_m->flags & PG_ZERO) == 0) 2826 pmap_zero_page(l3_m); 2827 2828 l3_pa = VM_PAGE_TO_PHYS(l3_m); 2829 pmap_load_store(pde, l3_pa | L2_TABLE); 2830 PTE_SYNC(pde); 2831 break; 2832 } 2833 } 2834 l3 = pmap_l2_to_l3(pde, va); 2835 pmap_invalidate_page(pmap, va); 2836 } 2837havel3: 2838 2839 om = NULL; 2840 orig_l3 = pmap_load(l3); 2841 opa = orig_l3 & ~ATTR_MASK; 2842 2843 /* 2844 * Is the specified virtual address already mapped? 2845 */ 2846 if (pmap_l3_valid(orig_l3)) { 2847 /* 2848 * Wiring change, just update stats. We don't worry about 2849 * wiring PT pages as they remain resident as long as there 2850 * are valid mappings in them. Hence, if a user page is wired, 2851 * the PT page will be also. 2852 */ 2853 if ((flags & PMAP_ENTER_WIRED) != 0 && 2854 (orig_l3 & ATTR_SW_WIRED) == 0) 2855 pmap->pm_stats.wired_count++; 2856 else if ((flags & PMAP_ENTER_WIRED) == 0 && 2857 (orig_l3 & ATTR_SW_WIRED) != 0) 2858 pmap->pm_stats.wired_count--; 2859 2860 /* 2861 * Remove the extra PT page reference. 2862 */ 2863 if (mpte != NULL) { 2864 mpte->wire_count--; 2865 KASSERT(mpte->wire_count > 0, 2866 ("pmap_enter: missing reference to page table page," 2867 " va: 0x%lx", va)); 2868 } 2869 2870 /* 2871 * Has the physical page changed? 2872 */ 2873 if (opa == pa) { 2874 /* 2875 * No, might be a protection or wiring change. 2876 */ 2877 if ((orig_l3 & ATTR_SW_MANAGED) != 0) { 2878 new_l3 |= ATTR_SW_MANAGED; 2879 if ((new_l3 & ATTR_AP(ATTR_AP_RW)) == 2880 ATTR_AP(ATTR_AP_RW)) { 2881 vm_page_aflag_set(m, PGA_WRITEABLE); 2882 } 2883 } 2884 goto validate; 2885 } 2886 2887 /* Flush the cache, there might be uncommitted data in it */ 2888 if (pmap_is_current(pmap) && pmap_l3_valid_cacheable(orig_l3)) 2889 cpu_dcache_wb_range(va, L3_SIZE); 2890 } else { 2891 /* 2892 * Increment the counters. 2893 */ 2894 if ((new_l3 & ATTR_SW_WIRED) != 0) 2895 pmap->pm_stats.wired_count++; 2896 pmap_resident_count_inc(pmap, 1); 2897 } 2898 /* 2899 * Enter on the PV list if part of our managed memory. 2900 */ 2901 if ((m->oflags & VPO_UNMANAGED) == 0) { 2902 new_l3 |= ATTR_SW_MANAGED; 2903 pv = get_pv_entry(pmap, &lock); 2904 pv->pv_va = va; 2905 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa); 2906 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2907 m->md.pv_gen++; 2908 if ((new_l3 & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) 2909 vm_page_aflag_set(m, PGA_WRITEABLE); 2910 } 2911 2912 /* 2913 * Update the L3 entry. 2914 */ 2915 if (orig_l3 != 0) { 2916validate: 2917 orig_l3 = pmap_load(l3); 2918 opa = orig_l3 & ~ATTR_MASK; 2919 2920 if (opa != pa) { 2921 pmap_update_entry(pmap, l3, new_l3, va, PAGE_SIZE); 2922 if ((orig_l3 & ATTR_SW_MANAGED) != 0) { 2923 om = PHYS_TO_VM_PAGE(opa); 2924 if (pmap_page_dirty(orig_l3)) 2925 vm_page_dirty(om); 2926 if ((orig_l3 & ATTR_AF) != 0) 2927 vm_page_aflag_set(om, PGA_REFERENCED); 2928 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa); 2929 pmap_pvh_free(&om->md, pmap, va); 2930 if ((om->aflags & PGA_WRITEABLE) != 0 && 2931 TAILQ_EMPTY(&om->md.pv_list) && 2932 ((om->flags & PG_FICTITIOUS) != 0 || 2933 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 2934 vm_page_aflag_clear(om, PGA_WRITEABLE); 2935 } 2936 } else { 2937 pmap_load_store(l3, new_l3); 2938 PTE_SYNC(l3); 2939 pmap_invalidate_page(pmap, va); 2940 if (pmap_page_dirty(orig_l3) && 2941 (orig_l3 & ATTR_SW_MANAGED) != 0) 2942 vm_page_dirty(m); 2943 } 2944 } else { 2945 pmap_load_store(l3, new_l3); 2946 } 2947 2948 PTE_SYNC(l3); 2949 pmap_invalidate_page(pmap, va); 2950 2951 if (pmap != pmap_kernel()) { 2952 if (pmap == &curproc->p_vmspace->vm_pmap && 2953 (prot & VM_PROT_EXECUTE) != 0) 2954 cpu_icache_sync_range(va, PAGE_SIZE); 2955 2956 if ((mpte == NULL || mpte->wire_count == NL3PG) && 2957 pmap_superpages_enabled() && 2958 (m->flags & PG_FICTITIOUS) == 0 && 2959 vm_reserv_level_iffullpop(m) == 0) { 2960 pmap_promote_l2(pmap, pde, va, &lock); 2961 } 2962 } 2963 2964 if (lock != NULL) 2965 rw_wunlock(lock); 2966 PMAP_UNLOCK(pmap); 2967 return (KERN_SUCCESS); 2968} 2969 2970/* 2971 * Maps a sequence of resident pages belonging to the same object. 2972 * The sequence begins with the given page m_start. This page is 2973 * mapped at the given virtual address start. Each subsequent page is 2974 * mapped at a virtual address that is offset from start by the same 2975 * amount as the page is offset from m_start within the object. The 2976 * last page in the sequence is the page with the largest offset from 2977 * m_start that can be mapped at a virtual address less than the given 2978 * virtual address end. Not every virtual page between start and end 2979 * is mapped; only those for which a resident page exists with the 2980 * corresponding offset from m_start are mapped. 2981 */ 2982void 2983pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2984 vm_page_t m_start, vm_prot_t prot) 2985{ 2986 struct rwlock *lock; 2987 vm_offset_t va; 2988 vm_page_t m, mpte; 2989 vm_pindex_t diff, psize; 2990 2991 VM_OBJECT_ASSERT_LOCKED(m_start->object); 2992 2993 psize = atop(end - start); 2994 mpte = NULL; 2995 m = m_start; 2996 lock = NULL; 2997 PMAP_LOCK(pmap); 2998 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2999 va = start + ptoa(diff); 3000 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte, &lock); 3001 m = TAILQ_NEXT(m, listq); 3002 } 3003 if (lock != NULL) 3004 rw_wunlock(lock); 3005 PMAP_UNLOCK(pmap); 3006} 3007 3008/* 3009 * this code makes some *MAJOR* assumptions: 3010 * 1. Current pmap & pmap exists. 3011 * 2. Not wired. 3012 * 3. Read access. 3013 * 4. No page table pages. 3014 * but is *MUCH* faster than pmap_enter... 3015 */ 3016 3017void 3018pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3019{ 3020 struct rwlock *lock; 3021 3022 lock = NULL; 3023 PMAP_LOCK(pmap); 3024 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock); 3025 if (lock != NULL) 3026 rw_wunlock(lock); 3027 PMAP_UNLOCK(pmap); 3028} 3029 3030static vm_page_t 3031pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3032 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp) 3033{ 3034 struct spglist free; 3035 pd_entry_t *pde; 3036 pt_entry_t *l2, *l3; 3037 vm_paddr_t pa; 3038 int lvl; 3039 3040 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3041 (m->oflags & VPO_UNMANAGED) != 0, 3042 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3043 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3044 3045 CTR2(KTR_PMAP, "pmap_enter_quick_locked: %p %lx", pmap, va); 3046 /* 3047 * In the case that a page table page is not 3048 * resident, we are creating it here. 3049 */ 3050 if (va < VM_MAXUSER_ADDRESS) { 3051 vm_pindex_t l2pindex; 3052 3053 /* 3054 * Calculate pagetable page index 3055 */ 3056 l2pindex = pmap_l2_pindex(va); 3057 if (mpte && (mpte->pindex == l2pindex)) { 3058 mpte->wire_count++; 3059 } else { 3060 /* 3061 * Get the l2 entry 3062 */ 3063 pde = pmap_pde(pmap, va, &lvl); 3064 3065 /* 3066 * If the page table page is mapped, we just increment 3067 * the hold count, and activate it. Otherwise, we 3068 * attempt to allocate a page table page. If this 3069 * attempt fails, we don't retry. Instead, we give up. 3070 */ 3071 if (lvl == 1) { 3072 l2 = pmap_l1_to_l2(pde, va); 3073 if ((pmap_load(l2) & ATTR_DESCR_MASK) == 3074 L2_BLOCK) 3075 return (NULL); 3076 } 3077 if (lvl == 2 && pmap_load(pde) != 0) { 3078 mpte = 3079 PHYS_TO_VM_PAGE(pmap_load(pde) & ~ATTR_MASK); 3080 mpte->wire_count++; 3081 } else { 3082 /* 3083 * Pass NULL instead of the PV list lock 3084 * pointer, because we don't intend to sleep. 3085 */ 3086 mpte = _pmap_alloc_l3(pmap, l2pindex, NULL); 3087 if (mpte == NULL) 3088 return (mpte); 3089 } 3090 } 3091 l3 = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte)); 3092 l3 = &l3[pmap_l3_index(va)]; 3093 } else { 3094 mpte = NULL; 3095 pde = pmap_pde(kernel_pmap, va, &lvl); 3096 KASSERT(pde != NULL, 3097 ("pmap_enter_quick_locked: Invalid page entry, va: 0x%lx", 3098 va)); 3099 KASSERT(lvl == 2, 3100 ("pmap_enter_quick_locked: Invalid level %d", lvl)); 3101 l3 = pmap_l2_to_l3(pde, va); 3102 } 3103 3104 if (pmap_load(l3) != 0) { 3105 if (mpte != NULL) { 3106 mpte->wire_count--; 3107 mpte = NULL; 3108 } 3109 return (mpte); 3110 } 3111 3112 /* 3113 * Enter on the PV list if part of our managed memory. 3114 */ 3115 if ((m->oflags & VPO_UNMANAGED) == 0 && 3116 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) { 3117 if (mpte != NULL) { 3118 SLIST_INIT(&free); 3119 if (pmap_unwire_l3(pmap, va, mpte, &free)) { 3120 pmap_invalidate_page(pmap, va); 3121 pmap_free_zero_pages(&free); 3122 } 3123 mpte = NULL; 3124 } 3125 return (mpte); 3126 } 3127 3128 /* 3129 * Increment counters 3130 */ 3131 pmap_resident_count_inc(pmap, 1); 3132 3133 pa = VM_PAGE_TO_PHYS(m) | ATTR_DEFAULT | ATTR_IDX(m->md.pv_memattr) | 3134 ATTR_AP(ATTR_AP_RO) | L3_PAGE; 3135 if ((prot & VM_PROT_EXECUTE) == 0 || m->md.pv_memattr == DEVICE_MEMORY) 3136 pa |= ATTR_XN; 3137 else if (va < VM_MAXUSER_ADDRESS) 3138 pa |= ATTR_PXN; 3139 3140 /* 3141 * Now validate mapping with RO protection 3142 */ 3143 if ((m->oflags & VPO_UNMANAGED) == 0) 3144 pa |= ATTR_SW_MANAGED; 3145 pmap_load_store(l3, pa); 3146 PTE_SYNC(l3); 3147 pmap_invalidate_page(pmap, va); 3148 return (mpte); 3149} 3150 3151/* 3152 * This code maps large physical mmap regions into the 3153 * processor address space. Note that some shortcuts 3154 * are taken, but the code works. 3155 */ 3156void 3157pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3158 vm_pindex_t pindex, vm_size_t size) 3159{ 3160 3161 VM_OBJECT_ASSERT_WLOCKED(object); 3162 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3163 ("pmap_object_init_pt: non-device object")); 3164} 3165 3166/* 3167 * Clear the wired attribute from the mappings for the specified range of 3168 * addresses in the given pmap. Every valid mapping within that range 3169 * must have the wired attribute set. In contrast, invalid mappings 3170 * cannot have the wired attribute set, so they are ignored. 3171 * 3172 * The wired attribute of the page table entry is not a hardware feature, 3173 * so there is no need to invalidate any TLB entries. 3174 */ 3175void 3176pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 3177{ 3178 vm_offset_t va_next; 3179 pd_entry_t *l0, *l1, *l2; 3180 pt_entry_t *l3; 3181 3182 PMAP_LOCK(pmap); 3183 for (; sva < eva; sva = va_next) { 3184 l0 = pmap_l0(pmap, sva); 3185 if (pmap_load(l0) == 0) { 3186 va_next = (sva + L0_SIZE) & ~L0_OFFSET; 3187 if (va_next < sva) 3188 va_next = eva; 3189 continue; 3190 } 3191 3192 l1 = pmap_l0_to_l1(l0, sva); 3193 if (pmap_load(l1) == 0) { 3194 va_next = (sva + L1_SIZE) & ~L1_OFFSET; 3195 if (va_next < sva) 3196 va_next = eva; 3197 continue; 3198 } 3199 3200 va_next = (sva + L2_SIZE) & ~L2_OFFSET; 3201 if (va_next < sva) 3202 va_next = eva; 3203 3204 l2 = pmap_l1_to_l2(l1, sva); 3205 if (pmap_load(l2) == 0) 3206 continue; 3207 3208 if ((pmap_load(l2) & ATTR_DESCR_MASK) == L2_BLOCK) { 3209 l3 = pmap_demote_l2(pmap, l2, sva); 3210 if (l3 == NULL) 3211 continue; 3212 } 3213 KASSERT((pmap_load(l2) & ATTR_DESCR_MASK) == L2_TABLE, 3214 ("pmap_unwire: Invalid l2 entry after demotion")); 3215 3216 if (va_next > eva) 3217 va_next = eva; 3218 for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++, 3219 sva += L3_SIZE) { 3220 if (pmap_load(l3) == 0) 3221 continue; 3222 if ((pmap_load(l3) & ATTR_SW_WIRED) == 0) 3223 panic("pmap_unwire: l3 %#jx is missing " 3224 "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3)); 3225 3226 /* 3227 * PG_W must be cleared atomically. Although the pmap 3228 * lock synchronizes access to PG_W, another processor 3229 * could be setting PG_M and/or PG_A concurrently. 3230 */ 3231 atomic_clear_long(l3, ATTR_SW_WIRED); 3232 pmap->pm_stats.wired_count--; 3233 } 3234 } 3235 PMAP_UNLOCK(pmap); 3236} 3237 3238/* 3239 * Copy the range specified by src_addr/len 3240 * from the source map to the range dst_addr/len 3241 * in the destination map. 3242 * 3243 * This routine is only advisory and need not do anything. 3244 */ 3245 3246void 3247pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 3248 vm_offset_t src_addr) 3249{ 3250} 3251 3252/* 3253 * pmap_zero_page zeros the specified hardware page by mapping 3254 * the page into KVM and using bzero to clear its contents. 3255 */ 3256void 3257pmap_zero_page(vm_page_t m) 3258{ 3259 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 3260 3261 pagezero((void *)va); 3262} 3263 3264/* 3265 * pmap_zero_page_area zeros the specified hardware page by mapping 3266 * the page into KVM and using bzero to clear its contents. 3267 * 3268 * off and size may not cover an area beyond a single hardware page. 3269 */ 3270void 3271pmap_zero_page_area(vm_page_t m, int off, int size) 3272{ 3273 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 3274 3275 if (off == 0 && size == PAGE_SIZE) 3276 pagezero((void *)va); 3277 else 3278 bzero((char *)va + off, size); 3279} 3280 3281/* 3282 * pmap_zero_page_idle zeros the specified hardware page by mapping 3283 * the page into KVM and using bzero to clear its contents. This 3284 * is intended to be called from the vm_pagezero process only and 3285 * outside of Giant. 3286 */ 3287void 3288pmap_zero_page_idle(vm_page_t m) 3289{ 3290 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)); 3291 3292 pagezero((void *)va); 3293} 3294 3295/* 3296 * pmap_copy_page copies the specified (machine independent) 3297 * page by mapping the page into virtual memory and using 3298 * bcopy to copy the page, one machine dependent page at a 3299 * time. 3300 */ 3301void 3302pmap_copy_page(vm_page_t msrc, vm_page_t mdst) 3303{ 3304 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc)); 3305 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst)); 3306 3307 pagecopy((void *)src, (void *)dst); 3308} 3309 3310int unmapped_buf_allowed = 1; 3311 3312void 3313pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 3314 vm_offset_t b_offset, int xfersize) 3315{ 3316 void *a_cp, *b_cp; 3317 vm_page_t m_a, m_b; 3318 vm_paddr_t p_a, p_b; 3319 vm_offset_t a_pg_offset, b_pg_offset; 3320 int cnt; 3321 3322 while (xfersize > 0) { 3323 a_pg_offset = a_offset & PAGE_MASK; 3324 m_a = ma[a_offset >> PAGE_SHIFT]; 3325 p_a = m_a->phys_addr; 3326 b_pg_offset = b_offset & PAGE_MASK; 3327 m_b = mb[b_offset >> PAGE_SHIFT]; 3328 p_b = m_b->phys_addr; 3329 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 3330 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 3331 if (__predict_false(!PHYS_IN_DMAP(p_a))) { 3332 panic("!DMAP a %lx", p_a); 3333 } else { 3334 a_cp = (char *)PHYS_TO_DMAP(p_a) + a_pg_offset; 3335 } 3336 if (__predict_false(!PHYS_IN_DMAP(p_b))) { 3337 panic("!DMAP b %lx", p_b); 3338 } else { 3339 b_cp = (char *)PHYS_TO_DMAP(p_b) + b_pg_offset; 3340 } 3341 bcopy(a_cp, b_cp, cnt); 3342 a_offset += cnt; 3343 b_offset += cnt; 3344 xfersize -= cnt; 3345 } 3346} 3347 3348vm_offset_t 3349pmap_quick_enter_page(vm_page_t m) 3350{ 3351 3352 return (PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m))); 3353} 3354 3355void 3356pmap_quick_remove_page(vm_offset_t addr) 3357{ 3358} 3359 3360/* 3361 * Returns true if the pmap's pv is one of the first 3362 * 16 pvs linked to from this page. This count may 3363 * be changed upwards or downwards in the future; it 3364 * is only necessary that true be returned for a small 3365 * subset of pmaps for proper page aging. 3366 */ 3367boolean_t 3368pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 3369{ 3370 struct md_page *pvh; 3371 struct rwlock *lock; 3372 pv_entry_t pv; 3373 int loops = 0; 3374 boolean_t rv; 3375 3376 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3377 ("pmap_page_exists_quick: page %p is not managed", m)); 3378 rv = FALSE; 3379 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3380 rw_rlock(lock); 3381 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3382 if (PV_PMAP(pv) == pmap) { 3383 rv = TRUE; 3384 break; 3385 } 3386 loops++; 3387 if (loops >= 16) 3388 break; 3389 } 3390 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 3391 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3392 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 3393 if (PV_PMAP(pv) == pmap) { 3394 rv = TRUE; 3395 break; 3396 } 3397 loops++; 3398 if (loops >= 16) 3399 break; 3400 } 3401 } 3402 rw_runlock(lock); 3403 return (rv); 3404} 3405 3406/* 3407 * pmap_page_wired_mappings: 3408 * 3409 * Return the number of managed mappings to the given physical page 3410 * that are wired. 3411 */ 3412int 3413pmap_page_wired_mappings(vm_page_t m) 3414{ 3415 struct rwlock *lock; 3416 struct md_page *pvh; 3417 pmap_t pmap; 3418 pt_entry_t *pte; 3419 pv_entry_t pv; 3420 int count, lvl, md_gen, pvh_gen; 3421 3422 if ((m->oflags & VPO_UNMANAGED) != 0) 3423 return (0); 3424 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3425 rw_rlock(lock); 3426restart: 3427 count = 0; 3428 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3429 pmap = PV_PMAP(pv); 3430 if (!PMAP_TRYLOCK(pmap)) { 3431 md_gen = m->md.pv_gen; 3432 rw_runlock(lock); 3433 PMAP_LOCK(pmap); 3434 rw_rlock(lock); 3435 if (md_gen != m->md.pv_gen) { 3436 PMAP_UNLOCK(pmap); 3437 goto restart; 3438 } 3439 } 3440 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3441 if (pte != NULL && (pmap_load(pte) & ATTR_SW_WIRED) != 0) 3442 count++; 3443 PMAP_UNLOCK(pmap); 3444 } 3445 if ((m->flags & PG_FICTITIOUS) == 0) { 3446 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3447 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 3448 pmap = PV_PMAP(pv); 3449 if (!PMAP_TRYLOCK(pmap)) { 3450 md_gen = m->md.pv_gen; 3451 pvh_gen = pvh->pv_gen; 3452 rw_runlock(lock); 3453 PMAP_LOCK(pmap); 3454 rw_rlock(lock); 3455 if (md_gen != m->md.pv_gen || 3456 pvh_gen != pvh->pv_gen) { 3457 PMAP_UNLOCK(pmap); 3458 goto restart; 3459 } 3460 } 3461 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3462 if (pte != NULL && 3463 (pmap_load(pte) & ATTR_SW_WIRED) != 0) 3464 count++; 3465 PMAP_UNLOCK(pmap); 3466 } 3467 } 3468 rw_runlock(lock); 3469 return (count); 3470} 3471 3472/* 3473 * Destroy all managed, non-wired mappings in the given user-space 3474 * pmap. This pmap cannot be active on any processor besides the 3475 * caller. 3476 * 3477 * This function cannot be applied to the kernel pmap. Moreover, it 3478 * is not intended for general use. It is only to be used during 3479 * process termination. Consequently, it can be implemented in ways 3480 * that make it faster than pmap_remove(). First, it can more quickly 3481 * destroy mappings by iterating over the pmap's collection of PV 3482 * entries, rather than searching the page table. Second, it doesn't 3483 * have to test and clear the page table entries atomically, because 3484 * no processor is currently accessing the user address space. In 3485 * particular, a page table entry's dirty bit won't change state once 3486 * this function starts. 3487 */ 3488void 3489pmap_remove_pages(pmap_t pmap) 3490{ 3491 pd_entry_t *pde; 3492 pt_entry_t *pte, tpte; 3493 struct spglist free; 3494 vm_page_t m, ml3, mt; 3495 pv_entry_t pv; 3496 struct md_page *pvh; 3497 struct pv_chunk *pc, *npc; 3498 struct rwlock *lock; 3499 int64_t bit; 3500 uint64_t inuse, bitmask; 3501 int allfree, field, freed, idx, lvl; 3502 vm_paddr_t pa; 3503 3504 lock = NULL; 3505 3506 SLIST_INIT(&free); 3507 PMAP_LOCK(pmap); 3508 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 3509 allfree = 1; 3510 freed = 0; 3511 for (field = 0; field < _NPCM; field++) { 3512 inuse = ~pc->pc_map[field] & pc_freemask[field]; 3513 while (inuse != 0) { 3514 bit = ffsl(inuse) - 1; 3515 bitmask = 1UL << bit; 3516 idx = field * 64 + bit; 3517 pv = &pc->pc_pventry[idx]; 3518 inuse &= ~bitmask; 3519 3520 pde = pmap_pde(pmap, pv->pv_va, &lvl); 3521 KASSERT(pde != NULL, 3522 ("Attempting to remove an unmapped page")); 3523 3524 switch(lvl) { 3525 case 1: 3526 pte = pmap_l1_to_l2(pde, pv->pv_va); 3527 tpte = pmap_load(pte); 3528 KASSERT((tpte & ATTR_DESCR_MASK) == 3529 L2_BLOCK, 3530 ("Attempting to remove an invalid " 3531 "block: %lx", tpte)); 3532 tpte = pmap_load(pte); 3533 break; 3534 case 2: 3535 pte = pmap_l2_to_l3(pde, pv->pv_va); 3536 tpte = pmap_load(pte); 3537 KASSERT((tpte & ATTR_DESCR_MASK) == 3538 L3_PAGE, 3539 ("Attempting to remove an invalid " 3540 "page: %lx", tpte)); 3541 break; 3542 default: 3543 panic( 3544 "Invalid page directory level: %d", 3545 lvl); 3546 } 3547 3548/* 3549 * We cannot remove wired pages from a process' mapping at this time 3550 */ 3551 if (tpte & ATTR_SW_WIRED) { 3552 allfree = 0; 3553 continue; 3554 } 3555 3556 pa = tpte & ~ATTR_MASK; 3557 3558 m = PHYS_TO_VM_PAGE(pa); 3559 KASSERT(m->phys_addr == pa, 3560 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 3561 m, (uintmax_t)m->phys_addr, 3562 (uintmax_t)tpte)); 3563 3564 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 3565 m < &vm_page_array[vm_page_array_size], 3566 ("pmap_remove_pages: bad pte %#jx", 3567 (uintmax_t)tpte)); 3568 3569 if (pmap_is_current(pmap)) { 3570 if (lvl == 2 && 3571 pmap_l3_valid_cacheable(tpte)) { 3572 cpu_dcache_wb_range(pv->pv_va, 3573 L3_SIZE); 3574 } else if (lvl == 1 && 3575 pmap_pte_valid_cacheable(tpte)) { 3576 cpu_dcache_wb_range(pv->pv_va, 3577 L2_SIZE); 3578 } 3579 } 3580 pmap_load_clear(pte); 3581 PTE_SYNC(pte); 3582 pmap_invalidate_page(pmap, pv->pv_va); 3583 3584 /* 3585 * Update the vm_page_t clean/reference bits. 3586 */ 3587 if ((tpte & ATTR_AP_RW_BIT) == 3588 ATTR_AP(ATTR_AP_RW)) { 3589 switch (lvl) { 3590 case 1: 3591 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 3592 vm_page_dirty(m); 3593 break; 3594 case 2: 3595 vm_page_dirty(m); 3596 break; 3597 } 3598 } 3599 3600 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m); 3601 3602 /* Mark free */ 3603 pc->pc_map[field] |= bitmask; 3604 switch (lvl) { 3605 case 1: 3606 pmap_resident_count_dec(pmap, 3607 L2_SIZE / PAGE_SIZE); 3608 pvh = pa_to_pvh(tpte & ~ATTR_MASK); 3609 TAILQ_REMOVE(&pvh->pv_list, pv,pv_next); 3610 pvh->pv_gen++; 3611 if (TAILQ_EMPTY(&pvh->pv_list)) { 3612 for (mt = m; mt < &m[L2_SIZE / PAGE_SIZE]; mt++) 3613 if ((mt->aflags & PGA_WRITEABLE) != 0 && 3614 TAILQ_EMPTY(&mt->md.pv_list)) 3615 vm_page_aflag_clear(mt, PGA_WRITEABLE); 3616 } 3617 ml3 = pmap_remove_pt_page(pmap, 3618 pv->pv_va); 3619 if (ml3 != NULL) { 3620 pmap_resident_count_dec(pmap,1); 3621 KASSERT(ml3->wire_count == NL3PG, 3622 ("pmap_remove_pages: l3 page wire count error")); 3623 ml3->wire_count = 0; 3624 pmap_add_delayed_free_list(ml3, 3625 &free, FALSE); 3626 atomic_subtract_int( 3627 &vm_cnt.v_wire_count, 1); 3628 } 3629 break; 3630 case 2: 3631 pmap_resident_count_dec(pmap, 1); 3632 TAILQ_REMOVE(&m->md.pv_list, pv, 3633 pv_next); 3634 m->md.pv_gen++; 3635 if ((m->aflags & PGA_WRITEABLE) != 0 && 3636 TAILQ_EMPTY(&m->md.pv_list) && 3637 (m->flags & PG_FICTITIOUS) == 0) { 3638 pvh = pa_to_pvh( 3639 VM_PAGE_TO_PHYS(m)); 3640 if (TAILQ_EMPTY(&pvh->pv_list)) 3641 vm_page_aflag_clear(m, 3642 PGA_WRITEABLE); 3643 } 3644 break; 3645 } 3646 pmap_unuse_l3(pmap, pv->pv_va, pmap_load(pde), 3647 &free); 3648 freed++; 3649 } 3650 } 3651 PV_STAT(atomic_add_long(&pv_entry_frees, freed)); 3652 PV_STAT(atomic_add_int(&pv_entry_spare, freed)); 3653 PV_STAT(atomic_subtract_long(&pv_entry_count, freed)); 3654 if (allfree) { 3655 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 3656 free_pv_chunk(pc); 3657 } 3658 } 3659 pmap_invalidate_all(pmap); 3660 if (lock != NULL) 3661 rw_wunlock(lock); 3662 PMAP_UNLOCK(pmap); 3663 pmap_free_zero_pages(&free); 3664} 3665 3666/* 3667 * This is used to check if a page has been accessed or modified. As we 3668 * don't have a bit to see if it has been modified we have to assume it 3669 * has been if the page is read/write. 3670 */ 3671static boolean_t 3672pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified) 3673{ 3674 struct rwlock *lock; 3675 pv_entry_t pv; 3676 struct md_page *pvh; 3677 pt_entry_t *pte, mask, value; 3678 pmap_t pmap; 3679 int lvl, md_gen, pvh_gen; 3680 boolean_t rv; 3681 3682 rv = FALSE; 3683 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3684 rw_rlock(lock); 3685restart: 3686 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3687 pmap = PV_PMAP(pv); 3688 if (!PMAP_TRYLOCK(pmap)) { 3689 md_gen = m->md.pv_gen; 3690 rw_runlock(lock); 3691 PMAP_LOCK(pmap); 3692 rw_rlock(lock); 3693 if (md_gen != m->md.pv_gen) { 3694 PMAP_UNLOCK(pmap); 3695 goto restart; 3696 } 3697 } 3698 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3699 KASSERT(lvl == 3, 3700 ("pmap_page_test_mappings: Invalid level %d", lvl)); 3701 mask = 0; 3702 value = 0; 3703 if (modified) { 3704 mask |= ATTR_AP_RW_BIT; 3705 value |= ATTR_AP(ATTR_AP_RW); 3706 } 3707 if (accessed) { 3708 mask |= ATTR_AF | ATTR_DESCR_MASK; 3709 value |= ATTR_AF | L3_PAGE; 3710 } 3711 rv = (pmap_load(pte) & mask) == value; 3712 PMAP_UNLOCK(pmap); 3713 if (rv) 3714 goto out; 3715 } 3716 if ((m->flags & PG_FICTITIOUS) == 0) { 3717 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3718 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 3719 pmap = PV_PMAP(pv); 3720 if (!PMAP_TRYLOCK(pmap)) { 3721 md_gen = m->md.pv_gen; 3722 pvh_gen = pvh->pv_gen; 3723 rw_runlock(lock); 3724 PMAP_LOCK(pmap); 3725 rw_rlock(lock); 3726 if (md_gen != m->md.pv_gen || 3727 pvh_gen != pvh->pv_gen) { 3728 PMAP_UNLOCK(pmap); 3729 goto restart; 3730 } 3731 } 3732 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3733 KASSERT(lvl == 2, 3734 ("pmap_page_test_mappings: Invalid level %d", lvl)); 3735 mask = 0; 3736 value = 0; 3737 if (modified) { 3738 mask |= ATTR_AP_RW_BIT; 3739 value |= ATTR_AP(ATTR_AP_RW); 3740 } 3741 if (accessed) { 3742 mask |= ATTR_AF | ATTR_DESCR_MASK; 3743 value |= ATTR_AF | L2_BLOCK; 3744 } 3745 rv = (pmap_load(pte) & mask) == value; 3746 PMAP_UNLOCK(pmap); 3747 if (rv) 3748 goto out; 3749 } 3750 } 3751out: 3752 rw_runlock(lock); 3753 return (rv); 3754} 3755 3756/* 3757 * pmap_is_modified: 3758 * 3759 * Return whether or not the specified physical page was modified 3760 * in any physical maps. 3761 */ 3762boolean_t 3763pmap_is_modified(vm_page_t m) 3764{ 3765 3766 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3767 ("pmap_is_modified: page %p is not managed", m)); 3768 3769 /* 3770 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3771 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 3772 * is clear, no PTEs can have PG_M set. 3773 */ 3774 VM_OBJECT_ASSERT_WLOCKED(m->object); 3775 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3776 return (FALSE); 3777 return (pmap_page_test_mappings(m, FALSE, TRUE)); 3778} 3779 3780/* 3781 * pmap_is_prefaultable: 3782 * 3783 * Return whether or not the specified virtual address is eligible 3784 * for prefault. 3785 */ 3786boolean_t 3787pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 3788{ 3789 pt_entry_t *pte; 3790 boolean_t rv; 3791 int lvl; 3792 3793 rv = FALSE; 3794 PMAP_LOCK(pmap); 3795 pte = pmap_pte(pmap, addr, &lvl); 3796 if (pte != NULL && pmap_load(pte) != 0) { 3797 rv = TRUE; 3798 } 3799 PMAP_UNLOCK(pmap); 3800 return (rv); 3801} 3802 3803/* 3804 * pmap_is_referenced: 3805 * 3806 * Return whether or not the specified physical page was referenced 3807 * in any physical maps. 3808 */ 3809boolean_t 3810pmap_is_referenced(vm_page_t m) 3811{ 3812 3813 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3814 ("pmap_is_referenced: page %p is not managed", m)); 3815 return (pmap_page_test_mappings(m, TRUE, FALSE)); 3816} 3817 3818/* 3819 * Clear the write and modified bits in each of the given page's mappings. 3820 */ 3821void 3822pmap_remove_write(vm_page_t m) 3823{ 3824 struct md_page *pvh; 3825 pmap_t pmap; 3826 struct rwlock *lock; 3827 pv_entry_t next_pv, pv; 3828 pt_entry_t oldpte, *pte; 3829 vm_offset_t va; 3830 int lvl, md_gen, pvh_gen; 3831 3832 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3833 ("pmap_remove_write: page %p is not managed", m)); 3834 3835 /* 3836 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 3837 * set by another thread while the object is locked. Thus, 3838 * if PGA_WRITEABLE is clear, no page table entries need updating. 3839 */ 3840 VM_OBJECT_ASSERT_WLOCKED(m->object); 3841 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 3842 return; 3843 lock = VM_PAGE_TO_PV_LIST_LOCK(m); 3844 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : 3845 pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3846retry_pv_loop: 3847 rw_wlock(lock); 3848 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 3849 pmap = PV_PMAP(pv); 3850 if (!PMAP_TRYLOCK(pmap)) { 3851 pvh_gen = pvh->pv_gen; 3852 rw_wunlock(lock); 3853 PMAP_LOCK(pmap); 3854 rw_wlock(lock); 3855 if (pvh_gen != pvh->pv_gen) { 3856 PMAP_UNLOCK(pmap); 3857 rw_wunlock(lock); 3858 goto retry_pv_loop; 3859 } 3860 } 3861 va = pv->pv_va; 3862 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3863 if ((pmap_load(pte) & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) 3864 pmap_demote_l2_locked(pmap, pte, va & ~L2_OFFSET, 3865 &lock); 3866 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 3867 ("inconsistent pv lock %p %p for page %p", 3868 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 3869 PMAP_UNLOCK(pmap); 3870 } 3871 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 3872 pmap = PV_PMAP(pv); 3873 if (!PMAP_TRYLOCK(pmap)) { 3874 pvh_gen = pvh->pv_gen; 3875 md_gen = m->md.pv_gen; 3876 rw_wunlock(lock); 3877 PMAP_LOCK(pmap); 3878 rw_wlock(lock); 3879 if (pvh_gen != pvh->pv_gen || 3880 md_gen != m->md.pv_gen) { 3881 PMAP_UNLOCK(pmap); 3882 rw_wunlock(lock); 3883 goto retry_pv_loop; 3884 } 3885 } 3886 pte = pmap_pte(pmap, pv->pv_va, &lvl); 3887retry: 3888 oldpte = pmap_load(pte); 3889 if ((oldpte & ATTR_AP_RW_BIT) == ATTR_AP(ATTR_AP_RW)) { 3890 if (!atomic_cmpset_long(pte, oldpte, 3891 oldpte | ATTR_AP(ATTR_AP_RO))) 3892 goto retry; 3893 if ((oldpte & ATTR_AF) != 0) 3894 vm_page_dirty(m); 3895 pmap_invalidate_page(pmap, pv->pv_va); 3896 } 3897 PMAP_UNLOCK(pmap); 3898 } 3899 rw_wunlock(lock); 3900 vm_page_aflag_clear(m, PGA_WRITEABLE); 3901} 3902 3903static __inline boolean_t 3904safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte) 3905{ 3906 3907 return (FALSE); 3908} 3909 3910#define PMAP_TS_REFERENCED_MAX 5 3911 3912/* 3913 * pmap_ts_referenced: 3914 * 3915 * Return a count of reference bits for a page, clearing those bits. 3916 * It is not necessary for every reference bit to be cleared, but it 3917 * is necessary that 0 only be returned when there are truly no 3918 * reference bits set. 3919 * 3920 * XXX: The exact number of bits to check and clear is a matter that 3921 * should be tested and standardized at some point in the future for 3922 * optimal aging of shared pages. 3923 */ 3924int 3925pmap_ts_referenced(vm_page_t m) 3926{ 3927 struct md_page *pvh; 3928 pv_entry_t pv, pvf; 3929 pmap_t pmap; 3930 struct rwlock *lock; 3931 pd_entry_t *pde, tpde; 3932 pt_entry_t *pte, tpte; 3933 pt_entry_t *l3; 3934 vm_offset_t va; 3935 vm_paddr_t pa; 3936 int cleared, md_gen, not_cleared, lvl, pvh_gen; 3937 struct spglist free; 3938 bool demoted; 3939 3940 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3941 ("pmap_ts_referenced: page %p is not managed", m)); 3942 SLIST_INIT(&free); 3943 cleared = 0; 3944 pa = VM_PAGE_TO_PHYS(m); 3945 lock = PHYS_TO_PV_LIST_LOCK(pa); 3946 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa); 3947 rw_wlock(lock); 3948retry: 3949 not_cleared = 0; 3950 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 3951 goto small_mappings; 3952 pv = pvf; 3953 do { 3954 if (pvf == NULL) 3955 pvf = pv; 3956 pmap = PV_PMAP(pv); 3957 if (!PMAP_TRYLOCK(pmap)) { 3958 pvh_gen = pvh->pv_gen; 3959 rw_wunlock(lock); 3960 PMAP_LOCK(pmap); 3961 rw_wlock(lock); 3962 if (pvh_gen != pvh->pv_gen) { 3963 PMAP_UNLOCK(pmap); 3964 goto retry; 3965 } 3966 } 3967 va = pv->pv_va; 3968 pde = pmap_pde(pmap, pv->pv_va, &lvl); 3969 KASSERT(pde != NULL, ("pmap_ts_referenced: no l1 table found")); 3970 KASSERT(lvl == 1, 3971 ("pmap_ts_referenced: invalid pde level %d", lvl)); 3972 tpde = pmap_load(pde); 3973 KASSERT((tpde & ATTR_DESCR_MASK) == L1_TABLE, 3974 ("pmap_ts_referenced: found an invalid l1 table")); 3975 pte = pmap_l1_to_l2(pde, pv->pv_va); 3976 tpte = pmap_load(pte); 3977 if ((tpte & ATTR_AF) != 0) { 3978 /* 3979 * Since this reference bit is shared by 512 4KB 3980 * pages, it should not be cleared every time it is 3981 * tested. Apply a simple "hash" function on the 3982 * physical page number, the virtual superpage number, 3983 * and the pmap address to select one 4KB page out of 3984 * the 512 on which testing the reference bit will 3985 * result in clearing that reference bit. This 3986 * function is designed to avoid the selection of the 3987 * same 4KB page for every 2MB page mapping. 3988 * 3989 * On demotion, a mapping that hasn't been referenced 3990 * is simply destroyed. To avoid the possibility of a 3991 * subsequent page fault on a demoted wired mapping, 3992 * always leave its reference bit set. Moreover, 3993 * since the superpage is wired, the current state of 3994 * its reference bit won't affect page replacement. 3995 */ 3996 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> L2_SHIFT) ^ 3997 (uintptr_t)pmap) & (Ln_ENTRIES - 1)) == 0 && 3998 (tpte & ATTR_SW_WIRED) == 0) { 3999 if (safe_to_clear_referenced(pmap, tpte)) { 4000 /* 4001 * TODO: We don't handle the access 4002 * flag at all. We need to be able 4003 * to set it in the exception handler. 4004 */ 4005 panic("ARM64TODO: " 4006 "safe_to_clear_referenced\n"); 4007 } else if (pmap_demote_l2_locked(pmap, pte, 4008 pv->pv_va, &lock) != NULL) { 4009 demoted = true; 4010 va += VM_PAGE_TO_PHYS(m) - 4011 (tpte & ~ATTR_MASK); 4012 l3 = pmap_l2_to_l3(pte, va); 4013 pmap_remove_l3(pmap, l3, va, 4014 pmap_load(pte), NULL, &lock); 4015 } else 4016 demoted = true; 4017 4018 if (demoted) { 4019 /* 4020 * The superpage mapping was removed 4021 * entirely and therefore 'pv' is no 4022 * longer valid. 4023 */ 4024 if (pvf == pv) 4025 pvf = NULL; 4026 pv = NULL; 4027 } 4028 cleared++; 4029 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 4030 ("inconsistent pv lock %p %p for page %p", 4031 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 4032 } else 4033 not_cleared++; 4034 } 4035 PMAP_UNLOCK(pmap); 4036 /* Rotate the PV list if it has more than one entry. */ 4037 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) { 4038 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4039 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 4040 pvh->pv_gen++; 4041 } 4042 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX) 4043 goto out; 4044 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 4045small_mappings: 4046 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 4047 goto out; 4048 pv = pvf; 4049 do { 4050 if (pvf == NULL) 4051 pvf = pv; 4052 pmap = PV_PMAP(pv); 4053 if (!PMAP_TRYLOCK(pmap)) { 4054 pvh_gen = pvh->pv_gen; 4055 md_gen = m->md.pv_gen; 4056 rw_wunlock(lock); 4057 PMAP_LOCK(pmap); 4058 rw_wlock(lock); 4059 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) { 4060 PMAP_UNLOCK(pmap); 4061 goto retry; 4062 } 4063 } 4064 pde = pmap_pde(pmap, pv->pv_va, &lvl); 4065 KASSERT(pde != NULL, ("pmap_ts_referenced: no l2 table found")); 4066 KASSERT(lvl == 2, 4067 ("pmap_ts_referenced: invalid pde level %d", lvl)); 4068 tpde = pmap_load(pde); 4069 KASSERT((tpde & ATTR_DESCR_MASK) == L2_TABLE, 4070 ("pmap_ts_referenced: found an invalid l2 table")); 4071 pte = pmap_l2_to_l3(pde, pv->pv_va); 4072 tpte = pmap_load(pte); 4073 if ((tpte & ATTR_AF) != 0) { 4074 if (safe_to_clear_referenced(pmap, tpte)) { 4075 /* 4076 * TODO: We don't handle the access flag 4077 * at all. We need to be able to set it in 4078 * the exception handler. 4079 */ 4080 panic("ARM64TODO: safe_to_clear_referenced\n"); 4081 } else if ((tpte & ATTR_SW_WIRED) == 0) { 4082 /* 4083 * Wired pages cannot be paged out so 4084 * doing accessed bit emulation for 4085 * them is wasted effort. We do the 4086 * hard work for unwired pages only. 4087 */ 4088 pmap_remove_l3(pmap, pte, pv->pv_va, tpde, 4089 &free, &lock); 4090 pmap_invalidate_page(pmap, pv->pv_va); 4091 cleared++; 4092 if (pvf == pv) 4093 pvf = NULL; 4094 pv = NULL; 4095 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m), 4096 ("inconsistent pv lock %p %p for page %p", 4097 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m)); 4098 } else 4099 not_cleared++; 4100 } 4101 PMAP_UNLOCK(pmap); 4102 /* Rotate the PV list if it has more than one entry. */ 4103 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) { 4104 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4105 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4106 m->md.pv_gen++; 4107 } 4108 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared + 4109 not_cleared < PMAP_TS_REFERENCED_MAX); 4110out: 4111 rw_wunlock(lock); 4112 pmap_free_zero_pages(&free); 4113 return (cleared + not_cleared); 4114} 4115 4116/* 4117 * Apply the given advice to the specified range of addresses within the 4118 * given pmap. Depending on the advice, clear the referenced and/or 4119 * modified flags in each mapping and set the mapped page's dirty field. 4120 */ 4121void 4122pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4123{ 4124} 4125 4126/* 4127 * Clear the modify bits on the specified physical page. 4128 */ 4129void 4130pmap_clear_modify(vm_page_t m) 4131{ 4132 4133 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4134 ("pmap_clear_modify: page %p is not managed", m)); 4135 VM_OBJECT_ASSERT_WLOCKED(m->object); 4136 KASSERT(!vm_page_xbusied(m), 4137 ("pmap_clear_modify: page %p is exclusive busied", m)); 4138 4139 /* 4140 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 4141 * If the object containing the page is locked and the page is not 4142 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4143 */ 4144 if ((m->aflags & PGA_WRITEABLE) == 0) 4145 return; 4146 4147 /* ARM64TODO: We lack support for tracking if a page is modified */ 4148} 4149 4150void * 4151pmap_mapbios(vm_paddr_t pa, vm_size_t size) 4152{ 4153 4154 return ((void *)PHYS_TO_DMAP(pa)); 4155} 4156 4157void 4158pmap_unmapbios(vm_paddr_t pa, vm_size_t size) 4159{ 4160} 4161 4162/* 4163 * Sets the memory attribute for the specified page. 4164 */ 4165void 4166pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 4167{ 4168 4169 m->md.pv_memattr = ma; 4170 4171 /* 4172 * If "m" is a normal page, update its direct mapping. This update 4173 * can be relied upon to perform any cache operations that are 4174 * required for data coherence. 4175 */ 4176 if ((m->flags & PG_FICTITIOUS) == 0 && 4177 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE, 4178 m->md.pv_memattr) != 0) 4179 panic("memory attribute change on the direct map failed"); 4180} 4181 4182/* 4183 * Changes the specified virtual address range's memory type to that given by 4184 * the parameter "mode". The specified virtual address range must be 4185 * completely contained within either the direct map or the kernel map. If 4186 * the virtual address range is contained within the kernel map, then the 4187 * memory type for each of the corresponding ranges of the direct map is also 4188 * changed. (The corresponding ranges of the direct map are those ranges that 4189 * map the same physical pages as the specified virtual address range.) These 4190 * changes to the direct map are necessary because Intel describes the 4191 * behavior of their processors as "undefined" if two or more mappings to the 4192 * same physical page have different memory types. 4193 * 4194 * Returns zero if the change completed successfully, and either EINVAL or 4195 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 4196 * of the virtual address range was not mapped, and ENOMEM is returned if 4197 * there was insufficient memory available to complete the change. In the 4198 * latter case, the memory type may have been changed on some part of the 4199 * virtual address range or the direct map. 4200 */ 4201static int 4202pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 4203{ 4204 int error; 4205 4206 PMAP_LOCK(kernel_pmap); 4207 error = pmap_change_attr_locked(va, size, mode); 4208 PMAP_UNLOCK(kernel_pmap); 4209 return (error); 4210} 4211 4212static int 4213pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode) 4214{ 4215 vm_offset_t base, offset, tmpva; 4216 pt_entry_t l3, *pte, *newpte; 4217 int lvl; 4218 4219 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED); 4220 base = trunc_page(va); 4221 offset = va & PAGE_MASK; 4222 size = round_page(offset + size); 4223 4224 if (!VIRT_IN_DMAP(base)) 4225 return (EINVAL); 4226 4227 for (tmpva = base; tmpva < base + size; ) { 4228 pte = pmap_pte(kernel_pmap, va, &lvl); 4229 if (pte == NULL) 4230 return (EINVAL); 4231 4232 if ((pmap_load(pte) & ATTR_IDX_MASK) == ATTR_IDX(mode)) { 4233 /* 4234 * We already have the correct attribute, 4235 * ignore this entry. 4236 */ 4237 switch (lvl) { 4238 default: 4239 panic("Invalid DMAP table level: %d\n", lvl); 4240 case 1: 4241 tmpva = (tmpva & ~L1_OFFSET) + L1_SIZE; 4242 break; 4243 case 2: 4244 tmpva = (tmpva & ~L2_OFFSET) + L2_SIZE; 4245 break; 4246 case 3: 4247 tmpva += PAGE_SIZE; 4248 break; 4249 } 4250 } else { 4251 /* 4252 * Split the entry to an level 3 table, then 4253 * set the new attribute. 4254 */ 4255 switch (lvl) { 4256 default: 4257 panic("Invalid DMAP table level: %d\n", lvl); 4258 case 1: 4259 newpte = pmap_demote_l1(kernel_pmap, pte, 4260 tmpva & ~L1_OFFSET); 4261 if (newpte == NULL) 4262 return (EINVAL); 4263 pte = pmap_l1_to_l2(pte, tmpva); 4264 case 2: 4265 newpte = pmap_demote_l2(kernel_pmap, pte, 4266 tmpva & ~L2_OFFSET); 4267 if (newpte == NULL) 4268 return (EINVAL); 4269 pte = pmap_l2_to_l3(pte, tmpva); 4270 case 3: 4271 /* Update the entry */ 4272 l3 = pmap_load(pte); 4273 l3 &= ~ATTR_IDX_MASK; 4274 l3 |= ATTR_IDX(mode); 4275 if (mode == DEVICE_MEMORY) 4276 l3 |= ATTR_XN; 4277 4278 pmap_update_entry(kernel_pmap, pte, l3, tmpva, 4279 PAGE_SIZE); 4280 4281 /* 4282 * If moving to a non-cacheable entry flush 4283 * the cache. 4284 */ 4285 if (mode == VM_MEMATTR_UNCACHEABLE) 4286 cpu_dcache_wbinv_range(tmpva, L3_SIZE); 4287 4288 break; 4289 } 4290 tmpva += PAGE_SIZE; 4291 } 4292 } 4293 4294 return (0); 4295} 4296 4297/* 4298 * Create an L2 table to map all addresses within an L1 mapping. 4299 */ 4300static pt_entry_t * 4301pmap_demote_l1(pmap_t pmap, pt_entry_t *l1, vm_offset_t va) 4302{ 4303 pt_entry_t *l2, newl2, oldl1; 4304 vm_offset_t tmpl1; 4305 vm_paddr_t l2phys, phys; 4306 vm_page_t ml2; 4307 int i; 4308 4309 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4310 oldl1 = pmap_load(l1); 4311 KASSERT((oldl1 & ATTR_DESCR_MASK) == L1_BLOCK, 4312 ("pmap_demote_l1: Demoting a non-block entry")); 4313 KASSERT((va & L1_OFFSET) == 0, 4314 ("pmap_demote_l1: Invalid virtual address %#lx", va)); 4315 KASSERT((oldl1 & ATTR_SW_MANAGED) == 0, 4316 ("pmap_demote_l1: Level 1 table shouldn't be managed")); 4317 4318 tmpl1 = 0; 4319 if (va <= (vm_offset_t)l1 && va + L1_SIZE > (vm_offset_t)l1) { 4320 tmpl1 = kva_alloc(PAGE_SIZE); 4321 if (tmpl1 == 0) 4322 return (NULL); 4323 } 4324 4325 if ((ml2 = vm_page_alloc(NULL, 0, VM_ALLOC_INTERRUPT | 4326 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 4327 CTR2(KTR_PMAP, "pmap_demote_l1: failure for va %#lx" 4328 " in pmap %p", va, pmap); 4329 return (NULL); 4330 } 4331 4332 l2phys = VM_PAGE_TO_PHYS(ml2); 4333 l2 = (pt_entry_t *)PHYS_TO_DMAP(l2phys); 4334 4335 /* Address the range points at */ 4336 phys = oldl1 & ~ATTR_MASK; 4337 /* The attributed from the old l1 table to be copied */ 4338 newl2 = oldl1 & ATTR_MASK; 4339 4340 /* Create the new entries */ 4341 for (i = 0; i < Ln_ENTRIES; i++) { 4342 l2[i] = newl2 | phys; 4343 phys += L2_SIZE; 4344 } 4345 cpu_dcache_wb_range((vm_offset_t)l2, PAGE_SIZE); 4346 KASSERT(l2[0] == ((oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK), 4347 ("Invalid l2 page (%lx != %lx)", l2[0], 4348 (oldl1 & ~ATTR_DESCR_MASK) | L2_BLOCK)); 4349 4350 if (tmpl1 != 0) { 4351 pmap_kenter(tmpl1, PAGE_SIZE, 4352 DMAP_TO_PHYS((vm_offset_t)l1) & ~L3_OFFSET, CACHED_MEMORY); 4353 l1 = (pt_entry_t *)(tmpl1 + ((vm_offset_t)l1 & PAGE_MASK)); 4354 } 4355 4356 pmap_update_entry(pmap, l1, l2phys | L1_TABLE, va, PAGE_SIZE); 4357 4358 if (tmpl1 != 0) { 4359 pmap_kremove(tmpl1); 4360 kva_free(tmpl1, PAGE_SIZE); 4361 } 4362 4363 return (l2); 4364} 4365 4366/* 4367 * Create an L3 table to map all addresses within an L2 mapping. 4368 */ 4369static pt_entry_t * 4370pmap_demote_l2_locked(pmap_t pmap, pt_entry_t *l2, vm_offset_t va, 4371 struct rwlock **lockp) 4372{ 4373 pt_entry_t *l3, newl3, oldl2; 4374 vm_offset_t tmpl2; 4375 vm_paddr_t l3phys, phys; 4376 vm_page_t ml3; 4377 int i; 4378 4379 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 4380 l3 = NULL; 4381 oldl2 = pmap_load(l2); 4382 KASSERT((oldl2 & ATTR_DESCR_MASK) == L2_BLOCK, 4383 ("pmap_demote_l2: Demoting a non-block entry")); 4384 KASSERT((va & L2_OFFSET) == 0, 4385 ("pmap_demote_l2: Invalid virtual address %#lx", va)); 4386 4387 tmpl2 = 0; 4388 if (va <= (vm_offset_t)l2 && va + L2_SIZE > (vm_offset_t)l2) { 4389 tmpl2 = kva_alloc(PAGE_SIZE); 4390 if (tmpl2 == 0) 4391 return (NULL); 4392 } 4393 4394 if ((ml3 = pmap_remove_pt_page(pmap, va)) == NULL) { 4395 ml3 = vm_page_alloc(NULL, pmap_l2_pindex(va), 4396 (VIRT_IN_DMAP(va) ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) | 4397 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED); 4398 if (ml3 == NULL) { 4399 CTR2(KTR_PMAP, "pmap_demote_l2: failure for va %#lx" 4400 " in pmap %p", va, pmap); 4401 goto fail; 4402 } 4403 if (va < VM_MAXUSER_ADDRESS) 4404 pmap_resident_count_inc(pmap, 1); 4405 } 4406 4407 l3phys = VM_PAGE_TO_PHYS(ml3); 4408 l3 = (pt_entry_t *)PHYS_TO_DMAP(l3phys); 4409 4410 /* Address the range points at */ 4411 phys = oldl2 & ~ATTR_MASK; 4412 /* The attributed from the old l2 table to be copied */ 4413 newl3 = (oldl2 & (ATTR_MASK & ~ATTR_DESCR_MASK)) | L3_PAGE; 4414 4415 /* 4416 * If the page table page is new, initialize it. 4417 */ 4418 if (ml3->wire_count == 1) { 4419 for (i = 0; i < Ln_ENTRIES; i++) { 4420 l3[i] = newl3 | phys; 4421 phys += L3_SIZE; 4422 } 4423 cpu_dcache_wb_range((vm_offset_t)l3, PAGE_SIZE); 4424 } 4425 KASSERT(l3[0] == ((oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE), 4426 ("Invalid l3 page (%lx != %lx)", l3[0], 4427 (oldl2 & ~ATTR_DESCR_MASK) | L3_PAGE)); 4428 4429 /* 4430 * Map the temporary page so we don't lose access to the l2 table. 4431 */ 4432 if (tmpl2 != 0) { 4433 pmap_kenter(tmpl2, PAGE_SIZE, 4434 DMAP_TO_PHYS((vm_offset_t)l2) & ~L3_OFFSET, CACHED_MEMORY); 4435 l2 = (pt_entry_t *)(tmpl2 + ((vm_offset_t)l2 & PAGE_MASK)); 4436 } 4437 4438 /* 4439 * The spare PV entries must be reserved prior to demoting the 4440 * mapping, that is, prior to changing the PDE. Otherwise, the state 4441 * of the L2 and the PV lists will be inconsistent, which can result 4442 * in reclaim_pv_chunk() attempting to remove a PV entry from the 4443 * wrong PV list and pmap_pv_demote_l2() failing to find the expected 4444 * PV entry for the 2MB page mapping that is being demoted. 4445 */ 4446 if ((oldl2 & ATTR_SW_MANAGED) != 0) 4447 reserve_pv_entries(pmap, Ln_ENTRIES - 1, lockp); 4448 4449 pmap_update_entry(pmap, l2, l3phys | L2_TABLE, va, PAGE_SIZE); 4450 4451 /* 4452 * Demote the PV entry. 4453 */ 4454 if ((oldl2 & ATTR_SW_MANAGED) != 0) 4455 pmap_pv_demote_l2(pmap, va, oldl2 & ~ATTR_MASK, lockp); 4456 4457 atomic_add_long(&pmap_l2_demotions, 1); 4458 CTR3(KTR_PMAP, "pmap_demote_l2: success for va %#lx" 4459 " in pmap %p %lx", va, pmap, l3[0]); 4460 4461fail: 4462 if (tmpl2 != 0) { 4463 pmap_kremove(tmpl2); 4464 kva_free(tmpl2, PAGE_SIZE); 4465 } 4466 4467 return (l3); 4468 4469} 4470 4471static pt_entry_t * 4472pmap_demote_l2(pmap_t pmap, pt_entry_t *l2, vm_offset_t va) 4473{ 4474 struct rwlock *lock; 4475 pt_entry_t *l3; 4476 4477 lock = NULL; 4478 l3 = pmap_demote_l2_locked(pmap, l2, va, &lock); 4479 if (lock != NULL) 4480 rw_wunlock(lock); 4481 return (l3); 4482} 4483 4484/* 4485 * perform the pmap work for mincore 4486 */ 4487int 4488pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 4489{ 4490 pd_entry_t *l1p, l1; 4491 pd_entry_t *l2p, l2; 4492 pt_entry_t *l3p, l3; 4493 vm_paddr_t pa; 4494 bool managed; 4495 int val; 4496 4497 PMAP_LOCK(pmap); 4498retry: 4499 pa = 0; 4500 val = 0; 4501 managed = false; 4502 4503 l1p = pmap_l1(pmap, addr); 4504 if (l1p == NULL) /* No l1 */ 4505 goto done; 4506 4507 l1 = pmap_load(l1p); 4508 if ((l1 & ATTR_DESCR_MASK) == L1_INVAL) 4509 goto done; 4510 4511 if ((l1 & ATTR_DESCR_MASK) == L1_BLOCK) { 4512 pa = (l1 & ~ATTR_MASK) | (addr & L1_OFFSET); 4513 managed = (l1 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED; 4514 val = MINCORE_SUPER | MINCORE_INCORE; 4515 if (pmap_page_dirty(l1)) 4516 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4517 if ((l1 & ATTR_AF) == ATTR_AF) 4518 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4519 goto done; 4520 } 4521 4522 l2p = pmap_l1_to_l2(l1p, addr); 4523 if (l2p == NULL) /* No l2 */ 4524 goto done; 4525 4526 l2 = pmap_load(l2p); 4527 if ((l2 & ATTR_DESCR_MASK) == L2_INVAL) 4528 goto done; 4529 4530 if ((l2 & ATTR_DESCR_MASK) == L2_BLOCK) { 4531 pa = (l2 & ~ATTR_MASK) | (addr & L2_OFFSET); 4532 managed = (l2 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED; 4533 val = MINCORE_SUPER | MINCORE_INCORE; 4534 if (pmap_page_dirty(l2)) 4535 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4536 if ((l2 & ATTR_AF) == ATTR_AF) 4537 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4538 goto done; 4539 } 4540 4541 l3p = pmap_l2_to_l3(l2p, addr); 4542 if (l3p == NULL) /* No l3 */ 4543 goto done; 4544 4545 l3 = pmap_load(l2p); 4546 if ((l3 & ATTR_DESCR_MASK) == L3_INVAL) 4547 goto done; 4548 4549 if ((l3 & ATTR_DESCR_MASK) == L3_PAGE) { 4550 pa = (l3 & ~ATTR_MASK) | (addr & L3_OFFSET); 4551 managed = (l3 & ATTR_SW_MANAGED) == ATTR_SW_MANAGED; 4552 val = MINCORE_INCORE; 4553 if (pmap_page_dirty(l3)) 4554 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 4555 if ((l3 & ATTR_AF) == ATTR_AF) 4556 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 4557 } 4558 4559done: 4560 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 4561 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 4562 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 4563 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 4564 goto retry; 4565 } else 4566 PA_UNLOCK_COND(*locked_pa); 4567 PMAP_UNLOCK(pmap); 4568 4569 return (val); 4570} 4571 4572void 4573pmap_activate(struct thread *td) 4574{ 4575 pmap_t pmap; 4576 4577 critical_enter(); 4578 pmap = vmspace_pmap(td->td_proc->p_vmspace); 4579 td->td_pcb->pcb_l0addr = vtophys(pmap->pm_l0); 4580 __asm __volatile("msr ttbr0_el1, %0" : : "r"(td->td_pcb->pcb_l0addr)); 4581 pmap_invalidate_all(pmap); 4582 critical_exit(); 4583} 4584 4585void 4586pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz) 4587{ 4588 4589 if (va >= VM_MIN_KERNEL_ADDRESS) { 4590 cpu_icache_sync_range(va, sz); 4591 } else { 4592 u_int len, offset; 4593 vm_paddr_t pa; 4594 4595 /* Find the length of data in this page to flush */ 4596 offset = va & PAGE_MASK; 4597 len = imin(PAGE_SIZE - offset, sz); 4598 4599 while (sz != 0) { 4600 /* Extract the physical address & find it in the DMAP */ 4601 pa = pmap_extract(pmap, va); 4602 if (pa != 0) 4603 cpu_icache_sync_range(PHYS_TO_DMAP(pa), len); 4604 4605 /* Move to the next page */ 4606 sz -= len; 4607 va += len; 4608 /* Set the length for the next iteration */ 4609 len = imin(PAGE_SIZE, sz); 4610 } 4611 } 4612} 4613 4614int 4615pmap_fault(pmap_t pmap, uint64_t esr, uint64_t far) 4616{ 4617#ifdef SMP 4618 uint64_t par; 4619#endif 4620 4621 switch (ESR_ELx_EXCEPTION(esr)) { 4622 case EXCP_DATA_ABORT_L: 4623 case EXCP_DATA_ABORT: 4624 break; 4625 default: 4626 return (KERN_FAILURE); 4627 } 4628 4629#ifdef SMP 4630 PMAP_LOCK(pmap); 4631 switch (esr & ISS_DATA_DFSC_MASK) { 4632 case ISS_DATA_DFSC_TF_L0: 4633 case ISS_DATA_DFSC_TF_L1: 4634 case ISS_DATA_DFSC_TF_L2: 4635 case ISS_DATA_DFSC_TF_L3: 4636 /* Ask the MMU to check the address */ 4637 if (pmap == kernel_pmap) 4638 par = arm64_address_translate_s1e1r(far); 4639 else 4640 par = arm64_address_translate_s1e0r(far); 4641 4642 /* 4643 * If the translation was successful the address was invalid 4644 * due to a break-before-make sequence. We can unlock and 4645 * return success to the trap handler. 4646 */ 4647 if (PAR_SUCCESS(par)) { 4648 PMAP_UNLOCK(pmap); 4649 return (KERN_SUCCESS); 4650 } 4651 break; 4652 default: 4653 break; 4654 } 4655 PMAP_UNLOCK(pmap); 4656#endif 4657 4658 return (KERN_FAILURE); 4659} 4660 4661/* 4662 * Increase the starting virtual address of the given mapping if a 4663 * different alignment might result in more superpage mappings. 4664 */ 4665void 4666pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 4667 vm_offset_t *addr, vm_size_t size) 4668{ 4669 vm_offset_t superpage_offset; 4670 4671 if (size < L2_SIZE) 4672 return; 4673 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 4674 offset += ptoa(object->pg_color); 4675 superpage_offset = offset & L2_OFFSET; 4676 if (size - ((L2_SIZE - superpage_offset) & L2_OFFSET) < L2_SIZE || 4677 (*addr & L2_OFFSET) == superpage_offset) 4678 return; 4679 if ((*addr & L2_OFFSET) < superpage_offset) 4680 *addr = (*addr & ~L2_OFFSET) + superpage_offset; 4681 else 4682 *addr = ((*addr + L2_OFFSET) & ~L2_OFFSET) + superpage_offset; 4683} 4684 4685/** 4686 * Get the kernel virtual address of a set of physical pages. If there are 4687 * physical addresses not covered by the DMAP perform a transient mapping 4688 * that will be removed when calling pmap_unmap_io_transient. 4689 * 4690 * \param page The pages the caller wishes to obtain the virtual 4691 * address on the kernel memory map. 4692 * \param vaddr On return contains the kernel virtual memory address 4693 * of the pages passed in the page parameter. 4694 * \param count Number of pages passed in. 4695 * \param can_fault TRUE if the thread using the mapped pages can take 4696 * page faults, FALSE otherwise. 4697 * 4698 * \returns TRUE if the caller must call pmap_unmap_io_transient when 4699 * finished or FALSE otherwise. 4700 * 4701 */ 4702boolean_t 4703pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 4704 boolean_t can_fault) 4705{ 4706 vm_paddr_t paddr; 4707 boolean_t needs_mapping; 4708 int error, i; 4709 4710 /* 4711 * Allocate any KVA space that we need, this is done in a separate 4712 * loop to prevent calling vmem_alloc while pinned. 4713 */ 4714 needs_mapping = FALSE; 4715 for (i = 0; i < count; i++) { 4716 paddr = VM_PAGE_TO_PHYS(page[i]); 4717 if (__predict_false(!PHYS_IN_DMAP(paddr))) { 4718 error = vmem_alloc(kernel_arena, PAGE_SIZE, 4719 M_BESTFIT | M_WAITOK, &vaddr[i]); 4720 KASSERT(error == 0, ("vmem_alloc failed: %d", error)); 4721 needs_mapping = TRUE; 4722 } else { 4723 vaddr[i] = PHYS_TO_DMAP(paddr); 4724 } 4725 } 4726 4727 /* Exit early if everything is covered by the DMAP */ 4728 if (!needs_mapping) 4729 return (FALSE); 4730 4731 if (!can_fault) 4732 sched_pin(); 4733 for (i = 0; i < count; i++) { 4734 paddr = VM_PAGE_TO_PHYS(page[i]); 4735 if (!PHYS_IN_DMAP(paddr)) { 4736 panic( 4737 "pmap_map_io_transient: TODO: Map out of DMAP data"); 4738 } 4739 } 4740 4741 return (needs_mapping); 4742} 4743 4744void 4745pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count, 4746 boolean_t can_fault) 4747{ 4748 vm_paddr_t paddr; 4749 int i; 4750 4751 if (!can_fault) 4752 sched_unpin(); 4753 for (i = 0; i < count; i++) { 4754 paddr = VM_PAGE_TO_PHYS(page[i]); 4755 if (!PHYS_IN_DMAP(paddr)) { 4756 panic("ARM64TODO: pmap_unmap_io_transient: Unmap data"); 4757 } 4758 } 4759} 4760