avila_machdep.c revision 236828
1/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ 2 3/*- 4 * Copyright (c) 1994-1998 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * machdep.c 40 * 41 * Machine dependant functions for kernel setup 42 * 43 * This file needs a lot of work. 44 * 45 * Created : 17/09/94 46 */ 47 48#include <sys/cdefs.h> 49__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/avila_machdep.c 236828 2012-06-10 01:13:04Z andrew $"); 50 51#define _ARM32_BUS_DMA_PRIVATE 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysproto.h> 55#include <sys/signalvar.h> 56#include <sys/imgact.h> 57#include <sys/kernel.h> 58#include <sys/ktr.h> 59#include <sys/linker.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/mutex.h> 63#include <sys/pcpu.h> 64#include <sys/proc.h> 65#include <sys/ptrace.h> 66#include <sys/cons.h> 67#include <sys/bio.h> 68#include <sys/bus.h> 69#include <sys/buf.h> 70#include <sys/exec.h> 71#include <sys/kdb.h> 72#include <sys/msgbuf.h> 73#include <machine/reg.h> 74#include <machine/cpu.h> 75 76#include <vm/vm.h> 77#include <vm/pmap.h> 78#include <vm/vm_object.h> 79#include <vm/vm_page.h> 80#include <vm/vm_pager.h> 81#include <vm/vm_map.h> 82#include <vm/vnode_pager.h> 83#include <machine/pmap.h> 84#include <machine/vmparam.h> 85#include <machine/pcb.h> 86#include <machine/undefined.h> 87#include <machine/machdep.h> 88#include <machine/metadata.h> 89#include <machine/armreg.h> 90#include <machine/bus.h> 91#include <sys/reboot.h> 92 93#include <arm/xscale/ixp425/ixp425reg.h> 94#include <arm/xscale/ixp425/ixp425var.h> 95 96/* kernel text starts where we were loaded at boot */ 97#define KERNEL_TEXT_OFF (KERNPHYSADDR - PHYSADDR) 98#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF) 99#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF) 100 101#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 102#define KERNEL_PT_IO 1 103#define KERNEL_PT_IO_NUM 3 104#define KERNEL_PT_BEFOREKERN KERNEL_PT_IO + KERNEL_PT_IO_NUM 105#define KERNEL_PT_AFKERNEL KERNEL_PT_BEFOREKERN + 1 /* L2 table for mapping after kernel */ 106#define KERNEL_PT_AFKERNEL_NUM 9 107 108/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 109#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 110 111/* Define various stack sizes in pages */ 112#define IRQ_STACK_SIZE 1 113#define ABT_STACK_SIZE 1 114#define UND_STACK_SIZE 1 115 116extern u_int data_abort_handler_address; 117extern u_int prefetch_abort_handler_address; 118extern u_int undefined_handler_address; 119 120struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 121 122extern void *_end; 123 124extern int *end; 125 126struct pcpu __pcpu; 127struct pcpu *pcpup = &__pcpu; 128 129/* Physical and virtual addresses for some global pages */ 130 131vm_paddr_t phys_avail[10]; 132vm_paddr_t dump_avail[4]; 133vm_offset_t physical_pages; 134 135struct pv_addr systempage; 136struct pv_addr msgbufpv; 137struct pv_addr irqstack; 138struct pv_addr undstack; 139struct pv_addr abtstack; 140struct pv_addr kernelstack; 141struct pv_addr minidataclean; 142 143/* Static device mappings. */ 144static const struct pmap_devmap ixp425_devmap[] = { 145 /* Physical/Virtual address for I/O space */ 146 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 147 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 148 149 /* Expansion Bus */ 150 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 151 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 152 153 /* CFI Flash on the Expansion Bus */ 154 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 155 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 156 157 /* IXP425 PCI Configuration */ 158 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 159 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 160 161 /* SDRAM Controller */ 162 { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, 163 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 164 165 /* PCI Memory Space */ 166 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 167 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 168 169 /* Q-Mgr Memory Space */ 170 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 171 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 172 173 { 0 }, 174}; 175 176/* Static device mappings. */ 177static const struct pmap_devmap ixp435_devmap[] = { 178 /* Physical/Virtual address for I/O space */ 179 { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 180 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 181 182 { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 183 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 184 185 /* IXP425 PCI Configuration */ 186 { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 187 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 188 189 /* DDRII Controller NB: mapped same place as IXP425 */ 190 { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, 191 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 192 193 /* PCI Memory Space */ 194 { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 195 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 196 197 /* Q-Mgr Memory Space */ 198 { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 199 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 200 201 /* CFI Flash on the Expansion Bus */ 202 { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 203 IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 204 205 /* USB1 Memory Space */ 206 { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, 207 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 208 /* USB2 Memory Space */ 209 { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, 210 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 211 212 /* GPS Memory Space */ 213 { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, 214 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 215 216 /* RS485 Memory Space */ 217 { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, 218 VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 219 220 { 0 } 221}; 222 223extern vm_offset_t xscale_cache_clean_addr; 224 225void * 226initarm(struct arm_boot_params *abp) 227{ 228#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1)) 229#define next_page(a) next_chunk2(a,PAGE_SIZE) 230 struct pv_addr kernel_l1pt; 231 struct pv_addr dpcpu; 232 int loop, i; 233 u_int l1pagetable; 234 vm_offset_t freemempos; 235 vm_offset_t freemem_pt; 236 vm_offset_t afterkern; 237 vm_offset_t freemem_after; 238 vm_offset_t lastaddr; 239 uint32_t memsize; 240 241 set_cpufuncs(); /* NB: sets cputype */ 242 lastaddr = fake_preload_metadata(); 243 pcpu_init(pcpup, 0, sizeof(struct pcpu)); 244 PCPU_SET(curthread, &thread0); 245 246 /* Do basic tuning, hz etc */ 247 init_param1(); 248 249 /* 250 * We allocate memory downwards from where we were loaded 251 * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS 252 * entries in the L2 page table. Past that we re-align the 253 * allocation boundary so later data structures (stacks, etc) 254 * can be mapped with different attributes (write-back vs 255 * write-through). Note this leaves a gap for expansion 256 * (or might be repurposed). 257 */ 258 freemempos = KERNPHYSADDR; 259 260 /* macros to simplify initial memory allocation */ 261#define alloc_pages(var, np) do { \ 262 freemempos -= (np * PAGE_SIZE); \ 263 (var) = freemempos; \ 264 /* NB: this works because locore maps PA=VA */ \ 265 memset((char *)(var), 0, ((np) * PAGE_SIZE)); \ 266} while (0) 267#define valloc_pages(var, np) do { \ 268 alloc_pages((var).pv_pa, (np)); \ 269 (var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \ 270} while (0) 271 272 /* force L1 page table alignment */ 273 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 274 freemempos -= PAGE_SIZE; 275 /* allocate contiguous L1 page table */ 276 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 277 /* now allocate L2 page tables; they are linked to L1 below */ 278 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 279 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 280 valloc_pages(kernel_pt_table[loop], 281 L2_TABLE_SIZE / PAGE_SIZE); 282 } else { 283 kernel_pt_table[loop].pv_pa = freemempos + 284 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 285 L2_TABLE_SIZE_REAL; 286 kernel_pt_table[loop].pv_va = 287 kernel_pt_table[loop].pv_pa + 288 (KERNVIRTADDR - KERNPHYSADDR); 289 } 290 } 291 freemem_pt = freemempos; /* base of allocated pt's */ 292 293 /* 294 * Re-align allocation boundary so we can map the area 295 * write-back instead of write-through for the stacks and 296 * related structures allocated below. 297 */ 298 freemempos = PHYSADDR + 0x100000; 299 /* 300 * Allocate a page for the system page mapped to V0x00000000 301 * This page will just contain the system vectors and can be 302 * shared by all processes. 303 */ 304 valloc_pages(systempage, 1); 305 306 /* Allocate dynamic per-cpu area. */ 307 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 308 dpcpu_init((void *)dpcpu.pv_va, 0); 309 310 /* Allocate stacks for all modes */ 311 valloc_pages(irqstack, IRQ_STACK_SIZE); 312 valloc_pages(abtstack, ABT_STACK_SIZE); 313 valloc_pages(undstack, UND_STACK_SIZE); 314 valloc_pages(kernelstack, KSTACK_PAGES); 315 alloc_pages(minidataclean.pv_pa, 1); 316 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 317#ifdef ARM_USE_SMALL_ALLOC 318 freemempos -= PAGE_SIZE; 319 freemem_pt = trunc_page(freemem_pt); 320 freemem_after = freemempos - ((freemem_pt - (PHYSADDR + 0x100000)) / 321 PAGE_SIZE) * sizeof(struct arm_small_page); 322 arm_add_smallalloc_pages( 323 (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)), 324 (void *)0xc0100000, 325 freemem_pt - (PHYSADDR + 0x100000), 1); 326 freemem_after -= ((freemem_after - (PHYSADDR + 0x1000)) / PAGE_SIZE) * 327 sizeof(struct arm_small_page); 328 arm_add_smallalloc_pages( 329 (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)), 330 (void *)0xc0001000, 331 trunc_page(freemem_after) - (PHYSADDR + 0x1000), 0); 332 freemempos = trunc_page(freemem_after); 333 freemempos -= PAGE_SIZE; 334#endif 335 336 /* 337 * Now construct the L1 page table. First map the L2 338 * page tables into the L1 so we can replace L1 mappings 339 * later on if necessary 340 */ 341 l1pagetable = kernel_l1pt.pv_va; 342 343 /* Map the L2 pages tables in the L1 page table */ 344 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), 345 &kernel_pt_table[KERNEL_PT_SYS]); 346 pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE, 347 &kernel_pt_table[KERNEL_PT_IO]); 348 pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE, 349 &kernel_pt_table[KERNEL_PT_IO + 1]); 350 pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE, 351 &kernel_pt_table[KERNEL_PT_IO + 2]); 352 pmap_link_l2pt(l1pagetable, KERNBASE, 353 &kernel_pt_table[KERNEL_PT_BEFOREKERN]); 354 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000, 355 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 356 pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000, 357 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 358 pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS, 359 next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE), 360 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 361 freemem_after = next_page((int)lastaddr); 362 afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE)); 363 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 364 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, 365 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 366 } 367 pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, 368 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 369 370#ifdef ARM_USE_SMALL_ALLOC 371 if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) { 372 arm_add_smallalloc_pages((void *)(freemem_after), 373 (void*)(freemem_after + PAGE_SIZE), 374 afterkern - (freemem_after + PAGE_SIZE), 0); 375 376 } 377#endif 378 379 /* Map the Mini-Data cache clean area. */ 380 xscale_setup_minidata(l1pagetable, afterkern, 381 minidataclean.pv_pa); 382 383 /* Map the vector page. */ 384 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 385 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 386 if (cpu_is_ixp43x()) 387 pmap_devmap_bootstrap(l1pagetable, ixp435_devmap); 388 else 389 pmap_devmap_bootstrap(l1pagetable, ixp425_devmap); 390 /* 391 * Give the XScale global cache clean code an appropriately 392 * sized chunk of unmapped VA space starting at 0xff000000 393 * (our device mappings end before this address). 394 */ 395 xscale_cache_clean_addr = 0xff000000U; 396 397 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 398 setttb(kernel_l1pt.pv_pa); 399 cpu_tlb_flushID(); 400 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 401 402 /* 403 * Pages were allocated during the secondary bootstrap for the 404 * stacks for different CPU modes. 405 * We must now set the r13 registers in the different CPU modes to 406 * point to these stacks. 407 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 408 * of the stack memory. 409 */ 410 set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE*PAGE_SIZE); 411 set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE*PAGE_SIZE); 412 set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE*PAGE_SIZE); 413 414 /* 415 * We must now clean the cache again.... 416 * Cleaning may be done by reading new data to displace any 417 * dirty data in the cache. This will have happened in setttb() 418 * but since we are boot strapping the addresses used for the read 419 * may have just been remapped and thus the cache could be out 420 * of sync. A re-clean after the switch will cure this. 421 * After booting there are no gross relocations of the kernel thus 422 * this problem will not occur after initarm(). 423 */ 424 cpu_idcache_wbinv_all(); 425 /* ready to setup the console (XXX move earlier if possible) */ 426 cninit(); 427 /* 428 * Fetch the RAM size from the MCU registers. The 429 * expansion bus was mapped above so we can now read 'em. 430 */ 431 if (cpu_is_ixp43x()) 432 memsize = ixp435_ddram_size(); 433 else 434 memsize = ixp425_sdram_size(); 435 physmem = memsize / PAGE_SIZE; 436 437 /* Set stack for exception handlers */ 438 439 data_abort_handler_address = (u_int)data_abort_handler; 440 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 441 undefined_handler_address = (u_int)undefinedinstruction_bounce; 442 undefined_init(); 443 444 init_proc0(kernelstack.pv_va); 445 446 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 447 448 pmap_curmaxkvaddr = afterkern + PAGE_SIZE; 449 dump_avail[0] = PHYSADDR; 450 dump_avail[1] = PHYSADDR + memsize; 451 dump_avail[2] = 0; 452 dump_avail[3] = 0; 453 454 pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt); 455 msgbufp = (void*)msgbufpv.pv_va; 456 msgbufinit(msgbufp, msgbufsize); 457 mutex_init(); 458 459 i = 0; 460#ifdef ARM_USE_SMALL_ALLOC 461 phys_avail[i++] = PHYSADDR; 462 phys_avail[i++] = PHYSADDR + PAGE_SIZE; /* 463 *XXX: Gross hack to get our 464 * pages in the vm_page_array. 465 */ 466#endif 467 phys_avail[i++] = round_page(virtual_avail - KERNBASE + PHYSADDR); 468 phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1); 469 phys_avail[i++] = 0; 470 phys_avail[i] = 0; 471 472 init_param2(physmem); 473 kdb_init(); 474 475 /* use static kernel environment if so configured */ 476 if (envmode == 1) 477 kern_envp = static_env; 478 479 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 480 sizeof(struct pcb))); 481#undef next_page 482#undef next_chunk2 483} 484