avila_machdep.c revision 236524
1164426Ssam/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ 2164426Ssam 3164426Ssam/*- 4164426Ssam * Copyright (c) 1994-1998 Mark Brinicombe. 5164426Ssam * Copyright (c) 1994 Brini. 6164426Ssam * All rights reserved. 7164426Ssam * 8164426Ssam * This code is derived from software written for Brini by Mark Brinicombe 9164426Ssam * 10164426Ssam * Redistribution and use in source and binary forms, with or without 11164426Ssam * modification, are permitted provided that the following conditions 12164426Ssam * are met: 13164426Ssam * 1. Redistributions of source code must retain the above copyright 14164426Ssam * notice, this list of conditions and the following disclaimer. 15164426Ssam * 2. Redistributions in binary form must reproduce the above copyright 16164426Ssam * notice, this list of conditions and the following disclaimer in the 17164426Ssam * documentation and/or other materials provided with the distribution. 18164426Ssam * 3. All advertising materials mentioning features or use of this software 19164426Ssam * must display the following acknowledgement: 20164426Ssam * This product includes software developed by Brini. 21164426Ssam * 4. The name of the company nor the name of the author may be used to 22164426Ssam * endorse or promote products derived from this software without specific 23164426Ssam * prior written permission. 24164426Ssam * 25164426Ssam * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26164426Ssam * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27164426Ssam * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28164426Ssam * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29164426Ssam * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30164426Ssam * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31164426Ssam * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32164426Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33164426Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34164426Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35164426Ssam * SUCH DAMAGE. 36164426Ssam * 37164426Ssam * RiscBSD kernel project 38164426Ssam * 39164426Ssam * machdep.c 40164426Ssam * 41164426Ssam * Machine dependant functions for kernel setup 42164426Ssam * 43164426Ssam * This file needs a lot of work. 44164426Ssam * 45164426Ssam * Created : 17/09/94 46164426Ssam */ 47164426Ssam 48164426Ssam#include <sys/cdefs.h> 49164426Ssam__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/avila_machdep.c 236524 2012-06-03 18:34:32Z imp $"); 50164426Ssam 51164426Ssam#define _ARM32_BUS_DMA_PRIVATE 52164426Ssam#include <sys/param.h> 53164426Ssam#include <sys/systm.h> 54164426Ssam#include <sys/sysproto.h> 55164426Ssam#include <sys/signalvar.h> 56164426Ssam#include <sys/imgact.h> 57164426Ssam#include <sys/kernel.h> 58164426Ssam#include <sys/ktr.h> 59164426Ssam#include <sys/linker.h> 60164426Ssam#include <sys/lock.h> 61164426Ssam#include <sys/malloc.h> 62164426Ssam#include <sys/mutex.h> 63164426Ssam#include <sys/pcpu.h> 64164426Ssam#include <sys/proc.h> 65164426Ssam#include <sys/ptrace.h> 66164426Ssam#include <sys/cons.h> 67164426Ssam#include <sys/bio.h> 68164426Ssam#include <sys/bus.h> 69164426Ssam#include <sys/buf.h> 70164426Ssam#include <sys/exec.h> 71164426Ssam#include <sys/kdb.h> 72164426Ssam#include <sys/msgbuf.h> 73164426Ssam#include <machine/reg.h> 74164426Ssam#include <machine/cpu.h> 75164426Ssam 76164426Ssam#include <vm/vm.h> 77164426Ssam#include <vm/pmap.h> 78164426Ssam#include <vm/vm_object.h> 79164426Ssam#include <vm/vm_page.h> 80164426Ssam#include <vm/vm_pager.h> 81164426Ssam#include <vm/vm_map.h> 82164426Ssam#include <vm/vnode_pager.h> 83164426Ssam#include <machine/pmap.h> 84164426Ssam#include <machine/vmparam.h> 85164426Ssam#include <machine/pcb.h> 86164426Ssam#include <machine/undefined.h> 87164426Ssam#include <machine/machdep.h> 88164426Ssam#include <machine/metadata.h> 89164426Ssam#include <machine/armreg.h> 90164426Ssam#include <machine/bus.h> 91164426Ssam#include <sys/reboot.h> 92164426Ssam 93164426Ssam#include <arm/xscale/ixp425/ixp425reg.h> 94164426Ssam#include <arm/xscale/ixp425/ixp425var.h> 95164426Ssam 96186352Ssam/* kernel text starts where we were loaded at boot */ 97186352Ssam#define KERNEL_TEXT_OFF (KERNPHYSADDR - PHYSADDR) 98186352Ssam#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF) 99186352Ssam#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF) 100186352Ssam 101164426Ssam#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 102164426Ssam#define KERNEL_PT_IO 1 103164426Ssam#define KERNEL_PT_IO_NUM 3 104164426Ssam#define KERNEL_PT_BEFOREKERN KERNEL_PT_IO + KERNEL_PT_IO_NUM 105164426Ssam#define KERNEL_PT_AFKERNEL KERNEL_PT_BEFOREKERN + 1 /* L2 table for mapping after kernel */ 106164426Ssam#define KERNEL_PT_AFKERNEL_NUM 9 107164426Ssam 108164426Ssam/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ 109164426Ssam#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) 110164426Ssam 111164426Ssam/* Define various stack sizes in pages */ 112164426Ssam#define IRQ_STACK_SIZE 1 113164426Ssam#define ABT_STACK_SIZE 1 114164426Ssam#define UND_STACK_SIZE 1 115164426Ssam 116164426Ssamextern u_int data_abort_handler_address; 117164426Ssamextern u_int prefetch_abort_handler_address; 118164426Ssamextern u_int undefined_handler_address; 119164426Ssam 120164426Ssamstruct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; 121164426Ssam 122164426Ssamextern void *_end; 123164426Ssam 124164426Ssamextern int *end; 125164426Ssam 126164426Ssamstruct pcpu __pcpu; 127164426Ssamstruct pcpu *pcpup = &__pcpu; 128164426Ssam 129164426Ssam/* Physical and virtual addresses for some global pages */ 130164426Ssam 131164426Ssamvm_paddr_t phys_avail[10]; 132164426Ssamvm_paddr_t dump_avail[4]; 133164426Ssamvm_offset_t physical_pages; 134164426Ssam 135164426Ssamstruct pv_addr systempage; 136164426Ssamstruct pv_addr msgbufpv; 137164426Ssamstruct pv_addr irqstack; 138164426Ssamstruct pv_addr undstack; 139164426Ssamstruct pv_addr abtstack; 140164426Ssamstruct pv_addr kernelstack; 141164426Ssamstruct pv_addr minidataclean; 142164426Ssam 143164426Ssamstatic struct trapframe proc0_tf; 144164426Ssam 145164426Ssam/* Static device mappings. */ 146164426Ssamstatic const struct pmap_devmap ixp425_devmap[] = { 147164426Ssam /* Physical/Virtual address for I/O space */ 148186352Ssam { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 149186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 150164426Ssam 151164426Ssam /* Expansion Bus */ 152186352Ssam { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 153186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 154164426Ssam 155188088Ssam /* CFI Flash on the Expansion Bus */ 156188088Ssam { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 157188088Ssam IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 158188088Ssam 159164426Ssam /* IXP425 PCI Configuration */ 160186352Ssam { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 161186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 162164426Ssam 163164426Ssam /* SDRAM Controller */ 164186352Ssam { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, 165186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 166164426Ssam 167164426Ssam /* PCI Memory Space */ 168186352Ssam { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 169186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 170186352Ssam 171186352Ssam /* Q-Mgr Memory Space */ 172186352Ssam { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 173186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 174186352Ssam 175186352Ssam { 0 }, 176186352Ssam}; 177186352Ssam 178186352Ssam/* Static device mappings. */ 179186352Ssamstatic const struct pmap_devmap ixp435_devmap[] = { 180186352Ssam /* Physical/Virtual address for I/O space */ 181186352Ssam { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, 182186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 183186352Ssam 184186352Ssam { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, 185186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 186186352Ssam 187186352Ssam /* IXP425 PCI Configuration */ 188186352Ssam { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, 189186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 190186352Ssam 191186352Ssam /* DDRII Controller NB: mapped same place as IXP425 */ 192186352Ssam { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, 193186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 194186352Ssam 195186352Ssam /* PCI Memory Space */ 196186352Ssam { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, 197186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 198186352Ssam 199164426Ssam /* Q-Mgr Memory Space */ 200186352Ssam { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, 201186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 202164426Ssam 203194654Ssam /* CFI Flash on the Expansion Bus */ 204194654Ssam { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, 205194654Ssam IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 206194654Ssam 207186352Ssam /* USB1 Memory Space */ 208186352Ssam { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, 209186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 210186352Ssam /* USB2 Memory Space */ 211186352Ssam { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, 212186352Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 213186352Ssam 214194654Ssam /* GPS Memory Space */ 215194654Ssam { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, 216194654Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 217194654Ssam 218194654Ssam /* RS485 Memory Space */ 219194654Ssam { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, 220194654Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, 221194654Ssam 222186352Ssam { 0 } 223164426Ssam}; 224164426Ssam 225164426Ssamextern vm_offset_t xscale_cache_clean_addr; 226164426Ssam 227164426Ssamvoid * 228236524Simpinitarm(struct arm_boot_params *abp) 229164426Ssam{ 230186352Ssam#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1)) 231186352Ssam#define next_page(a) next_chunk2(a,PAGE_SIZE) 232164426Ssam struct pv_addr kernel_l1pt; 233194784Sjeff struct pv_addr dpcpu; 234177886Sraj int loop, i; 235164426Ssam u_int l1pagetable; 236164426Ssam vm_offset_t freemempos; 237164426Ssam vm_offset_t freemem_pt; 238164426Ssam vm_offset_t afterkern; 239164426Ssam vm_offset_t freemem_after; 240164426Ssam vm_offset_t lastaddr; 241164426Ssam uint32_t memsize; 242164426Ssam 243186352Ssam set_cpufuncs(); /* NB: sets cputype */ 244177886Sraj lastaddr = fake_preload_metadata(); 245164426Ssam pcpu_init(pcpup, 0, sizeof(struct pcpu)); 246164426Ssam PCPU_SET(curthread, &thread0); 247164426Ssam 248218666Scognet /* Do basic tuning, hz etc */ 249218666Scognet init_param1(); 250218666Scognet 251186352Ssam /* 252186352Ssam * We allocate memory downwards from where we were loaded 253186352Ssam * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS 254186352Ssam * entries in the L2 page table. Past that we re-align the 255186352Ssam * allocation boundary so later data structures (stacks, etc) 256186352Ssam * can be mapped with different attributes (write-back vs 257186352Ssam * write-through). Note this leaves a gap for expansion 258186352Ssam * (or might be repurposed). 259186352Ssam */ 260186352Ssam freemempos = KERNPHYSADDR; 261164426Ssam 262186352Ssam /* macros to simplify initial memory allocation */ 263186352Ssam#define alloc_pages(var, np) do { \ 264186352Ssam freemempos -= (np * PAGE_SIZE); \ 265186352Ssam (var) = freemempos; \ 266186352Ssam /* NB: this works because locore maps PA=VA */ \ 267186352Ssam memset((char *)(var), 0, ((np) * PAGE_SIZE)); \ 268186352Ssam} while (0) 269186352Ssam#define valloc_pages(var, np) do { \ 270186352Ssam alloc_pages((var).pv_pa, (np)); \ 271186352Ssam (var).pv_va = (var).pv_pa + (KERNVIRTADDR - KERNPHYSADDR); \ 272186352Ssam} while (0) 273164426Ssam 274186352Ssam /* force L1 page table alignment */ 275164426Ssam while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) 276164426Ssam freemempos -= PAGE_SIZE; 277186352Ssam /* allocate contiguous L1 page table */ 278164426Ssam valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 279186352Ssam /* now allocate L2 page tables; they are linked to L1 below */ 280164426Ssam for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { 281164426Ssam if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { 282164426Ssam valloc_pages(kernel_pt_table[loop], 283164426Ssam L2_TABLE_SIZE / PAGE_SIZE); 284164426Ssam } else { 285164426Ssam kernel_pt_table[loop].pv_pa = freemempos + 286164426Ssam (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * 287164426Ssam L2_TABLE_SIZE_REAL; 288164426Ssam kernel_pt_table[loop].pv_va = 289186352Ssam kernel_pt_table[loop].pv_pa + 290186352Ssam (KERNVIRTADDR - KERNPHYSADDR); 291164426Ssam } 292164426Ssam } 293186352Ssam freemem_pt = freemempos; /* base of allocated pt's */ 294186352Ssam 295164426Ssam /* 296186352Ssam * Re-align allocation boundary so we can map the area 297186352Ssam * write-back instead of write-through for the stacks and 298186352Ssam * related structures allocated below. 299186352Ssam */ 300186352Ssam freemempos = PHYSADDR + 0x100000; 301186352Ssam /* 302164426Ssam * Allocate a page for the system page mapped to V0x00000000 303164426Ssam * This page will just contain the system vectors and can be 304164426Ssam * shared by all processes. 305164426Ssam */ 306164426Ssam valloc_pages(systempage, 1); 307164426Ssam 308194784Sjeff /* Allocate dynamic per-cpu area. */ 309194784Sjeff valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); 310194784Sjeff dpcpu_init((void *)dpcpu.pv_va, 0); 311194784Sjeff 312164426Ssam /* Allocate stacks for all modes */ 313164426Ssam valloc_pages(irqstack, IRQ_STACK_SIZE); 314164426Ssam valloc_pages(abtstack, ABT_STACK_SIZE); 315164426Ssam valloc_pages(undstack, UND_STACK_SIZE); 316164426Ssam valloc_pages(kernelstack, KSTACK_PAGES); 317164426Ssam alloc_pages(minidataclean.pv_pa, 1); 318217688Spluknet valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); 319164426Ssam#ifdef ARM_USE_SMALL_ALLOC 320164426Ssam freemempos -= PAGE_SIZE; 321164426Ssam freemem_pt = trunc_page(freemem_pt); 322188505Ssam freemem_after = freemempos - ((freemem_pt - (PHYSADDR + 0x100000)) / 323164426Ssam PAGE_SIZE) * sizeof(struct arm_small_page); 324188505Ssam arm_add_smallalloc_pages( 325188505Ssam (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)), 326188505Ssam (void *)0xc0100000, 327188505Ssam freemem_pt - (PHYSADDR + 0x100000), 1); 328188505Ssam freemem_after -= ((freemem_after - (PHYSADDR + 0x1000)) / PAGE_SIZE) * 329164426Ssam sizeof(struct arm_small_page); 330188505Ssam arm_add_smallalloc_pages( 331188505Ssam (void *)(freemem_after + (KERNVIRTADDR - KERNPHYSADDR)), 332188505Ssam (void *)0xc0001000, 333188505Ssam trunc_page(freemem_after) - (PHYSADDR + 0x1000), 0); 334164426Ssam freemempos = trunc_page(freemem_after); 335164426Ssam freemempos -= PAGE_SIZE; 336164426Ssam#endif 337164426Ssam 338164426Ssam /* 339186352Ssam * Now construct the L1 page table. First map the L2 340186352Ssam * page tables into the L1 so we can replace L1 mappings 341186352Ssam * later on if necessary 342164426Ssam */ 343164426Ssam l1pagetable = kernel_l1pt.pv_va; 344164426Ssam 345164426Ssam /* Map the L2 pages tables in the L1 page table */ 346164426Ssam pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1), 347164426Ssam &kernel_pt_table[KERNEL_PT_SYS]); 348164426Ssam pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE, 349186352Ssam &kernel_pt_table[KERNEL_PT_IO]); 350164426Ssam pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE, 351186352Ssam &kernel_pt_table[KERNEL_PT_IO + 1]); 352164426Ssam pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE, 353186352Ssam &kernel_pt_table[KERNEL_PT_IO + 2]); 354164426Ssam pmap_link_l2pt(l1pagetable, KERNBASE, 355164426Ssam &kernel_pt_table[KERNEL_PT_BEFOREKERN]); 356186352Ssam pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000, 357164426Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 358186352Ssam pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000, 359164426Ssam 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 360186352Ssam pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS, 361186352Ssam next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE), 362164426Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 363186352Ssam freemem_after = next_page((int)lastaddr); 364186352Ssam afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE)); 365164426Ssam for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { 366164426Ssam pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, 367164426Ssam &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); 368164426Ssam } 369164426Ssam pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, 370164426Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 371164426Ssam 372164426Ssam#ifdef ARM_USE_SMALL_ALLOC 373164426Ssam if ((freemem_after + 2 * PAGE_SIZE) <= afterkern) { 374164426Ssam arm_add_smallalloc_pages((void *)(freemem_after), 375164426Ssam (void*)(freemem_after + PAGE_SIZE), 376164426Ssam afterkern - (freemem_after + PAGE_SIZE), 0); 377164426Ssam 378164426Ssam } 379164426Ssam#endif 380164426Ssam 381164426Ssam /* Map the Mini-Data cache clean area. */ 382164426Ssam xscale_setup_minidata(l1pagetable, afterkern, 383164426Ssam minidataclean.pv_pa); 384164426Ssam 385164426Ssam /* Map the vector page. */ 386164426Ssam pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 387164426Ssam VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 388186352Ssam if (cpu_is_ixp43x()) 389186352Ssam pmap_devmap_bootstrap(l1pagetable, ixp435_devmap); 390186352Ssam else 391186352Ssam pmap_devmap_bootstrap(l1pagetable, ixp425_devmap); 392164426Ssam /* 393164426Ssam * Give the XScale global cache clean code an appropriately 394164426Ssam * sized chunk of unmapped VA space starting at 0xff000000 395164426Ssam * (our device mappings end before this address). 396164426Ssam */ 397164426Ssam xscale_cache_clean_addr = 0xff000000U; 398164426Ssam 399164426Ssam cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 400164426Ssam setttb(kernel_l1pt.pv_pa); 401164426Ssam cpu_tlb_flushID(); 402164426Ssam cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 403186352Ssam 404164426Ssam /* 405164426Ssam * Pages were allocated during the secondary bootstrap for the 406164426Ssam * stacks for different CPU modes. 407164426Ssam * We must now set the r13 registers in the different CPU modes to 408164426Ssam * point to these stacks. 409164426Ssam * Since the ARM stacks use STMFD etc. we must set r13 to the top end 410164426Ssam * of the stack memory. 411164426Ssam */ 412186352Ssam set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + IRQ_STACK_SIZE*PAGE_SIZE); 413186352Ssam set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + ABT_STACK_SIZE*PAGE_SIZE); 414186352Ssam set_stackptr(PSR_UND32_MODE, undstack.pv_va + UND_STACK_SIZE*PAGE_SIZE); 415164426Ssam 416164426Ssam /* 417164426Ssam * We must now clean the cache again.... 418164426Ssam * Cleaning may be done by reading new data to displace any 419164426Ssam * dirty data in the cache. This will have happened in setttb() 420164426Ssam * but since we are boot strapping the addresses used for the read 421164426Ssam * may have just been remapped and thus the cache could be out 422164426Ssam * of sync. A re-clean after the switch will cure this. 423185513Sstas * After booting there are no gross relocations of the kernel thus 424164426Ssam * this problem will not occur after initarm(). 425164426Ssam */ 426164426Ssam cpu_idcache_wbinv_all(); 427186352Ssam /* ready to setup the console (XXX move earlier if possible) */ 428186352Ssam cninit(); 429164426Ssam /* 430186352Ssam * Fetch the RAM size from the MCU registers. The 431186352Ssam * expansion bus was mapped above so we can now read 'em. 432164426Ssam */ 433186352Ssam if (cpu_is_ixp43x()) 434186352Ssam memsize = ixp435_ddram_size(); 435186352Ssam else 436186352Ssam memsize = ixp425_sdram_size(); 437164426Ssam physmem = memsize / PAGE_SIZE; 438164426Ssam 439164426Ssam /* Set stack for exception handlers */ 440186352Ssam 441164426Ssam data_abort_handler_address = (u_int)data_abort_handler; 442164426Ssam prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 443164426Ssam undefined_handler_address = (u_int)undefinedinstruction_bounce; 444164426Ssam undefined_init(); 445186352Ssam 446173361Skib proc_linkup0(&proc0, &thread0); 447164426Ssam thread0.td_kstack = kernelstack.pv_va; 448164426Ssam thread0.td_pcb = (struct pcb *) 449164426Ssam (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 450164426Ssam thread0.td_pcb->pcb_flags = 0; 451164426Ssam thread0.td_frame = &proc0_tf; 452164426Ssam pcpup->pc_curpcb = thread0.td_pcb; 453164426Ssam 454164426Ssam arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 455164426Ssam 456164426Ssam pmap_curmaxkvaddr = afterkern + PAGE_SIZE; 457186352Ssam dump_avail[0] = PHYSADDR; 458186352Ssam dump_avail[1] = PHYSADDR + memsize; 459164426Ssam dump_avail[2] = 0; 460164426Ssam dump_avail[3] = 0; 461186352Ssam 462186352Ssam pmap_bootstrap(pmap_curmaxkvaddr, 0xd0000000, &kernel_l1pt); 463164426Ssam msgbufp = (void*)msgbufpv.pv_va; 464217688Spluknet msgbufinit(msgbufp, msgbufsize); 465164426Ssam mutex_init(); 466186352Ssam 467164426Ssam i = 0; 468164426Ssam#ifdef ARM_USE_SMALL_ALLOC 469186352Ssam phys_avail[i++] = PHYSADDR; 470186352Ssam phys_avail[i++] = PHYSADDR + PAGE_SIZE; /* 471164426Ssam *XXX: Gross hack to get our 472194654Ssam * pages in the vm_page_array. 473194654Ssam */ 474164426Ssam#endif 475186352Ssam phys_avail[i++] = round_page(virtual_avail - KERNBASE + PHYSADDR); 476186352Ssam phys_avail[i++] = trunc_page(PHYSADDR + memsize - 1); 477164426Ssam phys_avail[i++] = 0; 478164426Ssam phys_avail[i] = 0; 479186352Ssam 480164426Ssam init_param2(physmem); 481164426Ssam kdb_init(); 482183557Sbms 483183557Sbms /* use static kernel environment if so configured */ 484183557Sbms if (envmode == 1) 485183557Sbms kern_envp = static_env; 486183557Sbms 487164426Ssam return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - 488164426Ssam sizeof(struct pcb))); 489186352Ssam#undef next_page 490186352Ssam#undef next_chunk2 491164426Ssam} 492