zy7_devcfg.c revision 249997
1/*- 2 * Copyright (C) 2013, Thomas Skibo. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * * Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * * The names of contributors may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHORS OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 25 * DAMAGE. 26 * 27 */ 28 29/* Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section 30 * of Zynq. 31 * 32 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 33 * (v1.4) November 16, 2012. Xilinx doc UG585. PL Configuration is 34 * covered in section 6.4.5. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/arm/xilinx/zy7_devcfg.c 249997 2013-04-27 22:38:29Z wkoszek $"); 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/conf.h> 43#include <sys/kernel.h> 44#include <sys/module.h> 45#include <sys/sysctl.h> 46#include <sys/lock.h> 47#include <sys/mutex.h> 48#include <sys/resource.h> 49#include <sys/rman.h> 50#include <sys/uio.h> 51 52#include <machine/bus.h> 53#include <machine/resource.h> 54#include <machine/stdarg.h> 55 56#include <dev/fdt/fdt_common.h> 57#include <dev/ofw/ofw_bus.h> 58#include <dev/ofw/ofw_bus_subr.h> 59 60#include <arm/xilinx/zy7_slcr.h> 61 62struct zy7_devcfg_softc { 63 device_t dev; 64 struct mtx sc_mtx; 65 struct resource *mem_res; 66 struct resource *irq_res; 67 struct cdev *sc_ctl_dev; 68 void *intrhandle; 69 70 bus_dma_tag_t dma_tag; 71 bus_dmamap_t dma_map; 72 73 int is_open; 74}; 75 76static struct zy7_devcfg_softc *zy7_devcfg_softc_p; 77 78#define DEVCFG_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 79#define DEVCFG_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 80#define DEVCFG_SC_LOCK_INIT(sc) \ 81 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \ 82 "zy7_devcfg", MTX_DEF) 83#define DEVCFG_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx); 84#define DEVCFG_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED); 85 86#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) 87#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) 88 89SYSCTL_NODE(_hw, OID_AUTO, fpga, CTLFLAG_RD, 0, \ 90 "Xilinx Zynq-7000 PL (FPGA) section"); 91 92static int zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS); 93SYSCTL_PROC(_hw_fpga, OID_AUTO, pl_done, CTLTYPE_INT | CTLFLAG_RD, NULL, 0, 94 zy7_devcfg_sysctl_pl_done, "I", "PL section config DONE signal"); 95 96static int zy7_en_level_shifters = 1; 97SYSCTL_INT(_hw_fpga, OID_AUTO, en_level_shifters, CTLFLAG_RW, 98 &zy7_en_level_shifters, 0, 99 "Enable PS-PL level shifters after device config"); 100 101static int zy7_ps_vers = 0; 102SYSCTL_INT(_hw, OID_AUTO, ps_vers, CTLFLAG_RD, &zy7_ps_vers, 0, 103 "Zynq-7000 PS version"); 104 105 106/* cdev entry points. */ 107static int zy7_devcfg_open(struct cdev *, int, int, struct thread *); 108static int zy7_devcfg_write(struct cdev *, struct uio *, int); 109static int zy7_devcfg_close(struct cdev *, int, int, struct thread *); 110 111 112struct cdevsw zy7_devcfg_cdevsw = { 113 .d_version = D_VERSION, 114 .d_open = zy7_devcfg_open, 115 .d_write = zy7_devcfg_write, 116 .d_close = zy7_devcfg_close, 117 .d_name = "devcfg", 118}; 119 120/* Devcfg block registers. */ 121#define ZY7_DEVCFG_CTRL 0x0000 122#define ZY7_DEVCFG_CTRL_FORCE_RST (1<<31) 123#define ZY7_DEVCFG_CTRL_PCFG_PROG_B (1<<30) 124#define ZY7_DEVCFG_CTRL_PCFG_POR_CNT_4K (1<<29) 125#define ZY7_DEVCFG_CTRL_PCAP_PR (1<<27) 126#define ZY7_DEVCFG_CTRL_PCAP_MODE (1<<26) 127#define ZY7_DEVCFG_CTRL_QTR_PCAP_RATE_EN (1<<25) 128#define ZY7_DEVCFG_CTRL_MULTIBOOT_EN (1<<24) 129#define ZY7_DEVCFG_CTRL_JTAG_CHAIN_DIS (1<<23) 130#define ZY7_DEVCFG_CTRL_USER_MODE (1<<15) 131#define ZY7_DEVCFG_CTRL_RESVD_WR11 (3<<13) /* always write 11 */ 132#define ZY7_DEVCFG_CTRL_PCFG_AES_FUSE (1<<12) 133#define ZY7_DEVCFG_CTRL_PCFG_AES_EN_MASK (7<<9) /* all 1's or 0's */ 134#define ZY7_DEVCFG_CTRL_SEU_EN (1<<8) 135#define ZY7_DEVCFG_CTRL_SEC_EN (1<<7) 136#define ZY7_DEVCFG_CTRL_SPNIDEN (1<<6) 137#define ZY7_DEVCFG_CTRL_SPIDEN (1<<5) 138#define ZY7_DEVCFG_CTRL_NIDEN (1<<4) 139#define ZY7_DEVCFG_CTRL_DBGEN (1<<3) 140#define ZY7_DEVCFG_CTRL_DAP_EN_MASK (7<<0) /* all 1's to enable */ 141 142#define ZY7_DEVCFG_LOCK 0x004 143#define ZY7_DEVCFG_LOCK_AES_FUSE_LOCK (1<<4) 144#define ZY7_DEVCFG_LOCK_AES_EN (1<<3) 145#define ZY7_DEVCFG_LOCK_SEU_LOCK (1<<2) 146#define ZY7_DEVCFG_LOCK_SEC_LOCK (1<<1) 147#define ZY7_DEVCFG_LOCK_DBG_LOCK (1<<0) 148 149#define ZY7_DEVCFG_CFG 0x008 150#define ZY7_DEVCFG_CFG_RFIFO_TH_MASK (3<<10) 151#define ZY7_DEVCFG_CFG_WFIFO_TH_MASK (3<<8) 152#define ZY7_DEVCFG_CFG_RCLK_EDGE (1<<7) 153#define ZY7_DEVCFG_CFG_WCLK_EDGE (1<<6) 154#define ZY7_DEVCFG_CFG_DIS_SRC_INC (1<<5) 155#define ZY7_DEVCFG_CFG_DIS_DST_INC (1<<4) 156 157#define ZY7_DEVCFG_INT_STATUS 0x00C 158#define ZY7_DEVCFG_INT_MASK 0x010 159#define ZY7_DEVCFG_INT_PSS_GTS_USR_B (1<<31) 160#define ZY7_DEVCFG_INT_PSS_FST_CFG_B (1<<30) 161#define ZY7_DEVCFG_INT_PSS_GPWRDWN_B (1<<29) 162#define ZY7_DEVCFG_INT_PSS_GTS_CFG_B (1<<28) 163#define ZY7_DEVCFG_INT_CFG_RESET_B (1<<27) 164#define ZY7_DEVCFG_INT_AXI_WTO (1<<23) /* axi write timeout */ 165#define ZY7_DEVCFG_INT_AXI_WERR (1<<22) /* axi write err */ 166#define ZY7_DEVCFG_INT_AXI_RTO (1<<21) /* axi read timeout */ 167#define ZY7_DEVCFG_INT_AXI_RERR (1<<20) /* axi read err */ 168#define ZY7_DEVCFG_INT_RX_FIFO_OV (1<<18) /* rx fifo overflow */ 169#define ZY7_DEVCFG_INT_WR_FIFO_LVL (1<<17) /* wr fifo < level */ 170#define ZY7_DEVCFG_INT_RD_FIFO_LVL (1<<16) /* rd fifo >= level */ 171#define ZY7_DEVCFG_INT_DMA_CMD_ERR (1<<15) 172#define ZY7_DEVCFG_INT_DMA_Q_OV (1<<14) 173#define ZY7_DEVCFG_INT_DMA_DONE (1<<13) 174#define ZY7_DEVCFG_INT_DMA_PCAP_DONE (1<<12) 175#define ZY7_DEVCFG_INT_P2D_LEN_ERR (1<<11) 176#define ZY7_DEVCFG_INT_PCFG_HMAC_ERR (1<<6) 177#define ZY7_DEVCFG_INT_PCFG_SEU_ERR (1<<5) 178#define ZY7_DEVCFG_INT_PCFG_POR_B (1<<4) 179#define ZY7_DEVCFG_INT_PCFG_CFG_RST (1<<3) 180#define ZY7_DEVCFG_INT_PCFG_DONE (1<<2) 181#define ZY7_DEVCFG_INT_PCFG_INIT_PE (1<<1) 182#define ZY7_DEVCFG_INT_PCFG_INIT_NE (1<<0) 183#define ZY7_DEVCFG_INT_ERRORS 0x00f0f860 184#define ZY7_DEVCFG_INT_ALL 0xf8f7f87f 185 186#define ZY7_DEVCFG_STATUS 0x014 187#define ZY7_DEVCFG_STATUS_DMA_CMD_Q_F (1<<31) /* cmd queue full */ 188#define ZY7_DEVCFG_STATUS_DMA_CMD_Q_E (1<<30) /* cmd queue empty */ 189#define ZY7_DEVCFG_STATUS_DONE_COUNT_MASK (3<<28) 190#define ZY7_DEVCFG_STATUS_DONE_COUNT_SHIFT 28 191#define ZY7_DEVCFG_STATUS_RX_FIFO_LVL_MASK (0x1f<<20) 192#define ZY7_DEVCFG_STATUS_RX_FIFO_LVL_SHIFT 20 193#define ZY7_DEVCFG_STATUS_TX_FIFO_LVL_MASK (0x7f<<12) 194#define ZY7_DEVCFG_STATUS_TX_FIFO_LVL_SHIFT 12 195#define ZY7_DEVCFG_STATUS_PSS_GTS_USR_B (1<<11) 196#define ZY7_DEVCFG_STATUS_PSS_FST_CFG_B (1<<10) 197#define ZY7_DEVCFG_STATUS_PSS_GPWRDWN_B (1<<9) 198#define ZY7_DEVCFG_STATUS_PSS_GTS_CFG_B (1<<8) 199#define ZY7_DEVCFG_STATUS_ILL_APB_ACCE (1<<6) 200#define ZY7_DEVCFG_STATUS_PSS_CFG_RESET_B (1<<5) 201#define ZY7_DEVCFG_STATUS_PCFG_INIT (1<<4) 202#define ZY7_DEVCFG_STATUS_EFUSE_BBRAM_KEY_DIS (1<<3) 203#define ZY7_DEVCFG_STATUS_EFUSE_SEC_EN (1<<2) 204#define ZY7_DEVCFG_STATUS_EFUSE_JTAG_DIS (1<<1) 205 206#define ZY7_DEVCFG_DMA_SRC_ADDR 0x018 207#define ZY7_DEVCFG_DMA_DST_ADDR 0x01c 208#define ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP 1 209#define ZY7_DEVCFG_DMA_ADDR_ILLEGAL 0xffffffff 210 211#define ZY7_DEVCFG_DMA_SRC_LEN 0x020 /* in 4-byte words. */ 212#define ZY7_DEVCFG_DMA_SRC_LEN_MAX 0x7ffffff 213#define ZY7_DEVCFG_DMA_DST_LEN 0x024 214#define ZY7_DEVCFG_ROM_SHADOW 0x028 215#define ZY7_DEVCFG_MULTIBOOT_ADDR 0x02c 216#define ZY7_DEVCFG_SW_ID 0x030 217#define ZY7_DEVCFG_UNLOCK 0x034 218#define ZY7_DEVCFG_UNLOCK_MAGIC 0x757bdf0d 219#define ZY7_DEVCFG_MCTRL 0x080 220#define ZY7_DEVCFG_MCTRL_PS_VERS_MASK (0xf<<28) 221#define ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT 28 222#define ZY7_DEVCFG_MCTRL_PCFG_POR_B (1<<8) 223#define ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK (1<<4) 224#define ZY7_DEVCFG_XADCIF_CFG 0x100 225#define ZY7_DEVCFG_XADCIF_INT_STAT 0x104 226#define ZY7_DEVCFG_XADCIF_INT_MASK 0x108 227#define ZY7_DEVCFG_XADCIF_MSTS 0x10c 228#define ZY7_DEVCFG_XADCIF_CMD_FIFO 0x110 229#define ZY7_DEVCFG_XADCIF_RD_FIFO 0x114 230#define ZY7_DEVCFG_XADCIF_MCTL 0x118 231 232 233/* Enable programming the PL through PCAP. */ 234static void 235zy7_devcfg_init_hw(struct zy7_devcfg_softc *sc) 236{ 237 238 DEVCFG_SC_ASSERT_LOCKED(sc); 239 240 /* Set devcfg control register. */ 241 WR4(sc, ZY7_DEVCFG_CTRL, 242 ZY7_DEVCFG_CTRL_PCFG_PROG_B | 243 ZY7_DEVCFG_CTRL_PCAP_PR | 244 ZY7_DEVCFG_CTRL_PCAP_MODE | 245 ZY7_DEVCFG_CTRL_USER_MODE | 246 ZY7_DEVCFG_CTRL_RESVD_WR11 | 247 ZY7_DEVCFG_CTRL_SPNIDEN | 248 ZY7_DEVCFG_CTRL_SPIDEN | 249 ZY7_DEVCFG_CTRL_NIDEN | 250 ZY7_DEVCFG_CTRL_DBGEN | 251 ZY7_DEVCFG_CTRL_DAP_EN_MASK); 252 253 /* Turn off internal PCAP loopback. */ 254 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) & 255 ~ZY7_DEVCFG_MCTRL_INT_PCAP_LPBK); 256} 257 258/* Clear previous configuration of the PL by asserting PROG_B. */ 259static int 260zy7_devcfg_reset_pl(struct zy7_devcfg_softc *sc) 261{ 262 uint32_t devcfg_ctl; 263 int tries, err; 264 265 DEVCFG_SC_ASSERT_LOCKED(sc); 266 267 devcfg_ctl = RD4(sc, ZY7_DEVCFG_CTRL); 268 269 /* Deassert PROG_B (active low). */ 270 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B; 271 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 272 273 /* Wait for INIT_B deasserted (active low). */ 274 tries = 0; 275 while ((RD4(sc, ZY7_DEVCFG_STATUS) & 276 ZY7_DEVCFG_STATUS_PCFG_INIT) == 0) { 277 if (++tries >= 100) 278 return (EIO); 279 DELAY(5); 280 } 281 282 /* Reassert PROG_B. */ 283 devcfg_ctl &= ~ZY7_DEVCFG_CTRL_PCFG_PROG_B; 284 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 285 286 /* Wait for INIT_B asserted. */ 287 tries = 0; 288 while ((RD4(sc, ZY7_DEVCFG_STATUS) & 289 ZY7_DEVCFG_STATUS_PCFG_INIT) != 0) { 290 if (++tries >= 100) 291 return (EIO); 292 DELAY(5); 293 } 294 295 /* Clear sticky bits and set up INIT_B positive edge interrupt. */ 296 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 297 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); 298 299 /* Deassert PROG_B again. */ 300 devcfg_ctl |= ZY7_DEVCFG_CTRL_PCFG_PROG_B; 301 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 302 303 /* Wait for INIT_B deasserted indicating FPGA internal initialization 304 * is complete. This takes much longer than the previous waits for 305 * INIT_B transition (on the order of 700us). 306 */ 307 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7in", hz); 308 if (err != 0) 309 return (err); 310 311 /* Clear sticky DONE bit in interrupt status. */ 312 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 313 314 return (0); 315} 316 317/* Callback function for bus_dmamap_load(). */ 318static void 319zy7_dma_cb2(void *arg, bus_dma_segment_t *seg, int nsegs, int error) 320{ 321 if (!error && nsegs == 1) 322 *(bus_addr_t *)arg = seg[0].ds_addr; 323} 324 325 326static int 327zy7_devcfg_open(struct cdev *dev, int oflags, int devtype, struct thread *td) 328{ 329 struct zy7_devcfg_softc *sc = dev->si_drv1; 330 int err; 331 332 DEVCFG_SC_LOCK(sc); 333 if (sc->is_open) { 334 DEVCFG_SC_UNLOCK(sc); 335 return (EBUSY); 336 } 337 338 sc->dma_map = NULL; 339 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 4, 0, 340 BUS_SPACE_MAXADDR_32BIT, 341 BUS_SPACE_MAXADDR, 342 NULL, NULL, 343 PAGE_SIZE, 344 1, 345 PAGE_SIZE, 346 0, 347 busdma_lock_mutex, 348 &sc->sc_mtx, 349 &sc->dma_tag); 350 if (err) { 351 DEVCFG_SC_UNLOCK(sc); 352 return (err); 353 } 354 355 sc->is_open = 1; 356 DEVCFG_SC_UNLOCK(sc); 357 return (0); 358} 359 360static int 361zy7_devcfg_write(struct cdev *dev, struct uio *uio, int ioflag) 362{ 363 struct zy7_devcfg_softc *sc = dev->si_drv1; 364 void *dma_mem; 365 bus_addr_t dma_physaddr; 366 int segsz, err; 367 368 DEVCFG_SC_LOCK(sc); 369 370 /* First write? Reset PL. */ 371 if (uio->uio_offset == 0 && uio->uio_resid > 0) { 372 zy7_devcfg_init_hw(sc); 373 zy7_slcr_preload_pl(); 374 err = zy7_devcfg_reset_pl(sc); 375 if (err != 0) { 376 DEVCFG_SC_UNLOCK(sc); 377 return (err); 378 } 379 } 380 381 /* Allocate dma memory and load. */ 382 err = bus_dmamem_alloc(sc->dma_tag, &dma_mem, BUS_DMA_NOWAIT, 383 &sc->dma_map); 384 if (err != 0) { 385 DEVCFG_SC_UNLOCK(sc); 386 return (err); 387 } 388 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, dma_mem, PAGE_SIZE, 389 zy7_dma_cb2, &dma_physaddr, 0); 390 if (err != 0) { 391 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map); 392 DEVCFG_SC_UNLOCK(sc); 393 return (err); 394 } 395 396 while (uio->uio_resid > 0) { 397 /* If DONE signal has been set, we shouldn't write anymore. */ 398 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & 399 ZY7_DEVCFG_INT_PCFG_DONE) != 0) { 400 err = EIO; 401 break; 402 } 403 404 /* uiomove the data from user buffer to our dma map. */ 405 segsz = MIN(PAGE_SIZE, uio->uio_resid); 406 err = uiomove(dma_mem, segsz, uio); 407 if (err != 0) 408 break; 409 410 /* Flush the cache to memory. */ 411 bus_dmamap_sync(sc->dma_tag, sc->dma_map, 412 BUS_DMASYNC_PREWRITE); 413 414 /* Program devcfg's DMA engine. The ordering of these 415 * register writes is critical. 416 */ 417 if (uio->uio_resid > segsz) 418 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR, 419 (uint32_t) dma_physaddr); 420 else 421 WR4(sc, ZY7_DEVCFG_DMA_SRC_ADDR, 422 (uint32_t) dma_physaddr | 423 ZY7_DEVCFG_DMA_ADDR_WAIT_PCAP); 424 WR4(sc, ZY7_DEVCFG_DMA_DST_ADDR, ZY7_DEVCFG_DMA_ADDR_ILLEGAL); 425 WR4(sc, ZY7_DEVCFG_DMA_SRC_LEN, (segsz+3)/4); 426 WR4(sc, ZY7_DEVCFG_DMA_DST_LEN, 0); 427 428 /* Now clear done bit and set up DMA done interrupt. */ 429 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 430 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_DMA_DONE); 431 432 /* Wait for DMA done interrupt. */ 433 err = mtx_sleep(sc->dma_map, &sc->sc_mtx, PCATCH, 434 "zy7dma", hz); 435 if (err != 0) 436 break; 437 438 bus_dmamap_sync(sc->dma_tag, sc->dma_map, 439 BUS_DMASYNC_POSTWRITE); 440 441 /* Check DONE signal. */ 442 if ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & 443 ZY7_DEVCFG_INT_PCFG_DONE) != 0) 444 zy7_slcr_postload_pl(zy7_en_level_shifters); 445 } 446 447 bus_dmamap_unload(sc->dma_tag, sc->dma_map); 448 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map); 449 DEVCFG_SC_UNLOCK(sc); 450 return (err); 451} 452 453static int 454zy7_devcfg_close(struct cdev *dev, int fflag, int devtype, struct thread *td) 455{ 456 struct zy7_devcfg_softc *sc = dev->si_drv1; 457 458 DEVCFG_SC_LOCK(sc); 459 sc->is_open = 0; 460 bus_dma_tag_destroy(sc->dma_tag); 461 DEVCFG_SC_UNLOCK(sc); 462 463 return (0); 464} 465 466 467static void 468zy7_devcfg_intr(void *arg) 469{ 470 struct zy7_devcfg_softc *sc = (struct zy7_devcfg_softc *)arg; 471 uint32_t istatus, imask; 472 473 DEVCFG_SC_LOCK(sc); 474 475 istatus = RD4(sc, ZY7_DEVCFG_INT_STATUS); 476 imask = ~RD4(sc, ZY7_DEVCFG_INT_MASK); 477 478 /* Turn interrupt off. */ 479 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); 480 481 if ((istatus & imask) == 0) { 482 DEVCFG_SC_UNLOCK(sc); 483 return; 484 } 485 486 /* DMA done? */ 487 if ((istatus & ZY7_DEVCFG_INT_DMA_DONE) != 0) 488 wakeup(sc->dma_map); 489 490 /* INIT_B positive edge? */ 491 if ((istatus & ZY7_DEVCFG_INT_PCFG_INIT_PE) != 0) 492 wakeup(sc); 493 494 DEVCFG_SC_UNLOCK(sc); 495} 496 497/* zy7_devcfg_sysctl_pl_done() returns status of the PL_DONE signal. 498 */ 499static int 500zy7_devcfg_sysctl_pl_done(SYSCTL_HANDLER_ARGS) 501{ 502 struct zy7_devcfg_softc *sc = zy7_devcfg_softc_p; 503 int pl_done = 0; 504 505 if (sc) { 506 DEVCFG_SC_LOCK(sc); 507 508 /* PCFG_DONE bit is sticky. Clear it before checking it. */ 509 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_PCFG_DONE); 510 pl_done = ((RD4(sc, ZY7_DEVCFG_INT_STATUS) & 511 ZY7_DEVCFG_INT_PCFG_DONE) != 0); 512 513 DEVCFG_SC_UNLOCK(sc); 514 } 515 return (sysctl_handle_int(oidp, &pl_done, 0, req)); 516} 517 518static int 519zy7_devcfg_probe(device_t dev) 520{ 521 if (!ofw_bus_is_compatible(dev, "xlnx,zy7_devcfg")) 522 return (ENXIO); 523 524 device_set_desc(dev, "Zynq devcfg block"); 525 return (0); 526} 527 528static int zy7_devcfg_detach(device_t dev); 529 530static int 531zy7_devcfg_attach(device_t dev) 532{ 533 struct zy7_devcfg_softc *sc = device_get_softc(dev); 534 int rid, err; 535 536 /* Allow only one attach. */ 537 if (zy7_devcfg_softc_p != NULL) 538 return (ENXIO); 539 540 sc->dev = dev; 541 542 DEVCFG_SC_LOCK_INIT(sc); 543 544 /* Get memory resource. */ 545 rid = 0; 546 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 547 RF_ACTIVE); 548 if (sc->mem_res == NULL) { 549 device_printf(dev, "could not allocate memory resources.\n"); 550 zy7_devcfg_detach(dev); 551 return (ENOMEM); 552 } 553 554 /* Allocate IRQ. */ 555 rid = 0; 556 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 557 RF_ACTIVE); 558 if (sc->irq_res == NULL) { 559 device_printf(dev, "cannot allocate IRQ\n"); 560 zy7_devcfg_detach(dev); 561 return (ENOMEM); 562 } 563 564 /* Activate the interrupt. */ 565 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 566 NULL, zy7_devcfg_intr, sc, &sc->intrhandle); 567 if (err) { 568 device_printf(dev, "cannot setup IRQ\n"); 569 zy7_devcfg_detach(dev); 570 return (err); 571 } 572 573 /* Create /dev/devcfg */ 574 sc->sc_ctl_dev = make_dev(&zy7_devcfg_cdevsw, 0, 575 UID_ROOT, GID_WHEEL, 0600, "devcfg"); 576 if (sc->sc_ctl_dev == NULL) { 577 device_printf(dev, "failed to create /dev/devcfg"); 578 zy7_devcfg_detach(dev); 579 return (ENXIO); 580 } 581 sc->sc_ctl_dev->si_drv1 = sc; 582 583 zy7_devcfg_softc_p = sc; 584 585 /* Unlock devcfg registers. */ 586 WR4(sc, ZY7_DEVCFG_UNLOCK, ZY7_DEVCFG_UNLOCK_MAGIC); 587 588 /* Make sure interrupts are completely disabled. */ 589 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 590 WR4(sc, ZY7_DEVCFG_INT_MASK, 0xffffffff); 591 592 /* Get PS_VERS for SYSCTL. */ 593 zy7_ps_vers = (RD4(sc, ZY7_DEVCFG_MCTRL) & 594 ZY7_DEVCFG_MCTRL_PS_VERS_MASK) >> 595 ZY7_DEVCFG_MCTRL_PS_VERS_SHIFT; 596 597 return (0); 598} 599 600static int 601zy7_devcfg_detach(device_t dev) 602{ 603 struct zy7_devcfg_softc *sc = device_get_softc(dev); 604 605 if (device_is_attached(dev)) 606 bus_generic_detach(dev); 607 608 /* Get rid of /dev/devcfg0. */ 609 if (sc->sc_ctl_dev != NULL) 610 destroy_dev(sc->sc_ctl_dev); 611 612 /* Teardown and release interrupt. */ 613 if (sc->irq_res != NULL) { 614 if (sc->intrhandle) 615 bus_teardown_intr(dev, sc->irq_res, sc->intrhandle); 616 bus_release_resource(dev, SYS_RES_IRQ, 617 rman_get_rid(sc->irq_res), sc->irq_res); 618 } 619 620 /* Release memory resource. */ 621 if (sc->mem_res != NULL) 622 bus_release_resource(dev, SYS_RES_MEMORY, 623 rman_get_rid(sc->mem_res), sc->mem_res); 624 625 zy7_devcfg_softc_p = NULL; 626 627 DEVCFG_SC_LOCK_DESTROY(sc); 628 629 return (0); 630} 631 632static device_method_t zy7_devcfg_methods[] = { 633 /* device_if */ 634 DEVMETHOD(device_probe, zy7_devcfg_probe), 635 DEVMETHOD(device_attach, zy7_devcfg_attach), 636 DEVMETHOD(device_detach, zy7_devcfg_detach), 637 638 DEVMETHOD_END 639}; 640 641static driver_t zy7_devcfg_driver = { 642 "zy7_devcfg", 643 zy7_devcfg_methods, 644 sizeof(struct zy7_devcfg_softc), 645}; 646static devclass_t zy7_devcfg_devclass; 647 648DRIVER_MODULE(zy7_devcfg, simplebus, zy7_devcfg_driver, zy7_devcfg_devclass, \ 649 0, 0); 650MODULE_DEPEND(zy7_devcfg, zy7_slcr, 1, 1, 1); 651