ti_wdt.c revision 273257
1273257Srpaulo/*- 2273257Srpaulo * Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org> 3273257Srpaulo * All rights reserved. 4273257Srpaulo * 5273257Srpaulo * Redistribution and use in source and binary forms, with or without 6273257Srpaulo * modification, are permitted provided that the following conditions 7273257Srpaulo * are met: 8273257Srpaulo * 1. Redistributions of source code must retain the above copyright 9273257Srpaulo * notice, this list of conditions and the following disclaimer. 10273257Srpaulo * 2. Redistributions in binary form must reproduce the above copyright 11273257Srpaulo * notice, this list of conditions and the following disclaimer in the 12273257Srpaulo * documentation and/or other materials provided with the distribution. 13273257Srpaulo * 14273257Srpaulo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15273257Srpaulo * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16273257Srpaulo * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17273257Srpaulo * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18273257Srpaulo * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19273257Srpaulo * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20273257Srpaulo * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21273257Srpaulo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22273257Srpaulo * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23273257Srpaulo * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24273257Srpaulo * POSSIBILITY OF SUCH DAMAGE. 25273257Srpaulo */ 26273257Srpaulo#include <sys/cdefs.h> 27273257Srpaulo__FBSDID("$FreeBSD: head/sys/arm/ti/ti_wdt.c 273257 2014-10-18 16:59:21Z rpaulo $"); 28273257Srpaulo 29273257Srpaulo#include <sys/param.h> 30273257Srpaulo#include <sys/systm.h> 31273257Srpaulo#include <sys/bus.h> 32273257Srpaulo#include <sys/conf.h> 33273257Srpaulo#include <sys/kernel.h> 34273257Srpaulo#include <sys/module.h> 35273257Srpaulo#include <sys/malloc.h> 36273257Srpaulo#include <sys/rman.h> 37273257Srpaulo#include <sys/event.h> 38273257Srpaulo#include <sys/selinfo.h> 39273257Srpaulo#include <sys/watchdog.h> 40273257Srpaulo#include <machine/bus.h> 41273257Srpaulo#include <machine/cpu.h> 42273257Srpaulo#include <machine/frame.h> 43273257Srpaulo#include <machine/intr.h> 44273257Srpaulo 45273257Srpaulo#include <dev/fdt/fdt_common.h> 46273257Srpaulo#include <dev/ofw/openfirm.h> 47273257Srpaulo#include <dev/ofw/ofw_bus.h> 48273257Srpaulo#include <dev/ofw/ofw_bus_subr.h> 49273257Srpaulo 50273257Srpaulo#include <machine/bus.h> 51273257Srpaulo#include <machine/fdt.h> 52273257Srpaulo 53273257Srpaulo#include <arm/ti/ti_prcm.h> 54273257Srpaulo#include <arm/ti/ti_wdt.h> 55273257Srpaulo 56273257Srpaulo#ifdef DEBUG 57273257Srpaulo#define DPRINTF(fmt, ...) do { \ 58273257Srpaulo printf("%s: ", __func__); \ 59273257Srpaulo printf(fmt, __VA_ARGS__); \ 60273257Srpaulo} while (0) 61273257Srpaulo#else 62273257Srpaulo#define DPRINTF(fmt, ...) 63273257Srpaulo#endif 64273257Srpaulo 65273257Srpaulostatic device_probe_t ti_wdt_probe; 66273257Srpaulostatic device_attach_t ti_wdt_attach; 67273257Srpaulostatic device_detach_t ti_wdt_detach; 68273257Srpaulostatic void ti_wdt_intr(void *); 69273257Srpaulostatic void ti_wdt_event(void *, unsigned int, int *); 70273257Srpaulo 71273257Srpaulostruct ti_wdt_softc { 72273257Srpaulo struct mtx sc_mtx; 73273257Srpaulo struct resource *sc_mem_res; 74273257Srpaulo struct resource *sc_irq_res; 75273257Srpaulo void *sc_intr; 76273257Srpaulo bus_space_tag_t sc_bt; 77273257Srpaulo bus_space_handle_t sc_bh; 78273257Srpaulo eventhandler_tag sc_ev_tag; 79273257Srpaulo}; 80273257Srpaulo 81273257Srpaulostatic device_method_t ti_wdt_methods[] = { 82273257Srpaulo DEVMETHOD(device_probe, ti_wdt_probe), 83273257Srpaulo DEVMETHOD(device_attach, ti_wdt_attach), 84273257Srpaulo DEVMETHOD(device_detach, ti_wdt_detach), 85273257Srpaulo 86273257Srpaulo DEVMETHOD_END 87273257Srpaulo}; 88273257Srpaulo 89273257Srpaulostatic driver_t ti_wdt_driver = { 90273257Srpaulo "ti_wdt", 91273257Srpaulo ti_wdt_methods, 92273257Srpaulo sizeof(struct ti_wdt_softc) 93273257Srpaulo}; 94273257Srpaulo 95273257Srpaulostatic devclass_t ti_wdt_devclass; 96273257Srpaulo 97273257SrpauloDRIVER_MODULE(ti_wdt, simplebus, ti_wdt_driver, ti_wdt_devclass, 0, 0); 98273257Srpaulo 99273257Srpaulostatic volatile __inline uint32_t 100273257Srpauloti_wdt_reg_read(struct ti_wdt_softc *sc, uint32_t reg) 101273257Srpaulo{ 102273257Srpaulo return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg)); 103273257Srpaulo} 104273257Srpaulo 105273257Srpaulostatic __inline void 106273257Srpauloti_wdt_reg_write(struct ti_wdt_softc *sc, uint32_t reg, uint32_t val) 107273257Srpaulo{ 108273257Srpaulo bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val); 109273257Srpaulo} 110273257Srpaulo 111273257Srpaulo/* 112273257Srpaulo * Wait for the write to a specific synchronised register to complete. 113273257Srpaulo */ 114273257Srpaulostatic __inline void 115273257Srpauloti_wdt_reg_wait(struct ti_wdt_softc *sc, uint32_t bit) 116273257Srpaulo{ 117273257Srpaulo while (ti_wdt_reg_read(sc, TI_WDT_WWPS) & bit) 118273257Srpaulo DELAY(10); 119273257Srpaulo 120273257Srpaulo} 121273257Srpaulo 122273257Srpaulostatic __inline void 123273257Srpauloti_wdt_disable(struct ti_wdt_softc *sc) 124273257Srpaulo{ 125273257Srpaulo DPRINTF("disabling watchdog %p\n", sc); 126273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xAAAA); 127273257Srpaulo ti_wdt_reg_wait(sc, TI_W_PEND_WSPR); 128273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x5555); 129273257Srpaulo ti_wdt_reg_wait(sc, TI_W_PEND_WSPR); 130273257Srpaulo} 131273257Srpaulo 132273257Srpaulostatic __inline void 133273257Srpauloti_wdt_enable(struct ti_wdt_softc *sc) 134273257Srpaulo{ 135273257Srpaulo DPRINTF("enabling watchdog %p\n", sc); 136273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xBBBB); 137273257Srpaulo ti_wdt_reg_wait(sc, TI_W_PEND_WSPR); 138273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x4444); 139273257Srpaulo ti_wdt_reg_wait(sc, TI_W_PEND_WSPR); 140273257Srpaulo} 141273257Srpaulo 142273257Srpaulostatic int 143273257Srpauloti_wdt_probe(device_t dev) 144273257Srpaulo{ 145273257Srpaulo 146273257Srpaulo if (!ofw_bus_status_okay(dev)) 147273257Srpaulo return (ENXIO); 148273257Srpaulo if (ofw_bus_is_compatible(dev, "ti,omap3-wdt")) { 149273257Srpaulo device_set_desc(dev, "TI Watchdog Timer"); 150273257Srpaulo return (BUS_PROBE_DEFAULT); 151273257Srpaulo } 152273257Srpaulo 153273257Srpaulo return (ENXIO); 154273257Srpaulo} 155273257Srpaulo 156273257Srpaulostatic int 157273257Srpauloti_wdt_attach(device_t dev) 158273257Srpaulo{ 159273257Srpaulo struct ti_wdt_softc *sc; 160273257Srpaulo int rid; 161273257Srpaulo 162273257Srpaulo sc = device_get_softc(dev); 163273257Srpaulo rid = 0; 164273257Srpaulo mtx_init(&sc->sc_mtx, "TI WDT", NULL, MTX_DEF); 165273257Srpaulo sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 166273257Srpaulo RF_ACTIVE); 167273257Srpaulo if (sc->sc_mem_res == NULL) { 168273257Srpaulo device_printf(dev, "could not allocate memory resource\n"); 169273257Srpaulo return (ENXIO); 170273257Srpaulo } 171273257Srpaulo sc->sc_bt = rman_get_bustag(sc->sc_mem_res); 172273257Srpaulo sc->sc_bh = rman_get_bushandle(sc->sc_mem_res); 173273257Srpaulo sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 174273257Srpaulo if (sc->sc_irq_res == NULL) { 175273257Srpaulo device_printf(dev, "could not allocate interrupt resource\n"); 176273257Srpaulo ti_wdt_detach(dev); 177273257Srpaulo return (ENXIO); 178273257Srpaulo } 179273257Srpaulo if (bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE | INTR_TYPE_MISC, 180273257Srpaulo NULL, ti_wdt_intr, sc, &sc->sc_intr) != 0) { 181273257Srpaulo device_printf(dev, 182273257Srpaulo "unable to setup the interrupt handler\n"); 183273257Srpaulo ti_wdt_detach(dev); 184273257Srpaulo return (ENXIO); 185273257Srpaulo } 186273257Srpaulo /* Reset, enable interrupts and stop the watchdog. */ 187273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WDSC, 188273257Srpaulo ti_wdt_reg_read(sc, TI_WDT_WDSC) | TI_WDSC_SR); 189273257Srpaulo while (ti_wdt_reg_read(sc, TI_WDT_WDSC) & TI_WDSC_SR) 190273257Srpaulo DELAY(10); 191273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WIRQENSET, TI_IRQ_EN_OVF | TI_IRQ_EN_DLY); 192273257Srpaulo ti_wdt_disable(sc); 193273257Srpaulo if (bootverbose) 194273257Srpaulo device_printf(dev, "revision: 0x%x\n", 195273257Srpaulo ti_wdt_reg_read(sc, TI_WDT_WIDR)); 196273257Srpaulo sc->sc_ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ti_wdt_event, sc, 197273257Srpaulo 0); 198273257Srpaulo 199273257Srpaulo return (0); 200273257Srpaulo} 201273257Srpaulo 202273257Srpaulostatic int 203273257Srpauloti_wdt_detach(device_t dev) 204273257Srpaulo{ 205273257Srpaulo struct ti_wdt_softc *sc; 206273257Srpaulo 207273257Srpaulo sc = device_get_softc(dev); 208273257Srpaulo if (sc->sc_ev_tag) 209273257Srpaulo EVENTHANDLER_DEREGISTER(watchdog_list, sc->sc_ev_tag); 210273257Srpaulo if (sc->sc_intr) 211273257Srpaulo bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr); 212273257Srpaulo if (sc->sc_irq_res) 213273257Srpaulo bus_release_resource(dev, SYS_RES_IRQ, 214273257Srpaulo rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 215273257Srpaulo if (sc->sc_mem_res) 216273257Srpaulo bus_release_resource(dev, SYS_RES_MEMORY, 217273257Srpaulo rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 218273257Srpaulo 219273257Srpaulo return (0); 220273257Srpaulo} 221273257Srpaulo 222273257Srpaulostatic void 223273257Srpauloti_wdt_intr(void *arg) 224273257Srpaulo{ 225273257Srpaulo struct ti_wdt_softc *sc; 226273257Srpaulo 227273257Srpaulo sc = arg; 228273257Srpaulo DPRINTF("interrupt %p", sc); 229273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WIRQSTAT, TI_IRQ_EV_OVF | TI_IRQ_EV_DLY); 230273257Srpaulo /* TODO: handle interrupt */ 231273257Srpaulo} 232273257Srpaulo 233273257Srpaulostatic void 234273257Srpauloti_wdt_event(void *arg, unsigned int cmd, int *error) 235273257Srpaulo{ 236273257Srpaulo struct ti_wdt_softc *sc; 237273257Srpaulo uint8_t s; 238273257Srpaulo uint32_t wldr; 239273257Srpaulo uint32_t ptv; 240273257Srpaulo 241273257Srpaulo sc = arg; 242273257Srpaulo ti_wdt_disable(sc); 243273257Srpaulo if (cmd == WD_TO_NEVER) { 244273257Srpaulo *error = 0; 245273257Srpaulo return; 246273257Srpaulo } 247273257Srpaulo DPRINTF("cmd 0x%x\n", cmd); 248273257Srpaulo cmd &= WD_INTERVAL; 249273257Srpaulo if (cmd < WD_TO_1SEC) { 250273257Srpaulo *error = EINVAL; 251273257Srpaulo return; 252273257Srpaulo } 253273257Srpaulo s = 1 << (cmd - WD_TO_1SEC); 254273257Srpaulo DPRINTF("seconds %u\n", s); 255273257Srpaulo /* 256273257Srpaulo * Leave the pre-scaler with its default values: 257273257Srpaulo * PTV = 0 == 2**0 == 1 258273257Srpaulo * PRE = 1 (enabled) 259273257Srpaulo * 260273257Srpaulo * Compute the load register value assuming a 32kHz clock. 261273257Srpaulo * See OVF_Rate in the WDT section of the AM335x TRM. 262273257Srpaulo */ 263273257Srpaulo ptv = 0; 264273257Srpaulo wldr = 0xffffffff - (s * (32768 / (1 << ptv))) + 1; 265273257Srpaulo DPRINTF("wldr 0x%x\n", wldr); 266273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WLDR, wldr); 267273257Srpaulo /* 268273257Srpaulo * Trigger a timer reload. 269273257Srpaulo */ 270273257Srpaulo ti_wdt_reg_write(sc, TI_WDT_WTGR, 271273257Srpaulo ti_wdt_reg_read(sc, TI_WDT_WTGR) + 1); 272273257Srpaulo ti_wdt_reg_wait(sc, TI_W_PEND_WTGR); 273273257Srpaulo ti_wdt_enable(sc); 274273257Srpaulo *error = 0; 275273257Srpaulo} 276