ti_sdhci.c revision 314503
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/arm/ti/ti_sdhci.c 314503 2017-03-01 18:53:05Z ian $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/gpio.h> 35#include <sys/kernel.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/resource.h> 39#include <sys/rman.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <machine/intr.h> 46 47#include <dev/ofw/ofw_bus.h> 48#include <dev/ofw/ofw_bus_subr.h> 49 50#include <dev/mmc/bridge.h> 51#include <dev/mmc/mmcreg.h> 52#include <dev/mmc/mmcbrvar.h> 53 54#include <dev/sdhci/sdhci.h> 55#include "sdhci_if.h" 56 57#include <arm/ti/ti_cpuid.h> 58#include <arm/ti/ti_prcm.h> 59#include <arm/ti/ti_hwmods.h> 60#include "gpio_if.h" 61 62struct ti_sdhci_softc { 63 device_t dev; 64 device_t gpio_dev; 65 struct resource * mem_res; 66 struct resource * irq_res; 67 void * intr_cookie; 68 struct sdhci_slot slot; 69 clk_ident_t mmchs_clk_id; 70 uint32_t mmchs_reg_off; 71 uint32_t sdhci_reg_off; 72 uint32_t baseclk_hz; 73 uint32_t wp_gpio_pin; 74 uint32_t cmd_and_mode; 75 uint32_t sdhci_clkdiv; 76 boolean_t disable_highspeed; 77 boolean_t force_card_present; 78}; 79 80/* 81 * Table of supported FDT compat strings. 82 * 83 * Note that "ti,mmchs" is our own invention, and should be phased out in favor 84 * of the documented names. 85 * 86 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 87 */ 88static struct ofw_compat_data compat_data[] = { 89 {"ti,omap3-hsmmc", 1}, 90 {"ti,omap4-hsmmc", 1}, 91 {"ti,mmchs", 1}, 92 {NULL, 0}, 93}; 94 95/* 96 * The MMCHS hardware has a few control and status registers at the beginning of 97 * the device's memory map, followed by the standard sdhci register block. 98 * Different SoCs have the register blocks at different offsets from the 99 * beginning of the device. Define some constants to map out the registers we 100 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 101 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 102 */ 103#define OMAP3_MMCHS_REG_OFFSET 0x000 104#define OMAP4_MMCHS_REG_OFFSET 0x100 105#define AM335X_MMCHS_REG_OFFSET 0x100 106#define SDHCI_REG_OFFSET 0x100 107 108#define MMCHS_SYSCONFIG 0x010 109#define MMCHS_SYSCONFIG_RESET (1 << 1) 110#define MMCHS_SYSSTATUS 0x014 111#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 112#define MMCHS_CON 0x02C 113#define MMCHS_CON_DW8 (1 << 5) 114#define MMCHS_CON_DVAL_8_4MS (3 << 9) 115#define MMCHS_CON_OD (1 << 0) 116#define MMCHS_SYSCTL 0x12C 117#define MMCHS_SYSCTL_CLKD_MASK 0x3FF 118#define MMCHS_SYSCTL_CLKD_SHIFT 6 119#define MMCHS_SD_CAPA 0x140 120#define MMCHS_SD_CAPA_VS18 (1 << 26) 121#define MMCHS_SD_CAPA_VS30 (1 << 25) 122#define MMCHS_SD_CAPA_VS33 (1 << 24) 123 124static inline uint32_t 125ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 126{ 127 128 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 129} 130 131static inline void 132ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 133{ 134 135 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 136} 137 138static inline uint32_t 139RD4(struct ti_sdhci_softc *sc, bus_size_t off) 140{ 141 142 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 143} 144 145static inline void 146WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 147{ 148 149 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 150} 151 152static uint8_t 153ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 154{ 155 struct ti_sdhci_softc *sc = device_get_softc(dev); 156 157 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 158} 159 160static uint16_t 161ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 162{ 163 struct ti_sdhci_softc *sc = device_get_softc(dev); 164 uint32_t clkdiv, val32; 165 166 /* 167 * The MMCHS hardware has a non-standard interpretation of the sdclock 168 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 169 * but doesn't split them into low:high fields. Instead they're a 170 * single number in the range 0..1023 and the number is exactly the 171 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 172 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 173 * here extracts the MMCHS representation from the hardware word, cleans 174 * those bits out, applies the 2N adjustment, and plugs the result into 175 * the bit positions for the 2.0 or 3.0 divisor in the returned register 176 * value. The ti_sdhci_write_2() routine performs the opposite 177 * transformation when the SDHCI driver writes to the register. 178 */ 179 if (off == SDHCI_CLOCK_CONTROL) { 180 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 181 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 182 MMCHS_SYSCTL_CLKD_MASK) / 2; 183 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 184 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 185 if (slot->version >= SDHCI_SPEC_300) 186 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 187 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 188 return (val32 & 0xffff); 189 } 190 191 /* 192 * Standard 32-bit handling of command and transfer mode. 193 */ 194 if (off == SDHCI_TRANSFER_MODE) { 195 return (sc->cmd_and_mode >> 16); 196 } else if (off == SDHCI_COMMAND_FLAGS) { 197 return (sc->cmd_and_mode & 0x0000ffff); 198 } 199 200 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 201} 202 203static uint32_t 204ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 205{ 206 struct ti_sdhci_softc *sc = device_get_softc(dev); 207 uint32_t val32; 208 209 val32 = RD4(sc, off); 210 211 /* 212 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 213 * that flag from the returned capabilities. 214 */ 215 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 216 val32 &= ~SDHCI_CAN_DO_HISPD; 217 218 /* 219 * Force the card-present state if necessary. 220 */ 221 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 222 val32 |= SDHCI_CARD_PRESENT; 223 224 return (val32); 225} 226 227static void 228ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 229 uint32_t *data, bus_size_t count) 230{ 231 struct ti_sdhci_softc *sc = device_get_softc(dev); 232 233 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 234} 235 236static void 237ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 238 uint8_t val) 239{ 240 struct ti_sdhci_softc *sc = device_get_softc(dev); 241 uint32_t val32; 242 243 val32 = RD4(sc, off & ~3); 244 val32 &= ~(0xff << (off & 3) * 8); 245 val32 |= (val << (off & 3) * 8); 246 247 WR4(sc, off & ~3, val32); 248} 249 250static void 251ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 252 uint16_t val) 253{ 254 struct ti_sdhci_softc *sc = device_get_softc(dev); 255 uint32_t clkdiv, val32; 256 257 /* 258 * Translate between the hardware and SDHCI 2.0 or 3.0 representations 259 * of the clock divisor. See the comments in ti_sdhci_read_2() for 260 * details. 261 */ 262 if (off == SDHCI_CLOCK_CONTROL) { 263 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 264 if (slot->version >= SDHCI_SPEC_300) 265 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 266 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 267 clkdiv *= 2; 268 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 269 clkdiv = MMCHS_SYSCTL_CLKD_MASK; 270 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 271 val32 &= 0xffff0000; 272 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 273 MMCHS_SYSCTL_CLKD_SHIFT); 274 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 275 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 276 return; 277 } 278 279 /* 280 * Standard 32-bit handling of command and transfer mode. 281 */ 282 if (off == SDHCI_TRANSFER_MODE) { 283 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 284 ((uint32_t)val & 0x0000ffff); 285 return; 286 } else if (off == SDHCI_COMMAND_FLAGS) { 287 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 288 ((uint32_t)val << 16); 289 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 290 return; 291 } 292 293 val32 = RD4(sc, off & ~3); 294 val32 &= ~(0xffff << (off & 3) * 8); 295 val32 |= ((val & 0xffff) << (off & 3) * 8); 296 WR4(sc, off & ~3, val32); 297} 298 299static void 300ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 301 uint32_t val) 302{ 303 struct ti_sdhci_softc *sc = device_get_softc(dev); 304 305 WR4(sc, off, val); 306} 307 308static void 309ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 310 uint32_t *data, bus_size_t count) 311{ 312 struct ti_sdhci_softc *sc = device_get_softc(dev); 313 314 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 315} 316 317static void 318ti_sdhci_intr(void *arg) 319{ 320 struct ti_sdhci_softc *sc = arg; 321 322 sdhci_generic_intr(&sc->slot); 323} 324 325static int 326ti_sdhci_update_ios(device_t brdev, device_t reqdev) 327{ 328 struct ti_sdhci_softc *sc = device_get_softc(brdev); 329 struct sdhci_slot *slot; 330 struct mmc_ios *ios; 331 uint32_t val32, newval32; 332 333 slot = device_get_ivars(reqdev); 334 ios = &slot->host.ios; 335 336 /* 337 * There is an 8-bit-bus bit in the MMCHS control register which, when 338 * set, overrides the 1 vs 4 bit setting in the standard SDHCI 339 * registers. Set that bit first according to whether an 8-bit bus is 340 * requested, then let the standard driver handle everything else. 341 */ 342 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 343 newval32 = val32; 344 345 if (ios->bus_width == bus_width_8) 346 newval32 |= MMCHS_CON_DW8; 347 else 348 newval32 &= ~MMCHS_CON_DW8; 349 350 if (ios->bus_mode == opendrain) 351 newval32 |= MMCHS_CON_OD; 352 else /* if (ios->bus_mode == pushpull) */ 353 newval32 &= ~MMCHS_CON_OD; 354 355 if (newval32 != val32) 356 ti_mmchs_write_4(sc, MMCHS_CON, newval32); 357 358 return (sdhci_generic_update_ios(brdev, reqdev)); 359} 360 361static int 362ti_sdhci_get_ro(device_t brdev, device_t reqdev) 363{ 364 struct ti_sdhci_softc *sc = device_get_softc(brdev); 365 unsigned int readonly = 0; 366 367 /* If a gpio pin is configured, read it. */ 368 if (sc->gpio_dev != NULL) { 369 GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); 370 } 371 372 return (readonly); 373} 374 375static int 376ti_sdhci_detach(device_t dev) 377{ 378 379 return (EBUSY); 380} 381 382static void 383ti_sdhci_hw_init(device_t dev) 384{ 385 struct ti_sdhci_softc *sc = device_get_softc(dev); 386 uint32_t regval; 387 unsigned long timeout; 388 389 /* Enable the controller and interface/functional clocks */ 390 if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) { 391 device_printf(dev, "Error: failed to enable MMC clock\n"); 392 return; 393 } 394 395 /* Get the frequency of the source clock */ 396 if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id, 397 &sc->baseclk_hz) != 0) { 398 device_printf(dev, "Error: failed to get source clock freq\n"); 399 return; 400 } 401 402 /* Issue a softreset to the controller */ 403 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 404 timeout = 1000; 405 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 406 MMCHS_SYSSTATUS_RESETDONE)) { 407 if (--timeout == 0) { 408 device_printf(dev, 409 "Error: Controller reset operation timed out\n"); 410 break; 411 } 412 DELAY(100); 413 } 414 415 /* 416 * Reset the command and data state machines and also other aspects of 417 * the controller such as bus clock and power. 418 * 419 * If we read the software reset register too fast after writing it we 420 * can get back a zero that means the reset hasn't started yet rather 421 * than that the reset is complete. Per TI recommendations, work around 422 * it by reading until we see the reset bit asserted, then read until 423 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk 424 * so that the main sdhci driver uses this same logic in its resets. 425 */ 426 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 427 timeout = 10000; 428 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 429 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) { 430 if (--timeout == 0) { 431 break; 432 } 433 DELAY(1); 434 } 435 timeout = 10000; 436 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 437 SDHCI_RESET_ALL)) { 438 if (--timeout == 0) { 439 device_printf(dev, 440 "Error: Software reset operation timed out\n"); 441 break; 442 } 443 DELAY(100); 444 } 445 446 /* 447 * The attach() routine has examined fdt data and set flags in 448 * slot.host.caps to reflect what voltages we can handle. Set those 449 * values in the CAPA register. The manual says that these values can 450 * only be set once, "before initialization" whatever that means, and 451 * that they survive a reset. So maybe doing this will be a no-op if 452 * u-boot has already initialized the hardware. 453 */ 454 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 455 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 456 regval |= MMCHS_SD_CAPA_VS18; 457 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 458 regval |= MMCHS_SD_CAPA_VS30; 459 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 460 461 /* Set initial host configuration (1-bit, std speed, pwr off). */ 462 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 463 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 464 465 /* Set the initial controller configuration. */ 466 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 467} 468 469static int 470ti_sdhci_attach(device_t dev) 471{ 472 struct ti_sdhci_softc *sc = device_get_softc(dev); 473 int rid, err; 474 pcell_t prop; 475 phandle_t node; 476 477 sc->dev = dev; 478 479 /* 480 * Get the MMCHS device id from FDT. If it's not there use the newbus 481 * unit number (which will work as long as the devices are in order and 482 * none are skipped in the fdt). Note that this is a property we made 483 * up and added in freebsd, it doesn't exist in the published bindings. 484 */ 485 node = ofw_bus_get_node(dev); 486 sc->mmchs_clk_id = ti_hwmods_get_clock(dev); 487 if (sc->mmchs_clk_id == INVALID_CLK_IDENT) { 488 device_printf(dev, "failed to get clock based on hwmods property\n"); 489 } 490 491 /* 492 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 493 * device, and only 1p8v on other devices unless an external transceiver 494 * is used. The only way we could know about a transceiver is fdt data. 495 * Note that we have to do this before calling ti_sdhci_hw_init() so 496 * that it can set the right values in the CAPA register, which can only 497 * be done once and never reset. 498 */ 499 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 500 if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) { 501 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 502 } 503 504 /* 505 * See if we've got a GPIO-based write detect pin. This is not the 506 * standard documented property for this, we added it in freebsd. 507 */ 508 if ((OF_getencprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) 509 sc->wp_gpio_pin = 0xffffffff; 510 else 511 sc->wp_gpio_pin = prop; 512 513 if (sc->wp_gpio_pin != 0xffffffff) { 514 sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 515 if (sc->gpio_dev == NULL) 516 device_printf(dev, "Error: No GPIO device, " 517 "Write Protect pin will not function\n"); 518 else 519 GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, 520 GPIO_PIN_INPUT); 521 } 522 523 /* 524 * Set the offset from the device's memory start to the MMCHS registers. 525 * Also for OMAP4 disable high speed mode due to erratum ID i626. 526 */ 527 switch (ti_chip()) { 528#ifdef SOC_OMAP4 529 case CHIP_OMAP_4: 530 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 531 sc->disable_highspeed = true; 532 break; 533#endif 534#ifdef SOC_TI_AM335X 535 case CHIP_AM335X: 536 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 537 break; 538#endif 539 default: 540 panic("Unknown OMAP device\n"); 541 } 542 543 /* 544 * The standard SDHCI registers are at a fixed offset (the same on all 545 * SoCs) beyond the MMCHS registers. 546 */ 547 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 548 549 /* Resource setup. */ 550 rid = 0; 551 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 552 RF_ACTIVE); 553 if (!sc->mem_res) { 554 device_printf(dev, "cannot allocate memory window\n"); 555 err = ENXIO; 556 goto fail; 557 } 558 559 rid = 0; 560 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 561 RF_ACTIVE); 562 if (!sc->irq_res) { 563 device_printf(dev, "cannot allocate interrupt\n"); 564 err = ENXIO; 565 goto fail; 566 } 567 568 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 569 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 570 device_printf(dev, "cannot setup interrupt handler\n"); 571 err = ENXIO; 572 goto fail; 573 } 574 575 /* Initialise the MMCHS hardware. */ 576 ti_sdhci_hw_init(dev); 577 578 /* 579 * The capabilities register can only express base clock frequencies in 580 * the range of 0-63MHz for a v2.0 controller. Since our clock runs 581 * faster than that, the hardware sets the frequency to zero in the 582 * register. When the register contains zero, the sdhci driver expects 583 * slot.max_clk to already have the right value in it. 584 */ 585 sc->slot.max_clk = sc->baseclk_hz; 586 587 /* 588 * The MMCHS timeout counter is based on the output sdclock. Tell the 589 * sdhci driver to recalculate the timeout clock whenever the output 590 * sdclock frequency changes. 591 */ 592 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 593 594 /* 595 * The MMCHS hardware shifts the 136-bit response data (in violation of 596 * the spec), so tell the sdhci driver not to do the same in software. 597 */ 598 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 599 600 /* 601 * Reset bits are broken, have to wait to see the bits asserted 602 * before waiting to see them de-asserted. 603 */ 604 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED; 605 606 /* 607 * DMA is not really broken, I just haven't implemented it yet. 608 */ 609 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 610 611 /* 612 * Set up the hardware and go. Note that this sets many of the 613 * slot.host.* fields, so we have to do this before overriding any of 614 * those values based on fdt data, below. 615 */ 616 sdhci_init_slot(dev, &sc->slot, 0); 617 618 /* 619 * The SDHCI controller doesn't realize it, but we can support 8-bit 620 * even though we're not a v3.0 controller. If there's an fdt bus-width 621 * property, honor it. 622 */ 623 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 624 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 625 MMC_CAP_8_BIT_DATA); 626 switch (prop) { 627 case 8: 628 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 629 /* FALLTHROUGH */ 630 case 4: 631 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 632 break; 633 case 1: 634 break; 635 default: 636 device_printf(dev, "Bad bus-width value %u\n", prop); 637 break; 638 } 639 } 640 641 /* 642 * If the slot is flagged with the non-removable property, set our flag 643 * to always force the SDHCI_CARD_PRESENT bit on. 644 */ 645 node = ofw_bus_get_node(dev); 646 if (OF_hasprop(node, "non-removable")) 647 sc->force_card_present = true; 648 649 bus_generic_probe(dev); 650 bus_generic_attach(dev); 651 652 sdhci_start_slot(&sc->slot); 653 654 return (0); 655 656fail: 657 if (sc->intr_cookie) 658 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 659 if (sc->irq_res) 660 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 661 if (sc->mem_res) 662 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 663 664 return (err); 665} 666 667static int 668ti_sdhci_probe(device_t dev) 669{ 670 671 if (!ofw_bus_status_okay(dev)) 672 return (ENXIO); 673 674 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 675 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 676 return (BUS_PROBE_DEFAULT); 677 } 678 679 return (ENXIO); 680} 681 682static device_method_t ti_sdhci_methods[] = { 683 /* Device interface */ 684 DEVMETHOD(device_probe, ti_sdhci_probe), 685 DEVMETHOD(device_attach, ti_sdhci_attach), 686 DEVMETHOD(device_detach, ti_sdhci_detach), 687 688 /* Bus interface */ 689 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 690 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 691 DEVMETHOD(bus_print_child, bus_generic_print_child), 692 693 /* MMC bridge interface */ 694 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 695 DEVMETHOD(mmcbr_request, sdhci_generic_request), 696 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 697 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 698 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 699 700 /* SDHCI registers accessors */ 701 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 702 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 703 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 704 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 705 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 706 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 707 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 708 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 709 710 DEVMETHOD_END 711}; 712 713static devclass_t ti_sdhci_devclass; 714 715static driver_t ti_sdhci_driver = { 716 "sdhci_ti", 717 ti_sdhci_methods, 718 sizeof(struct ti_sdhci_softc), 719}; 720 721DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 722MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 723DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL); 724MODULE_DEPEND(sdhci_ti, mmc, 1, 1, 1); 725