ti_sdhci.c revision 273052
1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: head/sys/arm/ti/ti_sdhci.c 273052 2014-10-13 16:33:08Z andrew $"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bus.h> 34#include <sys/gpio.h> 35#include <sys/kernel.h> 36#include <sys/malloc.h> 37#include <sys/module.h> 38#include <sys/resource.h> 39#include <sys/rman.h> 40#include <sys/sysctl.h> 41#include <sys/taskqueue.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <machine/intr.h> 46 47#include <dev/fdt/fdt_common.h> 48#include <dev/ofw/ofw_bus.h> 49#include <dev/ofw/ofw_bus_subr.h> 50 51#include <dev/mmc/bridge.h> 52#include <dev/mmc/mmcreg.h> 53#include <dev/mmc/mmcbrvar.h> 54 55#include <dev/sdhci/sdhci.h> 56#include "sdhci_if.h" 57 58#include <arm/ti/ti_cpuid.h> 59#include <arm/ti/ti_prcm.h> 60#include "gpio_if.h" 61 62struct ti_sdhci_softc { 63 device_t dev; 64 device_t gpio_dev; 65 struct resource * mem_res; 66 struct resource * irq_res; 67 void * intr_cookie; 68 struct sdhci_slot slot; 69 uint32_t mmchs_device_id; 70 uint32_t mmchs_reg_off; 71 uint32_t sdhci_reg_off; 72 uint32_t baseclk_hz; 73 uint32_t wp_gpio_pin; 74 uint32_t cmd_and_mode; 75 uint32_t sdhci_clkdiv; 76 boolean_t disable_highspeed; 77 boolean_t force_card_present; 78}; 79 80/* 81 * Table of supported FDT compat strings. 82 * 83 * Note that "ti,mmchs" is our own invention, and should be phased out in favor 84 * of the documented names. 85 * 86 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 87 */ 88static struct ofw_compat_data compat_data[] = { 89 {"ti,omap3-hsmmc", 1}, 90 {"ti,omap4-hsmmc", 1}, 91 {"ti,mmchs", 1}, 92 {NULL, 0}, 93}; 94 95/* 96 * The MMCHS hardware has a few control and status registers at the beginning of 97 * the device's memory map, followed by the standard sdhci register block. 98 * Different SoCs have the register blocks at different offsets from the 99 * beginning of the device. Define some constants to map out the registers we 100 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 101 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 102 */ 103#define OMAP3_MMCHS_REG_OFFSET 0x000 104#define OMAP4_MMCHS_REG_OFFSET 0x100 105#define AM335X_MMCHS_REG_OFFSET 0x100 106#define SDHCI_REG_OFFSET 0x100 107 108#define MMCHS_SYSCONFIG 0x010 109#define MMCHS_SYSCONFIG_RESET (1 << 1) 110#define MMCHS_SYSSTATUS 0x014 111#define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 112#define MMCHS_CON 0x02C 113#define MMCHS_CON_DW8 (1 << 5) 114#define MMCHS_CON_DVAL_8_4MS (3 << 9) 115#define MMCHS_SYSCTL 0x12C 116#define MMCHS_SYSCTL_CLKD_MASK 0x3FF 117#define MMCHS_SYSCTL_CLKD_SHIFT 6 118#define MMCHS_SD_CAPA 0x140 119#define MMCHS_SD_CAPA_VS18 (1 << 26) 120#define MMCHS_SD_CAPA_VS30 (1 << 25) 121#define MMCHS_SD_CAPA_VS33 (1 << 24) 122 123static inline uint32_t 124ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 125{ 126 127 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 128} 129 130static inline void 131ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 132{ 133 134 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 135} 136 137static inline uint32_t 138RD4(struct ti_sdhci_softc *sc, bus_size_t off) 139{ 140 141 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 142} 143 144static inline void 145WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 146{ 147 148 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 149} 150 151static uint8_t 152ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 153{ 154 struct ti_sdhci_softc *sc = device_get_softc(dev); 155 156 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 157} 158 159static uint16_t 160ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 161{ 162 struct ti_sdhci_softc *sc = device_get_softc(dev); 163 uint32_t clkdiv, val32; 164 165 /* 166 * The MMCHS hardware has a non-standard interpretation of the sdclock 167 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 168 * but doesn't split them into low:high fields. Instead they're a 169 * single number in the range 0..1023 and the number is exactly the 170 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 171 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 172 * here extracts the MMCHS representation from the hardware word, cleans 173 * those bits out, applies the 2N adjustment, and plugs the result into 174 * the bit positions for the 2.0 or 3.0 divisor in the returned register 175 * value. The ti_sdhci_write_2() routine performs the opposite 176 * transformation when the SDHCI driver writes to the register. 177 */ 178 if (off == SDHCI_CLOCK_CONTROL) { 179 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 180 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 181 MMCHS_SYSCTL_CLKD_MASK) / 2; 182 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 183 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 184 if (slot->version >= SDHCI_SPEC_300) 185 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 186 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 187 return (val32 & 0xffff); 188 } 189 190 /* 191 * Standard 32-bit handling of command and transfer mode. 192 */ 193 if (off == SDHCI_TRANSFER_MODE) { 194 return (sc->cmd_and_mode >> 16); 195 } else if (off == SDHCI_COMMAND_FLAGS) { 196 return (sc->cmd_and_mode & 0x0000ffff); 197 } 198 199 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 200} 201 202static uint32_t 203ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 204{ 205 struct ti_sdhci_softc *sc = device_get_softc(dev); 206 uint32_t val32; 207 208 val32 = RD4(sc, off); 209 210 /* 211 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 212 * that flag from the returned capabilities. 213 */ 214 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 215 val32 &= ~SDHCI_CAN_DO_HISPD; 216 217 /* 218 * Force the card-present state if necessary. 219 */ 220 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 221 val32 |= SDHCI_CARD_PRESENT; 222 223 return (val32); 224} 225 226static void 227ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 228 uint32_t *data, bus_size_t count) 229{ 230 struct ti_sdhci_softc *sc = device_get_softc(dev); 231 232 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 233} 234 235static void 236ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 237 uint8_t val) 238{ 239 struct ti_sdhci_softc *sc = device_get_softc(dev); 240 uint32_t val32; 241 242 val32 = RD4(sc, off & ~3); 243 val32 &= ~(0xff << (off & 3) * 8); 244 val32 |= (val << (off & 3) * 8); 245 246 WR4(sc, off & ~3, val32); 247} 248 249static void 250ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 251 uint16_t val) 252{ 253 struct ti_sdhci_softc *sc = device_get_softc(dev); 254 uint32_t clkdiv, val32; 255 256 /* 257 * Translate between the hardware and SDHCI 2.0 or 3.0 representations 258 * of the clock divisor. See the comments in ti_sdhci_read_2() for 259 * details. 260 */ 261 if (off == SDHCI_CLOCK_CONTROL) { 262 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 263 if (slot->version >= SDHCI_SPEC_300) 264 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 265 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 266 clkdiv *= 2; 267 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 268 clkdiv = MMCHS_SYSCTL_CLKD_MASK; 269 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 270 val32 &= 0xffff0000; 271 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 272 MMCHS_SYSCTL_CLKD_SHIFT); 273 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 274 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 275 return; 276 } 277 278 /* 279 * Standard 32-bit handling of command and transfer mode. 280 */ 281 if (off == SDHCI_TRANSFER_MODE) { 282 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 283 ((uint32_t)val & 0x0000ffff); 284 return; 285 } else if (off == SDHCI_COMMAND_FLAGS) { 286 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 287 ((uint32_t)val << 16); 288 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 289 return; 290 } 291 292 val32 = RD4(sc, off & ~3); 293 val32 &= ~(0xffff << (off & 3) * 8); 294 val32 |= ((val & 0xffff) << (off & 3) * 8); 295 WR4(sc, off & ~3, val32); 296} 297 298static void 299ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 300 uint32_t val) 301{ 302 struct ti_sdhci_softc *sc = device_get_softc(dev); 303 304 WR4(sc, off, val); 305} 306 307static void 308ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 309 uint32_t *data, bus_size_t count) 310{ 311 struct ti_sdhci_softc *sc = device_get_softc(dev); 312 313 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 314} 315 316static void 317ti_sdhci_intr(void *arg) 318{ 319 struct ti_sdhci_softc *sc = arg; 320 321 sdhci_generic_intr(&sc->slot); 322} 323 324static int 325ti_sdhci_update_ios(device_t brdev, device_t reqdev) 326{ 327 struct ti_sdhci_softc *sc = device_get_softc(brdev); 328 struct sdhci_slot *slot; 329 struct mmc_ios *ios; 330 uint32_t val32; 331 332 slot = device_get_ivars(reqdev); 333 ios = &slot->host.ios; 334 335 /* 336 * There is an 8-bit-bus bit in the MMCHS control register which, when 337 * set, overrides the 1 vs 4 bit setting in the standard SDHCI 338 * registers. Set that bit first according to whether an 8-bit bus is 339 * requested, then let the standard driver handle everything else. 340 */ 341 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 342 if (ios->bus_width == bus_width_8) 343 ti_mmchs_write_4(sc, MMCHS_CON, val32 | MMCHS_CON_DW8); 344 else 345 ti_mmchs_write_4(sc, MMCHS_CON, val32 & ~MMCHS_CON_DW8); 346 347 return (sdhci_generic_update_ios(brdev, reqdev)); 348} 349 350static int 351ti_sdhci_get_ro(device_t brdev, device_t reqdev) 352{ 353 struct ti_sdhci_softc *sc = device_get_softc(brdev); 354 unsigned int readonly = 0; 355 356 /* If a gpio pin is configured, read it. */ 357 if (sc->gpio_dev != NULL) { 358 GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); 359 } 360 361 return (readonly); 362} 363 364static int 365ti_sdhci_detach(device_t dev) 366{ 367 368 return (EBUSY); 369} 370 371static void 372ti_sdhci_hw_init(device_t dev) 373{ 374 struct ti_sdhci_softc *sc = device_get_softc(dev); 375 clk_ident_t clk; 376 uint32_t regval; 377 unsigned long timeout; 378 379 /* Enable the controller and interface/functional clocks */ 380 clk = MMC0_CLK + sc->mmchs_device_id; 381 if (ti_prcm_clk_enable(clk) != 0) { 382 device_printf(dev, "Error: failed to enable MMC clock\n"); 383 return; 384 } 385 386 /* Get the frequency of the source clock */ 387 if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) { 388 device_printf(dev, "Error: failed to get source clock freq\n"); 389 return; 390 } 391 392 /* Issue a softreset to the controller */ 393 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 394 timeout = 1000; 395 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & MMCHS_SYSSTATUS_RESETDONE)) { 396 if (--timeout == 0) { 397 device_printf(dev, "Error: Controller reset operation timed out\n"); 398 break; 399 } 400 DELAY(100); 401 } 402 403 /* Reset both the command and data state machines */ 404 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 405 timeout = 1000; 406 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) { 407 if (--timeout == 0) { 408 device_printf(dev, "Error: Software reset operation timed out\n"); 409 break; 410 } 411 DELAY(100); 412 } 413 414 /* 415 * The attach() routine has examined fdt data and set flags in 416 * slot.host.caps to reflect what voltages we can handle. Set those 417 * values in the CAPA register. The manual says that these values can 418 * only be set once, "before initialization" whatever that means, and 419 * that they survive a reset. So maybe doing this will be a no-op if 420 * u-boot has already initialized the hardware. 421 */ 422 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 423 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 424 regval |= MMCHS_SD_CAPA_VS18; 425 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 426 regval |= MMCHS_SD_CAPA_VS30; 427 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 428 429 /* Set initial host configuration (1-bit, std speed, pwr off). */ 430 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 431 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 432 433 /* Set the initial controller configuration. */ 434 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 435} 436 437static int 438ti_sdhci_attach(device_t dev) 439{ 440 struct ti_sdhci_softc *sc = device_get_softc(dev); 441 int rid, err; 442 pcell_t prop; 443 phandle_t node; 444 445 sc->dev = dev; 446 447 /* 448 * Get the MMCHS device id from FDT. If it's not there use the newbus 449 * unit number (which will work as long as the devices are in order and 450 * none are skipped in the fdt). Note that this is a property we made 451 * up and added in freebsd, it doesn't exist in the published bindings. 452 */ 453 node = ofw_bus_get_node(dev); 454 if ((OF_getprop(node, "mmchs-device-id", &prop, sizeof(prop))) <= 0) { 455 sc->mmchs_device_id = device_get_unit(dev); 456 device_printf(dev, "missing mmchs-device-id attribute in FDT, " 457 "using unit number (%d)", sc->mmchs_device_id); 458 } else 459 sc->mmchs_device_id = fdt32_to_cpu(prop); 460 461 /* 462 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 463 * device, and only 1p8v on other devices unless an external transceiver 464 * is used. The only way we could know about a transceiver is fdt data. 465 * Note that we have to do this before calling ti_sdhci_hw_init() so 466 * that it can set the right values in the CAPA register, which can only 467 * be done once and never reset. 468 */ 469 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 470 if (sc->mmchs_device_id == 0 || OF_hasprop(node, "ti,dual-volt")) { 471 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 472 } 473 474 /* 475 * See if we've got a GPIO-based write detect pin. This is not the 476 * standard documented property for this, we added it in freebsd. 477 */ 478 if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) 479 sc->wp_gpio_pin = 0xffffffff; 480 else 481 sc->wp_gpio_pin = fdt32_to_cpu(prop); 482 483 if (sc->wp_gpio_pin != 0xffffffff) { 484 sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 485 if (sc->gpio_dev == NULL) 486 device_printf(dev, "Error: No GPIO device, " 487 "Write Protect pin will not function\n"); 488 else 489 GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, 490 GPIO_PIN_INPUT); 491 } 492 493 /* 494 * Set the offset from the device's memory start to the MMCHS registers. 495 * Also for OMAP4 disable high speed mode due to erratum ID i626. 496 */ 497 switch (ti_chip()) { 498#ifdef SOC_OMAP4 499 case CHIP_OMAP_4: 500 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 501 sc->disable_highspeed = true; 502 break; 503#endif 504#ifdef SOC_TI_AM335X 505 case CHIP_AM335X: 506 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 507 break; 508#endif 509 default: 510 panic("Unknown OMAP device\n"); 511 } 512 513 /* 514 * The standard SDHCI registers are at a fixed offset (the same on all 515 * SoCs) beyond the MMCHS registers. 516 */ 517 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 518 519 /* Resource setup. */ 520 rid = 0; 521 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 522 RF_ACTIVE); 523 if (!sc->mem_res) { 524 device_printf(dev, "cannot allocate memory window\n"); 525 err = ENXIO; 526 goto fail; 527 } 528 529 rid = 0; 530 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 531 RF_ACTIVE); 532 if (!sc->irq_res) { 533 device_printf(dev, "cannot allocate interrupt\n"); 534 err = ENXIO; 535 goto fail; 536 } 537 538 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 539 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 540 device_printf(dev, "cannot setup interrupt handler\n"); 541 err = ENXIO; 542 goto fail; 543 } 544 545 /* Initialise the MMCHS hardware. */ 546 ti_sdhci_hw_init(dev); 547 548 /* 549 * The capabilities register can only express base clock frequencies in 550 * the range of 0-63MHz for a v2.0 controller. Since our clock runs 551 * faster than that, the hardware sets the frequency to zero in the 552 * register. When the register contains zero, the sdhci driver expects 553 * slot.max_clk to already have the right value in it. 554 */ 555 sc->slot.max_clk = sc->baseclk_hz; 556 557 /* 558 * The MMCHS timeout counter is based on the output sdclock. Tell the 559 * sdhci driver to recalculate the timeout clock whenever the output 560 * sdclock frequency changes. 561 */ 562 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 563 564 /* 565 * The MMCHS hardware shifts the 136-bit response data (in violation of 566 * the spec), so tell the sdhci driver not to do the same in software. 567 */ 568 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 569 570 /* 571 * DMA is not really broken, I just haven't implemented it yet. 572 */ 573 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 574 575 /* 576 * Set up the hardware and go. Note that this sets many of the 577 * slot.host.* fields, so we have to do this before overriding any of 578 * those values based on fdt data, below. 579 */ 580 sdhci_init_slot(dev, &sc->slot, 0); 581 582 /* 583 * The SDHCI controller doesn't realize it, but we can support 8-bit 584 * even though we're not a v3.0 controller. If there's an fdt bus-width 585 * property, honor it. 586 */ 587 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 588 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 589 MMC_CAP_8_BIT_DATA); 590 switch (prop) { 591 case 8: 592 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 593 /* FALLTHROUGH */ 594 case 4: 595 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 596 break; 597 case 1: 598 break; 599 default: 600 device_printf(dev, "Bad bus-width value %u\n", prop); 601 break; 602 } 603 } 604 605 /* 606 * If the slot is flagged with the non-removable property, set our flag 607 * to always force the SDHCI_CARD_PRESENT bit on. 608 */ 609 node = ofw_bus_get_node(dev); 610 if (OF_hasprop(node, "non-removable")) 611 sc->force_card_present = true; 612 613 bus_generic_probe(dev); 614 bus_generic_attach(dev); 615 616 sdhci_start_slot(&sc->slot); 617 618 return (0); 619 620fail: 621 if (sc->intr_cookie) 622 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 623 if (sc->irq_res) 624 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 625 if (sc->mem_res) 626 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 627 628 return (err); 629} 630 631static int 632ti_sdhci_probe(device_t dev) 633{ 634 635 if (!ofw_bus_status_okay(dev)) 636 return (ENXIO); 637 638 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 639 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 640 return (BUS_PROBE_DEFAULT); 641 } 642 643 return (ENXIO); 644} 645 646static device_method_t ti_sdhci_methods[] = { 647 /* Device interface */ 648 DEVMETHOD(device_probe, ti_sdhci_probe), 649 DEVMETHOD(device_attach, ti_sdhci_attach), 650 DEVMETHOD(device_detach, ti_sdhci_detach), 651 652 /* Bus interface */ 653 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 654 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 655 DEVMETHOD(bus_print_child, bus_generic_print_child), 656 657 /* MMC bridge interface */ 658 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 659 DEVMETHOD(mmcbr_request, sdhci_generic_request), 660 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 661 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 662 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 663 664 /* SDHCI registers accessors */ 665 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 666 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 667 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 668 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 669 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 670 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 671 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 672 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 673 674 DEVMETHOD_END 675}; 676 677static devclass_t ti_sdhci_devclass; 678 679static driver_t ti_sdhci_driver = { 680 "sdhci_ti", 681 ti_sdhci_methods, 682 sizeof(struct ti_sdhci_softc), 683}; 684 685DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 686MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 687