if_cpswvar.h revision 310860
1239281Sgonzo/*- 2239281Sgonzo * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3239281Sgonzo * All rights reserved. 4239281Sgonzo * 5239281Sgonzo * Redistribution and use in source and binary forms, with or without 6239281Sgonzo * modification, are permitted provided that the following conditions 7239281Sgonzo * are met: 8239281Sgonzo * 1. Redistributions of source code must retain the above copyright 9239281Sgonzo * notice, this list of conditions and the following disclaimer. 10239281Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11239281Sgonzo * notice, this list of conditions and the following disclaimer in the 12239281Sgonzo * documentation and/or other materials provided with the distribution. 13239281Sgonzo * 14239281Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15239281Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16239281Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17239281Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18239281Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19239281Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20239281Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21239281Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22239281Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23239281Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24239281Sgonzo * SUCH DAMAGE. 25239281Sgonzo * 26239281Sgonzo * $FreeBSD: stable/11/sys/arm/ti/cpsw/if_cpswvar.h 310860 2016-12-30 20:43:00Z loos $ 27239281Sgonzo */ 28239281Sgonzo 29239281Sgonzo#ifndef _IF_CPSWVAR_H 30239281Sgonzo#define _IF_CPSWVAR_H 31239281Sgonzo 32296993Sloos#define CPSW_PORTS 2 33296980Sloos#define CPSW_INTR_COUNT 4 34239281Sgonzo 35239281Sgonzo/* MII BUS */ 36296980Sloos#define CPSW_MIIBUS_RETRIES 5 37296980Sloos#define CPSW_MIIBUS_DELAY 1000 38239281Sgonzo 39296980Sloos#define CPSW_MAX_ALE_ENTRIES 1024 40239281Sgonzo 41296980Sloos#define CPSW_SYSCTL_COUNT 34 42246276Skientzle 43244939Skientzlestruct cpsw_slot { 44246276Skientzle uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */ 45244939Skientzle bus_dmamap_t dmamap; 46297043Sloos struct ifnet *ifp; 47244939Skientzle struct mbuf *mbuf; 48244939Skientzle STAILQ_ENTRY(cpsw_slot) next; 49244939Skientzle}; 50246276SkientzleSTAILQ_HEAD(cpsw_slots, cpsw_slot); 51244939Skientzle 52246276Skientzlestruct cpsw_queue { 53246276Skientzle struct mtx lock; 54246276Skientzle int running; 55310860Sloos int teardown; 56246276Skientzle struct cpsw_slots active; 57246276Skientzle struct cpsw_slots avail; 58246276Skientzle uint32_t queue_adds; /* total bufs added */ 59246276Skientzle uint32_t queue_removes; /* total bufs removed */ 60246276Skientzle uint32_t queue_removes_at_last_tick; /* Used by watchdog */ 61310860Sloos uint32_t queue_restart; 62246276Skientzle int queue_slots; 63246276Skientzle int active_queue_len; 64246276Skientzle int max_active_queue_len; 65246276Skientzle int avail_queue_len; 66246276Skientzle int max_avail_queue_len; 67246276Skientzle int longest_chain; /* Largest # segments in a single packet. */ 68246276Skientzle int hdp_offset; 69246276Skientzle}; 70246276Skientzle 71296993Sloosstruct cpsw_port { 72296993Sloos device_t dev; 73296993Sloos int phy; 74296993Sloos int vlan; 75296993Sloos}; 76296993Sloos 77239281Sgonzostruct cpsw_softc { 78296993Sloos device_t dev; 79296993Sloos int active_slave; 80296993Sloos int debug; 81296993Sloos int dualemac; 82310860Sloos int rx_batch; 83239281Sgonzo phandle_t node; 84246276Skientzle struct bintime attach_uptime; /* system uptime when attach happened. */ 85296993Sloos struct cpsw_port port[2]; 86310857Sloos unsigned coal_us; 87246276Skientzle 88296993Sloos /* RX and TX buffer tracking */ 89296993Sloos struct cpsw_queue rx, tx; 90246276Skientzle 91246276Skientzle /* We expect 1 memory resource and 4 interrupts from the device tree. */ 92296993Sloos int mem_rid; 93283276Sgonzo struct resource *mem_res; 94283276Sgonzo struct resource *irq_res[CPSW_INTR_COUNT]; 95296993Sloos void *ih_cookie[CPSW_INTR_COUNT]; 96239281Sgonzo 97296993Sloos /* An mbuf full of nulls for TX padding. */ 98296993Sloos bus_dmamap_t null_mbuf_dmamap; 99296993Sloos struct mbuf *null_mbuf; 100296993Sloos bus_addr_t null_mbuf_paddr; 101246276Skientzle 102296993Sloos bus_dma_tag_t mbuf_dtag; 103239281Sgonzo 104246276Skientzle struct { 105246276Skientzle int resets; 106246276Skientzle int timer; 107296993Sloos struct callout callout; 108246276Skientzle } watchdog; 109239281Sgonzo 110246276Skientzle /* 64-bit versions of 32-bit hardware statistics counters */ 111246276Skientzle uint64_t shadow_stats[CPSW_SYSCTL_COUNT]; 112239281Sgonzo 113246276Skientzle /* CPPI STATERAM has 512 slots for building TX/RX queues. */ 114246276Skientzle /* TODO: Size here supposedly varies with different versions 115246276Skientzle of the controller. Check DaVinci specs and find a good 116246276Skientzle way to adjust this. One option is to have a separate 117246276Skientzle Device Tree parameter for number slots; another option 118246276Skientzle is to calculate it from the memory size in the device tree. */ 119246276Skientzle struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)]; 120246276Skientzle struct cpsw_slots avail; 121239281Sgonzo}; 122239281Sgonzo 123296993Sloosstruct cpswp_softc { 124296993Sloos device_t dev; 125296993Sloos device_t miibus; 126296993Sloos device_t pdev; 127296993Sloos int media_status; 128296993Sloos int unit; 129296993Sloos int vlan; 130296993Sloos struct bintime init_uptime; /* system uptime when init happened. */ 131296993Sloos struct callout mii_callout; 132296993Sloos struct cpsw_softc *swsc; 133296993Sloos struct ifnet *ifp; 134296993Sloos struct mii_data *mii; 135296993Sloos struct mtx lock; 136296993Sloos uint32_t if_flags; 137296993Sloos uint32_t phy; 138296993Sloos uint32_t phyaccess; 139296993Sloos uint32_t physel; 140296993Sloos}; 141296993Sloos 142239281Sgonzo#endif /*_IF_CPSWVAR_H */ 143