if_cpsw.c revision 315366
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * TI Common Platform Ethernet Switch (CPSW) Driver 30 * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs. 31 * 32 * This controller is documented in the AM335x Technical Reference 33 * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM 34 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM. 35 * 36 * It is basically a single Ethernet port (port 0) wired internally to 37 * a 3-port store-and-forward switch connected to two independent 38 * "sliver" controllers (port 1 and port 2). You can operate the 39 * controller in a variety of different ways by suitably configuring 40 * the slivers and the Address Lookup Engine (ALE) that routes packets 41 * between the ports. 42 * 43 * This code was developed and tested on a BeagleBone with 44 * an AM335x SoC. 45 */ 46 47#include <sys/cdefs.h> 48__FBSDID("$FreeBSD: stable/11/sys/arm/ti/cpsw/if_cpsw.c 315366 2017-03-16 03:41:31Z ian $"); 49 50#include "opt_cpsw.h" 51 52#include <sys/param.h> 53#include <sys/bus.h> 54#include <sys/kernel.h> 55#include <sys/lock.h> 56#include <sys/mbuf.h> 57#include <sys/module.h> 58#include <sys/mutex.h> 59#include <sys/rman.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/sysctl.h> 63 64#include <machine/bus.h> 65#include <machine/resource.h> 66#include <machine/stdarg.h> 67 68#include <net/ethernet.h> 69#include <net/bpf.h> 70#include <net/if.h> 71#include <net/if_dl.h> 72#include <net/if_media.h> 73#include <net/if_types.h> 74 75#include <arm/ti/ti_scm.h> 76#include <arm/ti/am335x/am335x_scm.h> 77 78#include <dev/mii/mii.h> 79#include <dev/mii/miivar.h> 80 81#include <dev/fdt/fdt_common.h> 82#include <dev/ofw/ofw_bus.h> 83#include <dev/ofw/ofw_bus_subr.h> 84 85#ifdef CPSW_ETHERSWITCH 86#include <dev/etherswitch/etherswitch.h> 87#include "etherswitch_if.h" 88#endif 89 90#include "if_cpswreg.h" 91#include "if_cpswvar.h" 92 93#include "miibus_if.h" 94 95/* Device probe/attach/detach. */ 96static int cpsw_probe(device_t); 97static int cpsw_attach(device_t); 98static int cpsw_detach(device_t); 99static int cpswp_probe(device_t); 100static int cpswp_attach(device_t); 101static int cpswp_detach(device_t); 102 103static phandle_t cpsw_get_node(device_t, device_t); 104 105/* Device Init/shutdown. */ 106static int cpsw_shutdown(device_t); 107static void cpswp_init(void *); 108static void cpswp_init_locked(void *); 109static void cpswp_stop_locked(struct cpswp_softc *); 110 111/* Device Suspend/Resume. */ 112static int cpsw_suspend(device_t); 113static int cpsw_resume(device_t); 114 115/* Ioctl. */ 116static int cpswp_ioctl(struct ifnet *, u_long command, caddr_t data); 117 118static int cpswp_miibus_readreg(device_t, int phy, int reg); 119static int cpswp_miibus_writereg(device_t, int phy, int reg, int value); 120static void cpswp_miibus_statchg(device_t); 121 122/* Send/Receive packets. */ 123static void cpsw_intr_rx(void *arg); 124static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *); 125static void cpsw_rx_enqueue(struct cpsw_softc *); 126static void cpswp_start(struct ifnet *); 127static void cpsw_intr_tx(void *); 128static void cpswp_tx_enqueue(struct cpswp_softc *); 129static int cpsw_tx_dequeue(struct cpsw_softc *); 130 131/* Misc interrupts and watchdog. */ 132static void cpsw_intr_rx_thresh(void *); 133static void cpsw_intr_misc(void *); 134static void cpswp_tick(void *); 135static void cpswp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 136static int cpswp_ifmedia_upd(struct ifnet *); 137static void cpsw_tx_watchdog(void *); 138 139/* ALE support */ 140static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *); 141static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *); 142static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *); 143static void cpsw_ale_dump_table(struct cpsw_softc *); 144static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int, int, 145 int); 146static int cpswp_ale_update_addresses(struct cpswp_softc *, int); 147 148/* Statistics and sysctls. */ 149static void cpsw_add_sysctls(struct cpsw_softc *); 150static void cpsw_stats_collect(struct cpsw_softc *); 151static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS); 152 153#ifdef CPSW_ETHERSWITCH 154static etherswitch_info_t *cpsw_getinfo(device_t); 155static int cpsw_getport(device_t, etherswitch_port_t *); 156static int cpsw_setport(device_t, etherswitch_port_t *); 157static int cpsw_getconf(device_t, etherswitch_conf_t *); 158static int cpsw_getvgroup(device_t, etherswitch_vlangroup_t *); 159static int cpsw_setvgroup(device_t, etherswitch_vlangroup_t *); 160static int cpsw_readreg(device_t, int); 161static int cpsw_writereg(device_t, int, int); 162static int cpsw_readphy(device_t, int, int); 163static int cpsw_writephy(device_t, int, int, int); 164#endif 165 166/* 167 * Arbitrary limit on number of segments in an mbuf to be transmitted. 168 * Packets with more segments than this will be defragmented before 169 * they are queued. 170 */ 171#define CPSW_TXFRAGS 16 172 173/* Shared resources. */ 174static device_method_t cpsw_methods[] = { 175 /* Device interface */ 176 DEVMETHOD(device_probe, cpsw_probe), 177 DEVMETHOD(device_attach, cpsw_attach), 178 DEVMETHOD(device_detach, cpsw_detach), 179 DEVMETHOD(device_shutdown, cpsw_shutdown), 180 DEVMETHOD(device_suspend, cpsw_suspend), 181 DEVMETHOD(device_resume, cpsw_resume), 182 /* Bus interface */ 183 DEVMETHOD(bus_add_child, device_add_child_ordered), 184 /* OFW methods */ 185 DEVMETHOD(ofw_bus_get_node, cpsw_get_node), 186#ifdef CPSW_ETHERSWITCH 187 /* etherswitch interface */ 188 DEVMETHOD(etherswitch_getinfo, cpsw_getinfo), 189 DEVMETHOD(etherswitch_readreg, cpsw_readreg), 190 DEVMETHOD(etherswitch_writereg, cpsw_writereg), 191 DEVMETHOD(etherswitch_readphyreg, cpsw_readphy), 192 DEVMETHOD(etherswitch_writephyreg, cpsw_writephy), 193 DEVMETHOD(etherswitch_getport, cpsw_getport), 194 DEVMETHOD(etherswitch_setport, cpsw_setport), 195 DEVMETHOD(etherswitch_getvgroup, cpsw_getvgroup), 196 DEVMETHOD(etherswitch_setvgroup, cpsw_setvgroup), 197 DEVMETHOD(etherswitch_getconf, cpsw_getconf), 198#endif 199 DEVMETHOD_END 200}; 201 202static driver_t cpsw_driver = { 203 "cpswss", 204 cpsw_methods, 205 sizeof(struct cpsw_softc), 206}; 207 208static devclass_t cpsw_devclass; 209 210DRIVER_MODULE(cpswss, simplebus, cpsw_driver, cpsw_devclass, 0, 0); 211 212/* Port/Slave resources. */ 213static device_method_t cpswp_methods[] = { 214 /* Device interface */ 215 DEVMETHOD(device_probe, cpswp_probe), 216 DEVMETHOD(device_attach, cpswp_attach), 217 DEVMETHOD(device_detach, cpswp_detach), 218 /* MII interface */ 219 DEVMETHOD(miibus_readreg, cpswp_miibus_readreg), 220 DEVMETHOD(miibus_writereg, cpswp_miibus_writereg), 221 DEVMETHOD(miibus_statchg, cpswp_miibus_statchg), 222 DEVMETHOD_END 223}; 224 225static driver_t cpswp_driver = { 226 "cpsw", 227 cpswp_methods, 228 sizeof(struct cpswp_softc), 229}; 230 231static devclass_t cpswp_devclass; 232 233#ifdef CPSW_ETHERSWITCH 234DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, etherswitch_devclass, 0, 0); 235MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1); 236#endif 237 238DRIVER_MODULE(cpsw, cpswss, cpswp_driver, cpswp_devclass, 0, 0); 239DRIVER_MODULE(miibus, cpsw, miibus_driver, miibus_devclass, 0, 0); 240MODULE_DEPEND(cpsw, ether, 1, 1, 1); 241MODULE_DEPEND(cpsw, miibus, 1, 1, 1); 242 243#ifdef CPSW_ETHERSWITCH 244static struct cpsw_vlangroups cpsw_vgroups[CPSW_VLANS]; 245#endif 246 247static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 }; 248 249static struct resource_spec irq_res_spec[] = { 250 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 251 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE }, 252 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE }, 253 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE }, 254 { -1, 0 } 255}; 256 257static struct { 258 void (*cb)(void *); 259} cpsw_intr_cb[] = { 260 { cpsw_intr_rx_thresh }, 261 { cpsw_intr_rx }, 262 { cpsw_intr_tx }, 263 { cpsw_intr_misc }, 264}; 265 266/* Number of entries here must match size of stats 267 * array in struct cpswp_softc. */ 268static struct cpsw_stat { 269 int reg; 270 char *oid; 271} cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = { 272 {0x00, "GoodRxFrames"}, 273 {0x04, "BroadcastRxFrames"}, 274 {0x08, "MulticastRxFrames"}, 275 {0x0C, "PauseRxFrames"}, 276 {0x10, "RxCrcErrors"}, 277 {0x14, "RxAlignErrors"}, 278 {0x18, "OversizeRxFrames"}, 279 {0x1c, "RxJabbers"}, 280 {0x20, "ShortRxFrames"}, 281 {0x24, "RxFragments"}, 282 {0x30, "RxOctets"}, 283 {0x34, "GoodTxFrames"}, 284 {0x38, "BroadcastTxFrames"}, 285 {0x3c, "MulticastTxFrames"}, 286 {0x40, "PauseTxFrames"}, 287 {0x44, "DeferredTxFrames"}, 288 {0x48, "CollisionsTxFrames"}, 289 {0x4c, "SingleCollisionTxFrames"}, 290 {0x50, "MultipleCollisionTxFrames"}, 291 {0x54, "ExcessiveCollisions"}, 292 {0x58, "LateCollisions"}, 293 {0x5c, "TxUnderrun"}, 294 {0x60, "CarrierSenseErrors"}, 295 {0x64, "TxOctets"}, 296 {0x68, "RxTx64OctetFrames"}, 297 {0x6c, "RxTx65to127OctetFrames"}, 298 {0x70, "RxTx128to255OctetFrames"}, 299 {0x74, "RxTx256to511OctetFrames"}, 300 {0x78, "RxTx512to1024OctetFrames"}, 301 {0x7c, "RxTx1024upOctetFrames"}, 302 {0x80, "NetOctets"}, 303 {0x84, "RxStartOfFrameOverruns"}, 304 {0x88, "RxMiddleOfFrameOverruns"}, 305 {0x8c, "RxDmaOverruns"} 306}; 307 308/* 309 * Basic debug support. 310 */ 311 312static void 313cpsw_debugf_head(const char *funcname) 314{ 315 int t = (int)(time_second % (24 * 60 * 60)); 316 317 printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname); 318} 319 320static void 321cpsw_debugf(const char *fmt, ...) 322{ 323 va_list ap; 324 325 va_start(ap, fmt); 326 vprintf(fmt, ap); 327 va_end(ap); 328 printf("\n"); 329 330} 331 332#define CPSW_DEBUGF(_sc, a) do { \ 333 if ((_sc)->debug) { \ 334 cpsw_debugf_head(__func__); \ 335 cpsw_debugf a; \ 336 } \ 337} while (0) 338 339/* 340 * Locking macros 341 */ 342#define CPSW_TX_LOCK(sc) do { \ 343 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \ 344 mtx_lock(&(sc)->tx.lock); \ 345} while (0) 346 347#define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock) 348#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED) 349 350#define CPSW_RX_LOCK(sc) do { \ 351 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \ 352 mtx_lock(&(sc)->rx.lock); \ 353} while (0) 354 355#define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock) 356#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED) 357 358#define CPSW_PORT_LOCK(_sc) do { \ 359 mtx_assert(&(_sc)->lock, MA_NOTOWNED); \ 360 mtx_lock(&(_sc)->lock); \ 361} while (0) 362 363#define CPSW_PORT_UNLOCK(_sc) mtx_unlock(&(_sc)->lock) 364#define CPSW_PORT_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->lock, MA_OWNED) 365 366/* 367 * Read/Write macros 368 */ 369#define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg)) 370#define cpsw_write_4(_sc, _reg, _val) \ 371 bus_write_4((_sc)->mem_res, (_reg), (_val)) 372 373#define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16)) 374 375#define cpsw_cpdma_bd_paddr(sc, slot) \ 376 BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset) 377#define cpsw_cpdma_read_bd(sc, slot, val) \ 378 bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 379#define cpsw_cpdma_write_bd(sc, slot, val) \ 380 bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 381#define cpsw_cpdma_write_bd_next(sc, slot, next_slot) \ 382 cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot)) 383#define cpsw_cpdma_write_bd_flags(sc, slot, val) \ 384 bus_write_2(sc->mem_res, slot->bd_offset + 14, val) 385#define cpsw_cpdma_read_bd_flags(sc, slot) \ 386 bus_read_2(sc->mem_res, slot->bd_offset + 14) 387#define cpsw_write_hdp_slot(sc, queue, slot) \ 388 cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot)) 389#define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0)) 390#define cpsw_read_cp(sc, queue) \ 391 cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET) 392#define cpsw_write_cp(sc, queue, val) \ 393 cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val)) 394#define cpsw_write_cp_slot(sc, queue, slot) \ 395 cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot)) 396 397#if 0 398/* XXX temporary function versions for debugging. */ 399static void 400cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 401{ 402 uint32_t reg = queue->hdp_offset; 403 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 404 CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg))); 405 cpsw_write_4(sc, reg, v); 406} 407 408static void 409cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 410{ 411 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 412 CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue))); 413 cpsw_write_cp(sc, queue, v); 414} 415#endif 416 417/* 418 * Expanded dump routines for verbose debugging. 419 */ 420static void 421cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 422{ 423 static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ", 424 "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun", 425 "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1", 426 "Port0"}; 427 struct cpsw_cpdma_bd bd; 428 const char *sep; 429 int i; 430 431 cpsw_cpdma_read_bd(sc, slot, &bd); 432 printf("BD Addr : 0x%08x Next : 0x%08x\n", 433 cpsw_cpdma_bd_paddr(sc, slot), bd.next); 434 printf(" BufPtr: 0x%08x BufLen: 0x%08x\n", bd.bufptr, bd.buflen); 435 printf(" BufOff: 0x%08x PktLen: 0x%08x\n", bd.bufoff, bd.pktlen); 436 printf(" Flags: "); 437 sep = ""; 438 for (i = 0; i < 16; ++i) { 439 if (bd.flags & (1 << (15 - i))) { 440 printf("%s%s", sep, flags[i]); 441 sep = ","; 442 } 443 } 444 printf("\n"); 445 if (slot->mbuf) { 446 printf(" Ether: %14D\n", 447 (char *)(slot->mbuf->m_data), " "); 448 printf(" Packet: %16D\n", 449 (char *)(slot->mbuf->m_data) + 14, " "); 450 } 451} 452 453#define CPSW_DUMP_SLOT(cs, slot) do { \ 454 IF_DEBUG(sc) { \ 455 cpsw_dump_slot(sc, slot); \ 456 } \ 457} while (0) 458 459static void 460cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q) 461{ 462 struct cpsw_slot *slot; 463 int i = 0; 464 int others = 0; 465 466 STAILQ_FOREACH(slot, q, next) { 467 if (i > CPSW_TXFRAGS) 468 ++others; 469 else 470 cpsw_dump_slot(sc, slot); 471 ++i; 472 } 473 if (others) 474 printf(" ... and %d more.\n", others); 475 printf("\n"); 476} 477 478#define CPSW_DUMP_QUEUE(sc, q) do { \ 479 IF_DEBUG(sc) { \ 480 cpsw_dump_queue(sc, q); \ 481 } \ 482} while (0) 483 484static void 485cpsw_init_slots(struct cpsw_softc *sc) 486{ 487 struct cpsw_slot *slot; 488 int i; 489 490 STAILQ_INIT(&sc->avail); 491 492 /* Put the slot descriptors onto the global avail list. */ 493 for (i = 0; i < nitems(sc->_slots); i++) { 494 slot = &sc->_slots[i]; 495 slot->bd_offset = cpsw_cpdma_bd_offset(i); 496 STAILQ_INSERT_TAIL(&sc->avail, slot, next); 497 } 498} 499 500static int 501cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested) 502{ 503 const int max_slots = nitems(sc->_slots); 504 struct cpsw_slot *slot; 505 int i; 506 507 if (requested < 0) 508 requested = max_slots; 509 510 for (i = 0; i < requested; ++i) { 511 slot = STAILQ_FIRST(&sc->avail); 512 if (slot == NULL) 513 return (0); 514 if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) { 515 device_printf(sc->dev, "failed to create dmamap\n"); 516 return (ENOMEM); 517 } 518 STAILQ_REMOVE_HEAD(&sc->avail, next); 519 STAILQ_INSERT_TAIL(&queue->avail, slot, next); 520 ++queue->avail_queue_len; 521 ++queue->queue_slots; 522 } 523 return (0); 524} 525 526static void 527cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 528{ 529 int error; 530 531 if (slot->dmamap) { 532 if (slot->mbuf) 533 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 534 error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap); 535 KASSERT(error == 0, ("Mapping still active")); 536 slot->dmamap = NULL; 537 } 538 if (slot->mbuf) { 539 m_freem(slot->mbuf); 540 slot->mbuf = NULL; 541 } 542} 543 544static void 545cpsw_reset(struct cpsw_softc *sc) 546{ 547 int i; 548 549 callout_stop(&sc->watchdog.callout); 550 551 /* Reset RMII/RGMII wrapper. */ 552 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 553 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 554 ; 555 556 /* Disable TX and RX interrupts for all cores. */ 557 for (i = 0; i < 3; ++i) { 558 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00); 559 cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00); 560 cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00); 561 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00); 562 } 563 564 /* Reset CPSW subsystem. */ 565 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 566 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 567 ; 568 569 /* Reset Sliver port 1 and 2 */ 570 for (i = 0; i < 2; i++) { 571 /* Reset */ 572 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 573 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 574 ; 575 } 576 577 /* Reset DMA controller. */ 578 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 579 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 580 ; 581 582 /* Disable TX & RX DMA */ 583 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0); 584 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0); 585 586 /* Clear all queues. */ 587 for (i = 0; i < 8; i++) { 588 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 589 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 590 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 591 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 592 } 593 594 /* Clear all interrupt Masks */ 595 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 596 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 597} 598 599static void 600cpsw_init(struct cpsw_softc *sc) 601{ 602 struct cpsw_slot *slot; 603 uint32_t reg; 604 605 /* Disable the interrupt pacing. */ 606 reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 607 reg &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 608 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg); 609 610 /* Clear ALE */ 611 cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL); 612 613 /* Enable ALE */ 614 reg = CPSW_ALE_CTL_ENABLE; 615 if (sc->dualemac) 616 reg |= CPSW_ALE_CTL_VLAN_AWARE; 617 cpsw_write_4(sc, CPSW_ALE_CONTROL, reg); 618 619 /* Set Host Port Mapping. */ 620 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 621 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 622 623 /* Initialize ALE: set host port to forwarding(3). */ 624 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 625 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 626 627 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 628 629 /* Enable statistics for ports 0, 1 and 2 */ 630 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 631 632 /* Turn off flow control. */ 633 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 634 635 /* Make IP hdr aligned with 4 */ 636 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2); 637 638 /* Initialize RX Buffer Descriptors */ 639 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0); 640 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 641 642 /* Enable TX & RX DMA */ 643 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 644 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 645 646 /* Enable Interrupts for core 0 */ 647 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF); 648 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF); 649 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF); 650 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 651 652 /* Enable host Error Interrupt */ 653 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3); 654 655 /* Enable interrupts for RX and TX on Channel 0 */ 656 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 657 CPSW_CPDMA_RX_INT(0) | CPSW_CPDMA_RX_INT_THRESH(0)); 658 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 659 660 /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 661 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 662 cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff); 663 664 /* Select MII in GMII_SEL, Internal Delay mode */ 665 //ti_scm_reg_write_4(0x650, 0); 666 667 /* Initialize active queues. */ 668 slot = STAILQ_FIRST(&sc->tx.active); 669 if (slot != NULL) 670 cpsw_write_hdp_slot(sc, &sc->tx, slot); 671 slot = STAILQ_FIRST(&sc->rx.active); 672 if (slot != NULL) 673 cpsw_write_hdp_slot(sc, &sc->rx, slot); 674 cpsw_rx_enqueue(sc); 675 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len); 676 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS); 677 678 /* Activate network interface. */ 679 sc->rx.running = 1; 680 sc->tx.running = 1; 681 sc->watchdog.timer = 0; 682 callout_init(&sc->watchdog.callout, 0); 683 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 684} 685 686/* 687 * 688 * Device Probe, Attach, Detach. 689 * 690 */ 691 692static int 693cpsw_probe(device_t dev) 694{ 695 696 if (!ofw_bus_status_okay(dev)) 697 return (ENXIO); 698 699 if (!ofw_bus_is_compatible(dev, "ti,cpsw")) 700 return (ENXIO); 701 702 device_set_desc(dev, "3-port Switch Ethernet Subsystem"); 703 return (BUS_PROBE_DEFAULT); 704} 705 706static int 707cpsw_intr_attach(struct cpsw_softc *sc) 708{ 709 int i; 710 711 for (i = 0; i < CPSW_INTR_COUNT; i++) { 712 if (bus_setup_intr(sc->dev, sc->irq_res[i], 713 INTR_TYPE_NET | INTR_MPSAFE, NULL, 714 cpsw_intr_cb[i].cb, sc, &sc->ih_cookie[i]) != 0) { 715 return (-1); 716 } 717 } 718 719 return (0); 720} 721 722static void 723cpsw_intr_detach(struct cpsw_softc *sc) 724{ 725 int i; 726 727 for (i = 0; i < CPSW_INTR_COUNT; i++) { 728 if (sc->ih_cookie[i]) { 729 bus_teardown_intr(sc->dev, sc->irq_res[i], 730 sc->ih_cookie[i]); 731 } 732 } 733} 734 735static int 736cpsw_get_fdt_data(struct cpsw_softc *sc, int port) 737{ 738 char *name; 739 int len, phy, vlan; 740 pcell_t phy_id[3], vlan_id; 741 phandle_t child; 742 unsigned long mdio_child_addr; 743 744 /* Find any slave with phy_id */ 745 phy = -1; 746 vlan = -1; 747 for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) { 748 if (OF_getprop_alloc(child, "name", 1, (void **)&name) < 0) 749 continue; 750 if (sscanf(name, "slave@%lx", &mdio_child_addr) != 1) { 751 OF_prop_free(name); 752 continue; 753 } 754 OF_prop_free(name); 755 if (mdio_child_addr != slave_mdio_addr[port]) 756 continue; 757 758 len = OF_getproplen(child, "phy_id"); 759 if (len / sizeof(pcell_t) == 2) { 760 /* Get phy address from fdt */ 761 if (OF_getencprop(child, "phy_id", phy_id, len) > 0) 762 phy = phy_id[1]; 763 } 764 765 len = OF_getproplen(child, "dual_emac_res_vlan"); 766 if (len / sizeof(pcell_t) == 1) { 767 /* Get phy address from fdt */ 768 if (OF_getencprop(child, "dual_emac_res_vlan", 769 &vlan_id, len) > 0) { 770 vlan = vlan_id; 771 } 772 } 773 774 break; 775 } 776 if (phy == -1) 777 return (ENXIO); 778 sc->port[port].phy = phy; 779 sc->port[port].vlan = vlan; 780 781 return (0); 782} 783 784static int 785cpsw_attach(device_t dev) 786{ 787 int error, i; 788 struct cpsw_softc *sc; 789 uint32_t reg; 790 791 sc = device_get_softc(dev); 792 sc->dev = dev; 793 sc->node = ofw_bus_get_node(dev); 794 getbinuptime(&sc->attach_uptime); 795 796 if (OF_getencprop(sc->node, "active_slave", &sc->active_slave, 797 sizeof(sc->active_slave)) <= 0) { 798 sc->active_slave = 0; 799 } 800 if (sc->active_slave > 1) 801 sc->active_slave = 1; 802 803 if (OF_hasprop(sc->node, "dual_emac")) 804 sc->dualemac = 1; 805 806 for (i = 0; i < CPSW_PORTS; i++) { 807 if (!sc->dualemac && i != sc->active_slave) 808 continue; 809 if (cpsw_get_fdt_data(sc, i) != 0) { 810 device_printf(dev, 811 "failed to get PHY address from FDT\n"); 812 return (ENXIO); 813 } 814 } 815 816 /* Initialize mutexes */ 817 mtx_init(&sc->tx.lock, device_get_nameunit(dev), 818 "cpsw TX lock", MTX_DEF); 819 mtx_init(&sc->rx.lock, device_get_nameunit(dev), 820 "cpsw RX lock", MTX_DEF); 821 822 /* Allocate IRQ resources */ 823 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 824 if (error) { 825 device_printf(dev, "could not allocate IRQ resources\n"); 826 cpsw_detach(dev); 827 return (ENXIO); 828 } 829 830 sc->mem_rid = 0; 831 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 832 &sc->mem_rid, RF_ACTIVE); 833 if (sc->mem_res == NULL) { 834 device_printf(sc->dev, "failed to allocate memory resource\n"); 835 cpsw_detach(dev); 836 return (ENXIO); 837 } 838 839 reg = cpsw_read_4(sc, CPSW_SS_IDVER); 840 device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7), 841 reg & 0xFF, (reg >> 11) & 0x1F); 842 843 cpsw_add_sysctls(sc); 844 845 /* Allocate a busdma tag and DMA safe memory for mbufs. */ 846 error = bus_dma_tag_create( 847 bus_get_dma_tag(sc->dev), /* parent */ 848 1, 0, /* alignment, boundary */ 849 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 850 BUS_SPACE_MAXADDR, /* highaddr */ 851 NULL, NULL, /* filtfunc, filtfuncarg */ 852 MCLBYTES, CPSW_TXFRAGS, /* maxsize, nsegments */ 853 MCLBYTES, 0, /* maxsegsz, flags */ 854 NULL, NULL, /* lockfunc, lockfuncarg */ 855 &sc->mbuf_dtag); /* dmatag */ 856 if (error) { 857 device_printf(dev, "bus_dma_tag_create failed\n"); 858 cpsw_detach(dev); 859 return (error); 860 } 861 862 /* Allocate a NULL buffer for padding. */ 863 sc->nullpad = malloc(ETHER_MIN_LEN, M_DEVBUF, M_WAITOK | M_ZERO); 864 865 cpsw_init_slots(sc); 866 867 /* Allocate slots to TX and RX queues. */ 868 STAILQ_INIT(&sc->rx.avail); 869 STAILQ_INIT(&sc->rx.active); 870 STAILQ_INIT(&sc->tx.avail); 871 STAILQ_INIT(&sc->tx.active); 872 // For now: 128 slots to TX, rest to RX. 873 // XXX TODO: start with 32/64 and grow dynamically based on demand. 874 if (cpsw_add_slots(sc, &sc->tx, 128) || 875 cpsw_add_slots(sc, &sc->rx, -1)) { 876 device_printf(dev, "failed to allocate dmamaps\n"); 877 cpsw_detach(dev); 878 return (ENOMEM); 879 } 880 device_printf(dev, "Initial queue size TX=%d RX=%d\n", 881 sc->tx.queue_slots, sc->rx.queue_slots); 882 883 sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0); 884 sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0); 885 886 if (cpsw_intr_attach(sc) == -1) { 887 device_printf(dev, "failed to setup interrupts\n"); 888 cpsw_detach(dev); 889 return (ENXIO); 890 } 891 892#ifdef CPSW_ETHERSWITCH 893 for (i = 0; i < CPSW_VLANS; i++) 894 cpsw_vgroups[i].vid = -1; 895#endif 896 897 /* Reset the controller. */ 898 cpsw_reset(sc); 899 cpsw_init(sc); 900 901 for (i = 0; i < CPSW_PORTS; i++) { 902 if (!sc->dualemac && i != sc->active_slave) 903 continue; 904 sc->port[i].dev = device_add_child(dev, "cpsw", i); 905 if (sc->port[i].dev == NULL) { 906 cpsw_detach(dev); 907 return (ENXIO); 908 } 909 } 910 bus_generic_probe(dev); 911 bus_generic_attach(dev); 912 913 return (0); 914} 915 916static int 917cpsw_detach(device_t dev) 918{ 919 struct cpsw_softc *sc; 920 int error, i; 921 922 bus_generic_detach(dev); 923 sc = device_get_softc(dev); 924 925 for (i = 0; i < CPSW_PORTS; i++) { 926 if (sc->port[i].dev) 927 device_delete_child(dev, sc->port[i].dev); 928 } 929 930 if (device_is_attached(dev)) { 931 callout_stop(&sc->watchdog.callout); 932 callout_drain(&sc->watchdog.callout); 933 } 934 935 /* Stop and release all interrupts */ 936 cpsw_intr_detach(sc); 937 938 /* Free dmamaps and mbufs */ 939 for (i = 0; i < nitems(sc->_slots); ++i) 940 cpsw_free_slot(sc, &sc->_slots[i]); 941 942 /* Free null padding buffer. */ 943 if (sc->nullpad) 944 free(sc->nullpad, M_DEVBUF); 945 946 /* Free DMA tag */ 947 if (sc->mbuf_dtag) { 948 error = bus_dma_tag_destroy(sc->mbuf_dtag); 949 KASSERT(error == 0, ("Unable to destroy DMA tag")); 950 } 951 952 /* Free IO memory handler */ 953 if (sc->mem_res != NULL) 954 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 955 bus_release_resources(dev, irq_res_spec, sc->irq_res); 956 957 /* Destroy mutexes */ 958 mtx_destroy(&sc->rx.lock); 959 mtx_destroy(&sc->tx.lock); 960 961 /* Detach the switch device, if present. */ 962 error = bus_generic_detach(dev); 963 if (error != 0) 964 return (error); 965 966 return (device_delete_children(dev)); 967} 968 969static phandle_t 970cpsw_get_node(device_t bus, device_t dev) 971{ 972 973 /* Share controller node with port device. */ 974 return (ofw_bus_get_node(bus)); 975} 976 977static int 978cpswp_probe(device_t dev) 979{ 980 981 if (device_get_unit(dev) > 1) { 982 device_printf(dev, "Only two ports are supported.\n"); 983 return (ENXIO); 984 } 985 device_set_desc(dev, "Ethernet Switch Port"); 986 987 return (BUS_PROBE_DEFAULT); 988} 989 990static int 991cpswp_attach(device_t dev) 992{ 993 int error; 994 struct ifnet *ifp; 995 struct cpswp_softc *sc; 996 uint32_t reg; 997 uint8_t mac_addr[ETHER_ADDR_LEN]; 998 999 sc = device_get_softc(dev); 1000 sc->dev = dev; 1001 sc->pdev = device_get_parent(dev); 1002 sc->swsc = device_get_softc(sc->pdev); 1003 sc->unit = device_get_unit(dev); 1004 sc->phy = sc->swsc->port[sc->unit].phy; 1005 sc->vlan = sc->swsc->port[sc->unit].vlan; 1006 if (sc->swsc->dualemac && sc->vlan == -1) 1007 sc->vlan = sc->unit + 1; 1008 1009 if (sc->unit == 0) { 1010 sc->physel = MDIOUSERPHYSEL0; 1011 sc->phyaccess = MDIOUSERACCESS0; 1012 } else { 1013 sc->physel = MDIOUSERPHYSEL1; 1014 sc->phyaccess = MDIOUSERACCESS1; 1015 } 1016 1017 mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock", 1018 MTX_DEF); 1019 1020 /* Allocate network interface */ 1021 ifp = sc->ifp = if_alloc(IFT_ETHER); 1022 if (ifp == NULL) { 1023 cpswp_detach(dev); 1024 return (ENXIO); 1025 } 1026 1027 if_initname(ifp, device_get_name(sc->dev), sc->unit); 1028 ifp->if_softc = sc; 1029 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 1030 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM; //FIXME VLAN? 1031 ifp->if_capenable = ifp->if_capabilities; 1032 1033 ifp->if_init = cpswp_init; 1034 ifp->if_start = cpswp_start; 1035 ifp->if_ioctl = cpswp_ioctl; 1036 1037 ifp->if_snd.ifq_drv_maxlen = sc->swsc->tx.queue_slots; 1038 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1039 IFQ_SET_READY(&ifp->if_snd); 1040 1041 /* Get high part of MAC address from control module (mac_id[0|1]_hi) */ 1042 ti_scm_reg_read_4(SCM_MAC_ID0_HI + sc->unit * 8, ®); 1043 mac_addr[0] = reg & 0xFF; 1044 mac_addr[1] = (reg >> 8) & 0xFF; 1045 mac_addr[2] = (reg >> 16) & 0xFF; 1046 mac_addr[3] = (reg >> 24) & 0xFF; 1047 1048 /* Get low part of MAC address from control module (mac_id[0|1]_lo) */ 1049 ti_scm_reg_read_4(SCM_MAC_ID0_LO + sc->unit * 8, ®); 1050 mac_addr[4] = reg & 0xFF; 1051 mac_addr[5] = (reg >> 8) & 0xFF; 1052 1053 error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd, 1054 cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0); 1055 if (error) { 1056 device_printf(dev, "attaching PHYs failed\n"); 1057 cpswp_detach(dev); 1058 return (error); 1059 } 1060 sc->mii = device_get_softc(sc->miibus); 1061 1062 /* Select PHY and enable interrupts */ 1063 cpsw_write_4(sc->swsc, sc->physel, 1064 MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F)); 1065 1066 ether_ifattach(sc->ifp, mac_addr); 1067 callout_init(&sc->mii_callout, 0); 1068 1069 return (0); 1070} 1071 1072static int 1073cpswp_detach(device_t dev) 1074{ 1075 struct cpswp_softc *sc; 1076 1077 sc = device_get_softc(dev); 1078 CPSW_DEBUGF(sc->swsc, ("")); 1079 if (device_is_attached(dev)) { 1080 ether_ifdetach(sc->ifp); 1081 CPSW_PORT_LOCK(sc); 1082 cpswp_stop_locked(sc); 1083 CPSW_PORT_UNLOCK(sc); 1084 callout_drain(&sc->mii_callout); 1085 } 1086 1087 bus_generic_detach(dev); 1088 1089 if_free(sc->ifp); 1090 mtx_destroy(&sc->lock); 1091 1092 return (0); 1093} 1094 1095/* 1096 * 1097 * Init/Shutdown. 1098 * 1099 */ 1100 1101static int 1102cpsw_ports_down(struct cpsw_softc *sc) 1103{ 1104 struct cpswp_softc *psc; 1105 struct ifnet *ifp1, *ifp2; 1106 1107 if (!sc->dualemac) 1108 return (1); 1109 psc = device_get_softc(sc->port[0].dev); 1110 ifp1 = psc->ifp; 1111 psc = device_get_softc(sc->port[1].dev); 1112 ifp2 = psc->ifp; 1113 if ((ifp1->if_flags & IFF_UP) == 0 && (ifp2->if_flags & IFF_UP) == 0) 1114 return (1); 1115 1116 return (0); 1117} 1118 1119static void 1120cpswp_init(void *arg) 1121{ 1122 struct cpswp_softc *sc = arg; 1123 1124 CPSW_DEBUGF(sc->swsc, ("")); 1125 CPSW_PORT_LOCK(sc); 1126 cpswp_init_locked(arg); 1127 CPSW_PORT_UNLOCK(sc); 1128} 1129 1130static void 1131cpswp_init_locked(void *arg) 1132{ 1133#ifdef CPSW_ETHERSWITCH 1134 int i; 1135#endif 1136 struct cpswp_softc *sc = arg; 1137 struct ifnet *ifp; 1138 uint32_t reg; 1139 1140 CPSW_DEBUGF(sc->swsc, ("")); 1141 CPSW_PORT_LOCK_ASSERT(sc); 1142 ifp = sc->ifp; 1143 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1144 return; 1145 1146 getbinuptime(&sc->init_uptime); 1147 1148 if (!sc->swsc->rx.running && !sc->swsc->tx.running) { 1149 /* Reset the controller. */ 1150 cpsw_reset(sc->swsc); 1151 cpsw_init(sc->swsc); 1152 } 1153 1154 /* Set Slave Mapping. */ 1155 cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210); 1156 cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1), 1157 0x33221100); 1158 cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2); 1159 /* Enable MAC RX/TX modules. */ 1160 /* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */ 1161 /* Huh? Docs call bit 0 "Loopback" some places, "FullDuplex" others. */ 1162 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1163 reg |= CPSW_SL_MACTL_GMII_ENABLE; 1164 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1165 1166 /* Initialize ALE: set port to forwarding, initialize addrs */ 1167 cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1), 1168 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 1169 cpswp_ale_update_addresses(sc, 1); 1170 1171 if (sc->swsc->dualemac) { 1172 /* Set Port VID. */ 1173 cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1), 1174 sc->vlan & 0xfff); 1175 cpsw_ale_update_vlan_table(sc->swsc, sc->vlan, 1176 (1 << (sc->unit + 1)) | (1 << 0), /* Member list */ 1177 (1 << (sc->unit + 1)) | (1 << 0), /* Untagged egress */ 1178 (1 << (sc->unit + 1)) | (1 << 0), 0); /* mcast reg flood */ 1179#ifdef CPSW_ETHERSWITCH 1180 for (i = 0; i < CPSW_VLANS; i++) { 1181 if (cpsw_vgroups[i].vid != -1) 1182 continue; 1183 cpsw_vgroups[i].vid = sc->vlan; 1184 break; 1185 } 1186#endif 1187 } 1188 1189 mii_mediachg(sc->mii); 1190 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 1191 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1192 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1193} 1194 1195static int 1196cpsw_shutdown(device_t dev) 1197{ 1198 struct cpsw_softc *sc; 1199 struct cpswp_softc *psc; 1200 int i; 1201 1202 sc = device_get_softc(dev); 1203 CPSW_DEBUGF(sc, ("")); 1204 for (i = 0; i < CPSW_PORTS; i++) { 1205 if (!sc->dualemac && i != sc->active_slave) 1206 continue; 1207 psc = device_get_softc(sc->port[i].dev); 1208 CPSW_PORT_LOCK(psc); 1209 cpswp_stop_locked(psc); 1210 CPSW_PORT_UNLOCK(psc); 1211 } 1212 1213 return (0); 1214} 1215 1216static void 1217cpsw_rx_teardown(struct cpsw_softc *sc) 1218{ 1219 int i = 0; 1220 1221 CPSW_RX_LOCK(sc); 1222 CPSW_DEBUGF(sc, ("starting RX teardown")); 1223 sc->rx.teardown = 1; 1224 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1225 CPSW_RX_UNLOCK(sc); 1226 while (sc->rx.running) { 1227 if (++i > 10) { 1228 device_printf(sc->dev, 1229 "Unable to cleanly shutdown receiver\n"); 1230 return; 1231 } 1232 DELAY(200); 1233 } 1234 if (!sc->rx.running) 1235 CPSW_DEBUGF(sc, ("finished RX teardown (%d retries)", i)); 1236} 1237 1238static void 1239cpsw_tx_teardown(struct cpsw_softc *sc) 1240{ 1241 int i = 0; 1242 1243 CPSW_TX_LOCK(sc); 1244 CPSW_DEBUGF(sc, ("starting TX teardown")); 1245 /* Start the TX queue teardown if queue is not empty. */ 1246 if (STAILQ_FIRST(&sc->tx.active) != NULL) 1247 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1248 else 1249 sc->tx.teardown = 1; 1250 cpsw_tx_dequeue(sc); 1251 while (sc->tx.running && ++i < 10) { 1252 DELAY(200); 1253 cpsw_tx_dequeue(sc); 1254 } 1255 if (sc->tx.running) { 1256 device_printf(sc->dev, 1257 "Unable to cleanly shutdown transmitter\n"); 1258 } 1259 CPSW_DEBUGF(sc, 1260 ("finished TX teardown (%d retries, %d idle buffers)", i, 1261 sc->tx.active_queue_len)); 1262 CPSW_TX_UNLOCK(sc); 1263} 1264 1265static void 1266cpswp_stop_locked(struct cpswp_softc *sc) 1267{ 1268 struct ifnet *ifp; 1269 uint32_t reg; 1270 1271 ifp = sc->ifp; 1272 CPSW_DEBUGF(sc->swsc, ("")); 1273 CPSW_PORT_LOCK_ASSERT(sc); 1274 1275 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1276 return; 1277 1278 /* Disable interface */ 1279 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1280 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1281 1282 /* Stop ticker */ 1283 callout_stop(&sc->mii_callout); 1284 1285 /* Tear down the RX/TX queues. */ 1286 if (cpsw_ports_down(sc->swsc)) { 1287 cpsw_rx_teardown(sc->swsc); 1288 cpsw_tx_teardown(sc->swsc); 1289 } 1290 1291 /* Stop MAC RX/TX modules. */ 1292 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1293 reg &= ~CPSW_SL_MACTL_GMII_ENABLE; 1294 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1295 1296 if (cpsw_ports_down(sc->swsc)) { 1297 /* Capture stats before we reset controller. */ 1298 cpsw_stats_collect(sc->swsc); 1299 1300 cpsw_reset(sc->swsc); 1301 cpsw_init(sc->swsc); 1302 } 1303} 1304 1305/* 1306 * Suspend/Resume. 1307 */ 1308 1309static int 1310cpsw_suspend(device_t dev) 1311{ 1312 struct cpsw_softc *sc; 1313 struct cpswp_softc *psc; 1314 int i; 1315 1316 sc = device_get_softc(dev); 1317 CPSW_DEBUGF(sc, ("")); 1318 for (i = 0; i < CPSW_PORTS; i++) { 1319 if (!sc->dualemac && i != sc->active_slave) 1320 continue; 1321 psc = device_get_softc(sc->port[i].dev); 1322 CPSW_PORT_LOCK(psc); 1323 cpswp_stop_locked(psc); 1324 CPSW_PORT_UNLOCK(psc); 1325 } 1326 1327 return (0); 1328} 1329 1330static int 1331cpsw_resume(device_t dev) 1332{ 1333 struct cpsw_softc *sc; 1334 1335 sc = device_get_softc(dev); 1336 CPSW_DEBUGF(sc, ("UNIMPLEMENTED")); 1337 1338 return (0); 1339} 1340 1341/* 1342 * 1343 * IOCTL 1344 * 1345 */ 1346 1347static void 1348cpsw_set_promisc(struct cpswp_softc *sc, int set) 1349{ 1350 uint32_t reg; 1351 1352 /* 1353 * Enabling promiscuous mode requires ALE_BYPASS to be enabled. 1354 * That disables the ALE forwarding logic and causes every 1355 * packet to be sent only to the host port. In bypass mode, 1356 * the ALE processes host port transmit packets the same as in 1357 * normal mode. 1358 */ 1359 reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL); 1360 reg &= ~CPSW_ALE_CTL_BYPASS; 1361 if (set) 1362 reg |= CPSW_ALE_CTL_BYPASS; 1363 cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg); 1364} 1365 1366static void 1367cpsw_set_allmulti(struct cpswp_softc *sc, int set) 1368{ 1369 if (set) { 1370 printf("All-multicast mode unimplemented\n"); 1371 } 1372} 1373 1374static int 1375cpswp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1376{ 1377 struct cpswp_softc *sc; 1378 struct ifreq *ifr; 1379 int error; 1380 uint32_t changed; 1381 1382 error = 0; 1383 sc = ifp->if_softc; 1384 ifr = (struct ifreq *)data; 1385 1386 switch (command) { 1387 case SIOCSIFCAP: 1388 changed = ifp->if_capenable ^ ifr->ifr_reqcap; 1389 if (changed & IFCAP_HWCSUM) { 1390 if ((ifr->ifr_reqcap & changed) & IFCAP_HWCSUM) 1391 ifp->if_capenable |= IFCAP_HWCSUM; 1392 else 1393 ifp->if_capenable &= ~IFCAP_HWCSUM; 1394 } 1395 error = 0; 1396 break; 1397 case SIOCSIFFLAGS: 1398 CPSW_PORT_LOCK(sc); 1399 if (ifp->if_flags & IFF_UP) { 1400 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1401 changed = ifp->if_flags ^ sc->if_flags; 1402 CPSW_DEBUGF(sc->swsc, 1403 ("SIOCSIFFLAGS: UP & RUNNING (changed=0x%x)", 1404 changed)); 1405 if (changed & IFF_PROMISC) 1406 cpsw_set_promisc(sc, 1407 ifp->if_flags & IFF_PROMISC); 1408 if (changed & IFF_ALLMULTI) 1409 cpsw_set_allmulti(sc, 1410 ifp->if_flags & IFF_ALLMULTI); 1411 } else { 1412 CPSW_DEBUGF(sc->swsc, 1413 ("SIOCSIFFLAGS: starting up")); 1414 cpswp_init_locked(sc); 1415 } 1416 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1417 CPSW_DEBUGF(sc->swsc, ("SIOCSIFFLAGS: shutting down")); 1418 cpswp_stop_locked(sc); 1419 } 1420 1421 sc->if_flags = ifp->if_flags; 1422 CPSW_PORT_UNLOCK(sc); 1423 break; 1424 case SIOCADDMULTI: 1425 cpswp_ale_update_addresses(sc, 0); 1426 break; 1427 case SIOCDELMULTI: 1428 /* Ugh. DELMULTI doesn't provide the specific address 1429 being removed, so the best we can do is remove 1430 everything and rebuild it all. */ 1431 cpswp_ale_update_addresses(sc, 1); 1432 break; 1433 case SIOCGIFMEDIA: 1434 case SIOCSIFMEDIA: 1435 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command); 1436 break; 1437 default: 1438 error = ether_ioctl(ifp, command, data); 1439 } 1440 return (error); 1441} 1442 1443/* 1444 * 1445 * MIIBUS 1446 * 1447 */ 1448static int 1449cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg) 1450{ 1451 uint32_t r, retries = CPSW_MIIBUS_RETRIES; 1452 1453 while (--retries) { 1454 r = cpsw_read_4(sc, reg); 1455 if ((r & MDIO_PHYACCESS_GO) == 0) 1456 return (1); 1457 DELAY(CPSW_MIIBUS_DELAY); 1458 } 1459 1460 return (0); 1461} 1462 1463static int 1464cpswp_miibus_readreg(device_t dev, int phy, int reg) 1465{ 1466 struct cpswp_softc *sc; 1467 uint32_t cmd, r; 1468 1469 sc = device_get_softc(dev); 1470 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1471 device_printf(dev, "MDIO not ready to read\n"); 1472 return (0); 1473 } 1474 1475 /* Set GO, reg, phy */ 1476 cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16; 1477 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1478 1479 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1480 device_printf(dev, "MDIO timed out during read\n"); 1481 return (0); 1482 } 1483 1484 r = cpsw_read_4(sc->swsc, sc->phyaccess); 1485 if ((r & MDIO_PHYACCESS_ACK) == 0) { 1486 device_printf(dev, "Failed to read from PHY.\n"); 1487 r = 0; 1488 } 1489 return (r & 0xFFFF); 1490} 1491 1492static int 1493cpswp_miibus_writereg(device_t dev, int phy, int reg, int value) 1494{ 1495 struct cpswp_softc *sc; 1496 uint32_t cmd; 1497 1498 sc = device_get_softc(dev); 1499 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1500 device_printf(dev, "MDIO not ready to write\n"); 1501 return (0); 1502 } 1503 1504 /* Set GO, WRITE, reg, phy, and value */ 1505 cmd = MDIO_PHYACCESS_GO | MDIO_PHYACCESS_WRITE | 1506 (reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF); 1507 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1508 1509 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1510 device_printf(dev, "MDIO timed out during write\n"); 1511 return (0); 1512 } 1513 1514 return (0); 1515} 1516 1517static void 1518cpswp_miibus_statchg(device_t dev) 1519{ 1520 struct cpswp_softc *sc; 1521 uint32_t mac_control, reg; 1522 1523 sc = device_get_softc(dev); 1524 CPSW_DEBUGF(sc->swsc, ("")); 1525 1526 reg = CPSW_SL_MACCONTROL(sc->unit); 1527 mac_control = cpsw_read_4(sc->swsc, reg); 1528 mac_control &= ~(CPSW_SL_MACTL_GIG | CPSW_SL_MACTL_IFCTL_A | 1529 CPSW_SL_MACTL_IFCTL_B | CPSW_SL_MACTL_FULLDUPLEX); 1530 1531 switch(IFM_SUBTYPE(sc->mii->mii_media_active)) { 1532 case IFM_1000_SX: 1533 case IFM_1000_LX: 1534 case IFM_1000_CX: 1535 case IFM_1000_T: 1536 mac_control |= CPSW_SL_MACTL_GIG; 1537 break; 1538 1539 case IFM_100_TX: 1540 mac_control |= CPSW_SL_MACTL_IFCTL_A; 1541 break; 1542 } 1543 if (sc->mii->mii_media_active & IFM_FDX) 1544 mac_control |= CPSW_SL_MACTL_FULLDUPLEX; 1545 1546 cpsw_write_4(sc->swsc, reg, mac_control); 1547} 1548 1549/* 1550 * 1551 * Transmit/Receive Packets. 1552 * 1553 */ 1554static void 1555cpsw_intr_rx(void *arg) 1556{ 1557 struct cpsw_softc *sc; 1558 struct ifnet *ifp; 1559 struct mbuf *received, *next; 1560 1561 sc = (struct cpsw_softc *)arg; 1562 CPSW_RX_LOCK(sc); 1563 if (sc->rx.teardown) { 1564 sc->rx.running = 0; 1565 sc->rx.teardown = 0; 1566 cpsw_write_cp(sc, &sc->rx, 0xfffffffc); 1567 } 1568 received = cpsw_rx_dequeue(sc); 1569 cpsw_rx_enqueue(sc); 1570 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1); 1571 CPSW_RX_UNLOCK(sc); 1572 1573 while (received != NULL) { 1574 next = received->m_nextpkt; 1575 received->m_nextpkt = NULL; 1576 ifp = received->m_pkthdr.rcvif; 1577 (*ifp->if_input)(ifp, received); 1578 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1579 received = next; 1580 } 1581} 1582 1583static struct mbuf * 1584cpsw_rx_dequeue(struct cpsw_softc *sc) 1585{ 1586 int nsegs, port, removed; 1587 struct cpsw_cpdma_bd bd; 1588 struct cpsw_slot *last, *slot; 1589 struct cpswp_softc *psc; 1590 struct mbuf *m, *m0, *mb_head, *mb_tail; 1591 uint16_t m0_flags; 1592 1593 nsegs = 0; 1594 m0 = NULL; 1595 last = NULL; 1596 mb_head = NULL; 1597 mb_tail = NULL; 1598 removed = 0; 1599 1600 /* Pull completed packets off hardware RX queue. */ 1601 while ((slot = STAILQ_FIRST(&sc->rx.active)) != NULL) { 1602 cpsw_cpdma_read_bd(sc, slot, &bd); 1603 1604 /* 1605 * Stop on packets still in use by hardware, but do not stop 1606 * on packets with the teardown complete flag, they will be 1607 * discarded later. 1608 */ 1609 if ((bd.flags & (CPDMA_BD_OWNER | CPDMA_BD_TDOWNCMPLT)) == 1610 CPDMA_BD_OWNER) 1611 break; 1612 1613 last = slot; 1614 ++removed; 1615 STAILQ_REMOVE_HEAD(&sc->rx.active, next); 1616 STAILQ_INSERT_TAIL(&sc->rx.avail, slot, next); 1617 1618 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1619 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1620 1621 m = slot->mbuf; 1622 slot->mbuf = NULL; 1623 1624 if (bd.flags & CPDMA_BD_TDOWNCMPLT) { 1625 CPSW_DEBUGF(sc, ("RX teardown is complete")); 1626 m_freem(m); 1627 sc->rx.running = 0; 1628 sc->rx.teardown = 0; 1629 break; 1630 } 1631 1632 port = (bd.flags & CPDMA_BD_PORT_MASK) - 1; 1633 KASSERT(port >= 0 && port <= 1, 1634 ("patcket received with invalid port: %d", port)); 1635 psc = device_get_softc(sc->port[port].dev); 1636 1637 /* Set up mbuf */ 1638 m->m_data += bd.bufoff; 1639 m->m_len = bd.buflen; 1640 if (bd.flags & CPDMA_BD_SOP) { 1641 m->m_pkthdr.len = bd.pktlen; 1642 m->m_pkthdr.rcvif = psc->ifp; 1643 m->m_flags |= M_PKTHDR; 1644 m0_flags = bd.flags; 1645 m0 = m; 1646 } 1647 nsegs++; 1648 m->m_next = NULL; 1649 m->m_nextpkt = NULL; 1650 if (bd.flags & CPDMA_BD_EOP && m0 != NULL) { 1651 if (m0_flags & CPDMA_BD_PASS_CRC) 1652 m_adj(m0, -ETHER_CRC_LEN); 1653 m0_flags = 0; 1654 m0 = NULL; 1655 if (nsegs > sc->rx.longest_chain) 1656 sc->rx.longest_chain = nsegs; 1657 nsegs = 0; 1658 } 1659 1660 if ((psc->ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1661 /* check for valid CRC by looking into pkt_err[5:4] */ 1662 if ((bd.flags & 1663 (CPDMA_BD_SOP | CPDMA_BD_PKT_ERR_MASK)) == 1664 CPDMA_BD_SOP) { 1665 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1666 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1667 m->m_pkthdr.csum_data = 0xffff; 1668 } 1669 } 1670 1671 if (STAILQ_FIRST(&sc->rx.active) != NULL && 1672 (bd.flags & (CPDMA_BD_EOP | CPDMA_BD_EOQ)) == 1673 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 1674 cpsw_write_hdp_slot(sc, &sc->rx, 1675 STAILQ_FIRST(&sc->rx.active)); 1676 sc->rx.queue_restart++; 1677 } 1678 1679 /* Add mbuf to packet list to be returned. */ 1680 if (mb_tail != NULL && (bd.flags & CPDMA_BD_SOP)) { 1681 mb_tail->m_nextpkt = m; 1682 } else if (mb_tail != NULL) { 1683 mb_tail->m_next = m; 1684 } else if (mb_tail == NULL && (bd.flags & CPDMA_BD_SOP) == 0) { 1685 if (bootverbose) 1686 printf( 1687 "%s: %s: discanding fragment packet w/o header\n", 1688 __func__, psc->ifp->if_xname); 1689 m_freem(m); 1690 continue; 1691 } else { 1692 mb_head = m; 1693 } 1694 mb_tail = m; 1695 } 1696 1697 if (removed != 0) { 1698 cpsw_write_cp_slot(sc, &sc->rx, last); 1699 sc->rx.queue_removes += removed; 1700 sc->rx.avail_queue_len += removed; 1701 sc->rx.active_queue_len -= removed; 1702 if (sc->rx.avail_queue_len > sc->rx.max_avail_queue_len) 1703 sc->rx.max_avail_queue_len = sc->rx.avail_queue_len; 1704 CPSW_DEBUGF(sc, ("Removed %d received packet(s) from RX queue", removed)); 1705 } 1706 1707 return (mb_head); 1708} 1709 1710static void 1711cpsw_rx_enqueue(struct cpsw_softc *sc) 1712{ 1713 bus_dma_segment_t seg[1]; 1714 struct cpsw_cpdma_bd bd; 1715 struct cpsw_slot *first_new_slot, *last_old_slot, *next, *slot; 1716 int error, nsegs, added = 0; 1717 1718 /* Register new mbufs with hardware. */ 1719 first_new_slot = NULL; 1720 last_old_slot = STAILQ_LAST(&sc->rx.active, cpsw_slot, next); 1721 while ((slot = STAILQ_FIRST(&sc->rx.avail)) != NULL) { 1722 if (first_new_slot == NULL) 1723 first_new_slot = slot; 1724 if (slot->mbuf == NULL) { 1725 slot->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1726 if (slot->mbuf == NULL) { 1727 device_printf(sc->dev, 1728 "Unable to fill RX queue\n"); 1729 break; 1730 } 1731 slot->mbuf->m_len = 1732 slot->mbuf->m_pkthdr.len = 1733 slot->mbuf->m_ext.ext_size; 1734 } 1735 1736 error = bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, slot->dmamap, 1737 slot->mbuf, seg, &nsegs, BUS_DMA_NOWAIT); 1738 1739 KASSERT(nsegs == 1, ("More than one segment (nsegs=%d)", nsegs)); 1740 KASSERT(error == 0, ("DMA error (error=%d)", error)); 1741 if (error != 0 || nsegs != 1) { 1742 device_printf(sc->dev, 1743 "%s: Can't prep RX buf for DMA (nsegs=%d, error=%d)\n", 1744 __func__, nsegs, error); 1745 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1746 m_freem(slot->mbuf); 1747 slot->mbuf = NULL; 1748 break; 1749 } 1750 1751 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_PREREAD); 1752 1753 /* Create and submit new rx descriptor. */ 1754 if ((next = STAILQ_NEXT(slot, next)) != NULL) 1755 bd.next = cpsw_cpdma_bd_paddr(sc, next); 1756 else 1757 bd.next = 0; 1758 bd.bufptr = seg->ds_addr; 1759 bd.bufoff = 0; 1760 bd.buflen = MCLBYTES - 1; 1761 bd.pktlen = bd.buflen; 1762 bd.flags = CPDMA_BD_OWNER; 1763 cpsw_cpdma_write_bd(sc, slot, &bd); 1764 ++added; 1765 1766 STAILQ_REMOVE_HEAD(&sc->rx.avail, next); 1767 STAILQ_INSERT_TAIL(&sc->rx.active, slot, next); 1768 } 1769 1770 if (added == 0 || first_new_slot == NULL) 1771 return; 1772 1773 CPSW_DEBUGF(sc, ("Adding %d buffers to RX queue", added)); 1774 1775 /* Link new entries to hardware RX queue. */ 1776 if (last_old_slot == NULL) { 1777 /* Start a fresh queue. */ 1778 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1779 } else { 1780 /* Add buffers to end of current queue. */ 1781 cpsw_cpdma_write_bd_next(sc, last_old_slot, first_new_slot); 1782 } 1783 sc->rx.queue_adds += added; 1784 sc->rx.avail_queue_len -= added; 1785 sc->rx.active_queue_len += added; 1786 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added); 1787 if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) 1788 sc->rx.max_active_queue_len = sc->rx.active_queue_len; 1789} 1790 1791static void 1792cpswp_start(struct ifnet *ifp) 1793{ 1794 struct cpswp_softc *sc; 1795 1796 sc = ifp->if_softc; 1797 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1798 sc->swsc->tx.running == 0) { 1799 return; 1800 } 1801 CPSW_TX_LOCK(sc->swsc); 1802 cpswp_tx_enqueue(sc); 1803 cpsw_tx_dequeue(sc->swsc); 1804 CPSW_TX_UNLOCK(sc->swsc); 1805} 1806 1807static void 1808cpsw_intr_tx(void *arg) 1809{ 1810 struct cpsw_softc *sc; 1811 1812 sc = (struct cpsw_softc *)arg; 1813 CPSW_TX_LOCK(sc); 1814 if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc) 1815 cpsw_write_cp(sc, &sc->tx, 0xfffffffc); 1816 cpsw_tx_dequeue(sc); 1817 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2); 1818 CPSW_TX_UNLOCK(sc); 1819} 1820 1821static void 1822cpswp_tx_enqueue(struct cpswp_softc *sc) 1823{ 1824 bus_dma_segment_t segs[CPSW_TXFRAGS]; 1825 struct cpsw_cpdma_bd bd; 1826 struct cpsw_slot *first_new_slot, *last, *last_old_slot, *next, *slot; 1827 struct mbuf *m0; 1828 int error, nsegs, seg, added = 0, padlen; 1829 1830 /* Pull pending packets from IF queue and prep them for DMA. */ 1831 last = NULL; 1832 first_new_slot = NULL; 1833 last_old_slot = STAILQ_LAST(&sc->swsc->tx.active, cpsw_slot, next); 1834 while ((slot = STAILQ_FIRST(&sc->swsc->tx.avail)) != NULL) { 1835 IF_DEQUEUE(&sc->ifp->if_snd, m0); 1836 if (m0 == NULL) 1837 break; 1838 1839 slot->mbuf = m0; 1840 padlen = ETHER_MIN_LEN - ETHER_CRC_LEN - m0->m_pkthdr.len; 1841 if (padlen < 0) 1842 padlen = 0; 1843 else if (padlen > 0) 1844 m_append(slot->mbuf, padlen, sc->swsc->nullpad); 1845 1846 /* Create mapping in DMA memory */ 1847 error = bus_dmamap_load_mbuf_sg(sc->swsc->mbuf_dtag, 1848 slot->dmamap, slot->mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 1849 /* If the packet is too fragmented, try to simplify. */ 1850 if (error == EFBIG || 1851 (error == 0 && nsegs > sc->swsc->tx.avail_queue_len)) { 1852 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1853 m0 = m_defrag(slot->mbuf, M_NOWAIT); 1854 if (m0 == NULL) { 1855 device_printf(sc->dev, 1856 "Can't defragment packet; dropping\n"); 1857 m_freem(slot->mbuf); 1858 } else { 1859 CPSW_DEBUGF(sc->swsc, 1860 ("Requeueing defragmented packet")); 1861 IF_PREPEND(&sc->ifp->if_snd, m0); 1862 } 1863 slot->mbuf = NULL; 1864 continue; 1865 } 1866 if (error != 0) { 1867 device_printf(sc->dev, 1868 "%s: Can't setup DMA (error=%d), dropping packet\n", 1869 __func__, error); 1870 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1871 m_freem(slot->mbuf); 1872 slot->mbuf = NULL; 1873 break; 1874 } 1875 1876 bus_dmamap_sync(sc->swsc->mbuf_dtag, slot->dmamap, 1877 BUS_DMASYNC_PREWRITE); 1878 1879 CPSW_DEBUGF(sc->swsc, 1880 ("Queueing TX packet: %d segments + %d pad bytes", 1881 nsegs, padlen)); 1882 1883 if (first_new_slot == NULL) 1884 first_new_slot = slot; 1885 1886 /* Link from the previous descriptor. */ 1887 if (last != NULL) 1888 cpsw_cpdma_write_bd_next(sc->swsc, last, slot); 1889 1890 slot->ifp = sc->ifp; 1891 1892 /* If there is only one segment, the for() loop 1893 * gets skipped and the single buffer gets set up 1894 * as both SOP and EOP. */ 1895 if (nsegs > 1) { 1896 next = STAILQ_NEXT(slot, next); 1897 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1898 } else 1899 bd.next = 0; 1900 /* Start by setting up the first buffer. */ 1901 bd.bufptr = segs[0].ds_addr; 1902 bd.bufoff = 0; 1903 bd.buflen = segs[0].ds_len; 1904 bd.pktlen = m_length(slot->mbuf, NULL); 1905 bd.flags = CPDMA_BD_SOP | CPDMA_BD_OWNER; 1906 if (sc->swsc->dualemac) { 1907 bd.flags |= CPDMA_BD_TO_PORT; 1908 bd.flags |= ((sc->unit + 1) & CPDMA_BD_PORT_MASK); 1909 } 1910 for (seg = 1; seg < nsegs; ++seg) { 1911 /* Save the previous buffer (which isn't EOP) */ 1912 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1913 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1914 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1915 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1916 1917 /* Setup next buffer (which isn't SOP) */ 1918 if (nsegs > seg + 1) { 1919 next = STAILQ_NEXT(slot, next); 1920 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1921 } else 1922 bd.next = 0; 1923 bd.bufptr = segs[seg].ds_addr; 1924 bd.bufoff = 0; 1925 bd.buflen = segs[seg].ds_len; 1926 bd.pktlen = 0; 1927 bd.flags = CPDMA_BD_OWNER; 1928 } 1929 1930 /* Save the final buffer. */ 1931 bd.flags |= CPDMA_BD_EOP; 1932 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1933 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1934 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1935 1936 last = slot; 1937 added += nsegs; 1938 if (nsegs > sc->swsc->tx.longest_chain) 1939 sc->swsc->tx.longest_chain = nsegs; 1940 1941 BPF_MTAP(sc->ifp, m0); 1942 } 1943 1944 if (first_new_slot == NULL) 1945 return; 1946 1947 /* Attach the list of new buffers to the hardware TX queue. */ 1948 if (last_old_slot != NULL && 1949 (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) & 1950 CPDMA_BD_EOQ) == 0) { 1951 /* Add buffers to end of current queue. */ 1952 cpsw_cpdma_write_bd_next(sc->swsc, last_old_slot, 1953 first_new_slot); 1954 } else { 1955 /* Start a fresh queue. */ 1956 cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot); 1957 } 1958 sc->swsc->tx.queue_adds += added; 1959 sc->swsc->tx.avail_queue_len -= added; 1960 sc->swsc->tx.active_queue_len += added; 1961 if (sc->swsc->tx.active_queue_len > sc->swsc->tx.max_active_queue_len) { 1962 sc->swsc->tx.max_active_queue_len = sc->swsc->tx.active_queue_len; 1963 } 1964 CPSW_DEBUGF(sc->swsc, ("Queued %d TX packet(s)", added)); 1965} 1966 1967static int 1968cpsw_tx_dequeue(struct cpsw_softc *sc) 1969{ 1970 struct cpsw_slot *slot, *last_removed_slot = NULL; 1971 struct cpsw_cpdma_bd bd; 1972 uint32_t flags, removed = 0; 1973 1974 /* Pull completed buffers off the hardware TX queue. */ 1975 slot = STAILQ_FIRST(&sc->tx.active); 1976 while (slot != NULL) { 1977 flags = cpsw_cpdma_read_bd_flags(sc, slot); 1978 1979 /* TearDown complete is only marked on the SOP for the packet. */ 1980 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) == 1981 (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) { 1982 sc->tx.teardown = 1; 1983 } 1984 1985 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_OWNER)) == 1986 (CPDMA_BD_SOP | CPDMA_BD_OWNER) && sc->tx.teardown == 0) 1987 break; /* Hardware is still using this packet. */ 1988 1989 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1990 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1991 m_freem(slot->mbuf); 1992 slot->mbuf = NULL; 1993 1994 if (slot->ifp) { 1995 if (sc->tx.teardown == 0) 1996 if_inc_counter(slot->ifp, IFCOUNTER_OPACKETS, 1); 1997 else 1998 if_inc_counter(slot->ifp, IFCOUNTER_OQDROPS, 1); 1999 } 2000 2001 /* Dequeue any additional buffers used by this packet. */ 2002 while (slot != NULL && slot->mbuf == NULL) { 2003 STAILQ_REMOVE_HEAD(&sc->tx.active, next); 2004 STAILQ_INSERT_TAIL(&sc->tx.avail, slot, next); 2005 ++removed; 2006 last_removed_slot = slot; 2007 slot = STAILQ_FIRST(&sc->tx.active); 2008 } 2009 2010 cpsw_write_cp_slot(sc, &sc->tx, last_removed_slot); 2011 2012 /* Restart the TX queue if necessary. */ 2013 cpsw_cpdma_read_bd(sc, last_removed_slot, &bd); 2014 if (slot != NULL && bd.next != 0 && (bd.flags & 2015 (CPDMA_BD_EOP | CPDMA_BD_OWNER | CPDMA_BD_EOQ)) == 2016 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 2017 cpsw_write_hdp_slot(sc, &sc->tx, slot); 2018 sc->tx.queue_restart++; 2019 break; 2020 } 2021 } 2022 2023 if (removed != 0) { 2024 sc->tx.queue_removes += removed; 2025 sc->tx.active_queue_len -= removed; 2026 sc->tx.avail_queue_len += removed; 2027 if (sc->tx.avail_queue_len > sc->tx.max_avail_queue_len) 2028 sc->tx.max_avail_queue_len = sc->tx.avail_queue_len; 2029 CPSW_DEBUGF(sc, ("TX removed %d completed packet(s)", removed)); 2030 } 2031 2032 if (sc->tx.teardown && STAILQ_EMPTY(&sc->tx.active)) { 2033 CPSW_DEBUGF(sc, ("TX teardown is complete")); 2034 sc->tx.teardown = 0; 2035 sc->tx.running = 0; 2036 } 2037 2038 return (removed); 2039} 2040 2041/* 2042 * 2043 * Miscellaneous interrupts. 2044 * 2045 */ 2046 2047static void 2048cpsw_intr_rx_thresh(void *arg) 2049{ 2050 struct cpsw_softc *sc; 2051 struct ifnet *ifp; 2052 struct mbuf *received, *next; 2053 2054 sc = (struct cpsw_softc *)arg; 2055 CPSW_RX_LOCK(sc); 2056 received = cpsw_rx_dequeue(sc); 2057 cpsw_rx_enqueue(sc); 2058 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0); 2059 CPSW_RX_UNLOCK(sc); 2060 2061 while (received != NULL) { 2062 next = received->m_nextpkt; 2063 received->m_nextpkt = NULL; 2064 ifp = received->m_pkthdr.rcvif; 2065 (*ifp->if_input)(ifp, received); 2066 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2067 received = next; 2068 } 2069} 2070 2071static void 2072cpsw_intr_misc_host_error(struct cpsw_softc *sc) 2073{ 2074 uint32_t intstat; 2075 uint32_t dmastat; 2076 int txerr, rxerr, txchan, rxchan; 2077 2078 printf("\n\n"); 2079 device_printf(sc->dev, 2080 "HOST ERROR: PROGRAMMING ERROR DETECTED BY HARDWARE\n"); 2081 printf("\n\n"); 2082 intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 2083 device_printf(sc->dev, "CPSW_CPDMA_DMA_INTSTAT_MASKED=0x%x\n", intstat); 2084 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 2085 device_printf(sc->dev, "CPSW_CPDMA_DMASTATUS=0x%x\n", dmastat); 2086 2087 txerr = (dmastat >> 20) & 15; 2088 txchan = (dmastat >> 16) & 7; 2089 rxerr = (dmastat >> 12) & 15; 2090 rxchan = (dmastat >> 8) & 7; 2091 2092 switch (txerr) { 2093 case 0: break; 2094 case 1: printf("SOP error on TX channel %d\n", txchan); 2095 break; 2096 case 2: printf("Ownership bit not set on SOP buffer on TX channel %d\n", txchan); 2097 break; 2098 case 3: printf("Zero Next Buffer but not EOP on TX channel %d\n", txchan); 2099 break; 2100 case 4: printf("Zero Buffer Pointer on TX channel %d\n", txchan); 2101 break; 2102 case 5: printf("Zero Buffer Length on TX channel %d\n", txchan); 2103 break; 2104 case 6: printf("Packet length error on TX channel %d\n", txchan); 2105 break; 2106 default: printf("Unknown error on TX channel %d\n", txchan); 2107 break; 2108 } 2109 2110 if (txerr != 0) { 2111 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 2112 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan))); 2113 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 2114 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan))); 2115 cpsw_dump_queue(sc, &sc->tx.active); 2116 } 2117 2118 switch (rxerr) { 2119 case 0: break; 2120 case 2: printf("Ownership bit not set on RX channel %d\n", rxchan); 2121 break; 2122 case 4: printf("Zero Buffer Pointer on RX channel %d\n", rxchan); 2123 break; 2124 case 5: printf("Zero Buffer Length on RX channel %d\n", rxchan); 2125 break; 2126 case 6: printf("Buffer offset too big on RX channel %d\n", rxchan); 2127 break; 2128 default: printf("Unknown RX error on RX channel %d\n", rxchan); 2129 break; 2130 } 2131 2132 if (rxerr != 0) { 2133 printf("CPSW_CPDMA_RX%d_HDP=0x%x\n", 2134 rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan))); 2135 printf("CPSW_CPDMA_RX%d_CP=0x%x\n", 2136 rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan))); 2137 cpsw_dump_queue(sc, &sc->rx.active); 2138 } 2139 2140 printf("\nALE Table\n"); 2141 cpsw_ale_dump_table(sc); 2142 2143 // XXX do something useful here?? 2144 panic("CPSW HOST ERROR INTERRUPT"); 2145 2146 // Suppress this interrupt in the future. 2147 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat); 2148 printf("XXX HOST ERROR INTERRUPT SUPPRESSED\n"); 2149 // The watchdog will probably reset the controller 2150 // in a little while. It will probably fail again. 2151} 2152 2153static void 2154cpsw_intr_misc(void *arg) 2155{ 2156 struct cpsw_softc *sc = arg; 2157 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 2158 2159 if (stat & CPSW_WR_C_MISC_EVNT_PEND) 2160 CPSW_DEBUGF(sc, ("Time sync event interrupt unimplemented")); 2161 if (stat & CPSW_WR_C_MISC_STAT_PEND) 2162 cpsw_stats_collect(sc); 2163 if (stat & CPSW_WR_C_MISC_HOST_PEND) 2164 cpsw_intr_misc_host_error(sc); 2165 if (stat & CPSW_WR_C_MISC_MDIOLINK) { 2166 cpsw_write_4(sc, MDIOLINKINTMASKED, 2167 cpsw_read_4(sc, MDIOLINKINTMASKED)); 2168 } 2169 if (stat & CPSW_WR_C_MISC_MDIOUSER) { 2170 CPSW_DEBUGF(sc, 2171 ("MDIO operation completed interrupt unimplemented")); 2172 } 2173 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3); 2174} 2175 2176/* 2177 * 2178 * Periodic Checks and Watchdog. 2179 * 2180 */ 2181 2182static void 2183cpswp_tick(void *msc) 2184{ 2185 struct cpswp_softc *sc = msc; 2186 2187 /* Check for media type change */ 2188 mii_tick(sc->mii); 2189 if (sc->media_status != sc->mii->mii_media.ifm_media) { 2190 printf("%s: media type changed (ifm_media=%x)\n", __func__, 2191 sc->mii->mii_media.ifm_media); 2192 cpswp_ifmedia_upd(sc->ifp); 2193 } 2194 2195 /* Schedule another timeout one second from now */ 2196 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 2197} 2198 2199static void 2200cpswp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2201{ 2202 struct cpswp_softc *sc; 2203 struct mii_data *mii; 2204 2205 sc = ifp->if_softc; 2206 CPSW_DEBUGF(sc->swsc, ("")); 2207 CPSW_PORT_LOCK(sc); 2208 2209 mii = sc->mii; 2210 mii_pollstat(mii); 2211 2212 ifmr->ifm_active = mii->mii_media_active; 2213 ifmr->ifm_status = mii->mii_media_status; 2214 CPSW_PORT_UNLOCK(sc); 2215} 2216 2217static int 2218cpswp_ifmedia_upd(struct ifnet *ifp) 2219{ 2220 struct cpswp_softc *sc; 2221 2222 sc = ifp->if_softc; 2223 CPSW_DEBUGF(sc->swsc, ("")); 2224 CPSW_PORT_LOCK(sc); 2225 mii_mediachg(sc->mii); 2226 sc->media_status = sc->mii->mii_media.ifm_media; 2227 CPSW_PORT_UNLOCK(sc); 2228 2229 return (0); 2230} 2231 2232static void 2233cpsw_tx_watchdog_full_reset(struct cpsw_softc *sc) 2234{ 2235 struct cpswp_softc *psc; 2236 int i; 2237 2238 cpsw_debugf_head("CPSW watchdog"); 2239 device_printf(sc->dev, "watchdog timeout\n"); 2240 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 0, 2241 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0))); 2242 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 0, 2243 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0))); 2244 cpsw_dump_queue(sc, &sc->tx.active); 2245 for (i = 0; i < CPSW_PORTS; i++) { 2246 if (!sc->dualemac && i != sc->active_slave) 2247 continue; 2248 psc = device_get_softc(sc->port[i].dev); 2249 CPSW_PORT_LOCK(psc); 2250 cpswp_stop_locked(psc); 2251 CPSW_PORT_UNLOCK(psc); 2252 } 2253} 2254 2255static void 2256cpsw_tx_watchdog(void *msc) 2257{ 2258 struct cpsw_softc *sc; 2259 2260 sc = msc; 2261 CPSW_TX_LOCK(sc); 2262 if (sc->tx.active_queue_len == 0 || !sc->tx.running) { 2263 sc->watchdog.timer = 0; /* Nothing to do. */ 2264 } else if (sc->tx.queue_removes > sc->tx.queue_removes_at_last_tick) { 2265 sc->watchdog.timer = 0; /* Stuff done while we weren't looking. */ 2266 } else if (cpsw_tx_dequeue(sc) > 0) { 2267 sc->watchdog.timer = 0; /* We just did something. */ 2268 } else { 2269 /* There was something to do but it didn't get done. */ 2270 ++sc->watchdog.timer; 2271 if (sc->watchdog.timer > 5) { 2272 sc->watchdog.timer = 0; 2273 ++sc->watchdog.resets; 2274 cpsw_tx_watchdog_full_reset(sc); 2275 } 2276 } 2277 sc->tx.queue_removes_at_last_tick = sc->tx.queue_removes; 2278 CPSW_TX_UNLOCK(sc); 2279 2280 /* Schedule another timeout one second from now */ 2281 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 2282} 2283 2284/* 2285 * 2286 * ALE support routines. 2287 * 2288 */ 2289 2290static void 2291cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2292{ 2293 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 2294 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 2295 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 2296 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 2297} 2298 2299static void 2300cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2301{ 2302 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 2303 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 2304 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 2305 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 2306} 2307 2308static void 2309cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 2310{ 2311 int i; 2312 uint32_t ale_entry[3]; 2313 2314 /* First four entries are link address and broadcast. */ 2315 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2316 cpsw_ale_read_entry(sc, i, ale_entry); 2317 if ((ALE_TYPE(ale_entry) == ALE_TYPE_ADDR || 2318 ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) && 2319 ALE_MCAST(ale_entry) == 1) { /* MCast link addr */ 2320 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2321 cpsw_ale_write_entry(sc, i, ale_entry); 2322 } 2323 } 2324} 2325 2326static int 2327cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, int vlan, 2328 uint8_t *mac) 2329{ 2330 int free_index = -1, matching_index = -1, i; 2331 uint32_t ale_entry[3], ale_type; 2332 2333 /* Find a matching entry or a free entry. */ 2334 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2335 cpsw_ale_read_entry(sc, i, ale_entry); 2336 2337 /* Entry Type[61:60] is 0 for free entry */ 2338 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2339 free_index = i; 2340 2341 if ((((ale_entry[1] >> 8) & 0xFF) == mac[0]) && 2342 (((ale_entry[1] >> 0) & 0xFF) == mac[1]) && 2343 (((ale_entry[0] >>24) & 0xFF) == mac[2]) && 2344 (((ale_entry[0] >>16) & 0xFF) == mac[3]) && 2345 (((ale_entry[0] >> 8) & 0xFF) == mac[4]) && 2346 (((ale_entry[0] >> 0) & 0xFF) == mac[5])) { 2347 matching_index = i; 2348 break; 2349 } 2350 } 2351 2352 if (matching_index < 0) { 2353 if (free_index < 0) 2354 return (ENOMEM); 2355 i = free_index; 2356 } 2357 2358 if (vlan != -1) 2359 ale_type = ALE_TYPE_VLAN_ADDR << 28 | vlan << 16; 2360 else 2361 ale_type = ALE_TYPE_ADDR << 28; 2362 2363 /* Set MAC address */ 2364 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2365 ale_entry[1] = mac[0] << 8 | mac[1]; 2366 2367 /* Entry type[61:60] and Mcast fwd state[63:62] is fw(3). */ 2368 ale_entry[1] |= ALE_MCAST_FWD | ale_type; 2369 2370 /* Set portmask [68:66] */ 2371 ale_entry[2] = (portmap & 7) << 2; 2372 2373 cpsw_ale_write_entry(sc, i, ale_entry); 2374 2375 return 0; 2376} 2377 2378static void 2379cpsw_ale_dump_table(struct cpsw_softc *sc) { 2380 int i; 2381 uint32_t ale_entry[3]; 2382 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2383 cpsw_ale_read_entry(sc, i, ale_entry); 2384 switch (ALE_TYPE(ale_entry)) { 2385 case ALE_TYPE_VLAN: 2386 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2387 ale_entry[1], ale_entry[0]); 2388 printf("type: %u ", ALE_TYPE(ale_entry)); 2389 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2390 printf("untag: %u ", ALE_VLAN_UNTAG(ale_entry)); 2391 printf("reg flood: %u ", ALE_VLAN_REGFLOOD(ale_entry)); 2392 printf("unreg flood: %u ", ALE_VLAN_UNREGFLOOD(ale_entry)); 2393 printf("members: %u ", ALE_VLAN_MEMBERS(ale_entry)); 2394 printf("\n"); 2395 break; 2396 case ALE_TYPE_ADDR: 2397 case ALE_TYPE_VLAN_ADDR: 2398 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2399 ale_entry[1], ale_entry[0]); 2400 printf("type: %u ", ALE_TYPE(ale_entry)); 2401 printf("mac: %02x:%02x:%02x:%02x:%02x:%02x ", 2402 (ale_entry[1] >> 8) & 0xFF, 2403 (ale_entry[1] >> 0) & 0xFF, 2404 (ale_entry[0] >>24) & 0xFF, 2405 (ale_entry[0] >>16) & 0xFF, 2406 (ale_entry[0] >> 8) & 0xFF, 2407 (ale_entry[0] >> 0) & 0xFF); 2408 printf(ALE_MCAST(ale_entry) ? "mcast " : "ucast "); 2409 if (ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) 2410 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2411 printf("port: %u ", ALE_PORTS(ale_entry)); 2412 printf("\n"); 2413 break; 2414 } 2415 } 2416 printf("\n"); 2417} 2418 2419static int 2420cpswp_ale_update_addresses(struct cpswp_softc *sc, int purge) 2421{ 2422 uint8_t *mac; 2423 uint32_t ale_entry[3], ale_type, portmask; 2424 struct ifmultiaddr *ifma; 2425 2426 if (sc->swsc->dualemac) { 2427 ale_type = ALE_TYPE_VLAN_ADDR << 28 | sc->vlan << 16; 2428 portmask = 1 << (sc->unit + 1) | 1 << 0; 2429 } else { 2430 ale_type = ALE_TYPE_ADDR << 28; 2431 portmask = 7; 2432 } 2433 2434 /* 2435 * Route incoming packets for our MAC address to Port 0 (host). 2436 * For simplicity, keep this entry at table index 0 for port 1 and 2437 * at index 2 for port 2 in the ALE. 2438 */ 2439 if_addr_rlock(sc->ifp); 2440 mac = LLADDR((struct sockaddr_dl *)sc->ifp->if_addr->ifa_addr); 2441 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2442 ale_entry[1] = ale_type | mac[0] << 8 | mac[1]; /* addr entry + mac */ 2443 ale_entry[2] = 0; /* port = 0 */ 2444 cpsw_ale_write_entry(sc->swsc, 0 + 2 * sc->unit, ale_entry); 2445 2446 /* Set outgoing MAC Address for slave port. */ 2447 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1), 2448 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 2449 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1), 2450 mac[5] << 8 | mac[4]); 2451 if_addr_runlock(sc->ifp); 2452 2453 /* Keep the broadcast address at table entry 1 (or 3). */ 2454 ale_entry[0] = 0xffffffff; /* Lower 32 bits of MAC */ 2455 /* ALE_MCAST_FWD, Addr type, upper 16 bits of Mac */ 2456 ale_entry[1] = ALE_MCAST_FWD | ale_type | 0xffff; 2457 ale_entry[2] = portmask << 2; 2458 cpsw_ale_write_entry(sc->swsc, 1 + 2 * sc->unit, ale_entry); 2459 2460 /* SIOCDELMULTI doesn't specify the particular address 2461 being removed, so we have to remove all and rebuild. */ 2462 if (purge) 2463 cpsw_ale_remove_all_mc_entries(sc->swsc); 2464 2465 /* Set other multicast addrs desired. */ 2466 if_maddr_rlock(sc->ifp); 2467 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 2468 if (ifma->ifma_addr->sa_family != AF_LINK) 2469 continue; 2470 cpsw_ale_mc_entry_set(sc->swsc, portmask, sc->vlan, 2471 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 2472 } 2473 if_maddr_runlock(sc->ifp); 2474 2475 return (0); 2476} 2477 2478static int 2479cpsw_ale_update_vlan_table(struct cpsw_softc *sc, int vlan, int ports, 2480 int untag, int mcregflood, int mcunregflood) 2481{ 2482 int free_index, i, matching_index; 2483 uint32_t ale_entry[3]; 2484 2485 free_index = matching_index = -1; 2486 /* Find a matching entry or a free entry. */ 2487 for (i = 5; i < CPSW_MAX_ALE_ENTRIES; i++) { 2488 cpsw_ale_read_entry(sc, i, ale_entry); 2489 2490 /* Entry Type[61:60] is 0 for free entry */ 2491 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2492 free_index = i; 2493 2494 if (ALE_VLAN(ale_entry) == vlan) { 2495 matching_index = i; 2496 break; 2497 } 2498 } 2499 2500 if (matching_index < 0) { 2501 if (free_index < 0) 2502 return (-1); 2503 i = free_index; 2504 } 2505 2506 ale_entry[0] = (untag & 7) << 24 | (mcregflood & 7) << 16 | 2507 (mcunregflood & 7) << 8 | (ports & 7); 2508 ale_entry[1] = ALE_TYPE_VLAN << 28 | vlan << 16; 2509 ale_entry[2] = 0; 2510 cpsw_ale_write_entry(sc, i, ale_entry); 2511 2512 return (0); 2513} 2514 2515/* 2516 * 2517 * Statistics and Sysctls. 2518 * 2519 */ 2520 2521#if 0 2522static void 2523cpsw_stats_dump(struct cpsw_softc *sc) 2524{ 2525 int i; 2526 uint32_t r; 2527 2528 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2529 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2530 cpsw_stat_sysctls[i].reg); 2531 CPSW_DEBUGF(sc, ("%s: %ju + %u = %ju", cpsw_stat_sysctls[i].oid, 2532 (intmax_t)sc->shadow_stats[i], r, 2533 (intmax_t)sc->shadow_stats[i] + r)); 2534 } 2535} 2536#endif 2537 2538static void 2539cpsw_stats_collect(struct cpsw_softc *sc) 2540{ 2541 int i; 2542 uint32_t r; 2543 2544 CPSW_DEBUGF(sc, ("Controller shadow statistics updated.")); 2545 2546 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2547 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2548 cpsw_stat_sysctls[i].reg); 2549 sc->shadow_stats[i] += r; 2550 cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg, 2551 r); 2552 } 2553} 2554 2555static int 2556cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS) 2557{ 2558 struct cpsw_softc *sc; 2559 struct cpsw_stat *stat; 2560 uint64_t result; 2561 2562 sc = (struct cpsw_softc *)arg1; 2563 stat = &cpsw_stat_sysctls[oidp->oid_number]; 2564 result = sc->shadow_stats[oidp->oid_number]; 2565 result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg); 2566 return (sysctl_handle_64(oidp, &result, 0, req)); 2567} 2568 2569static int 2570cpsw_stat_attached(SYSCTL_HANDLER_ARGS) 2571{ 2572 struct cpsw_softc *sc; 2573 struct bintime t; 2574 unsigned result; 2575 2576 sc = (struct cpsw_softc *)arg1; 2577 getbinuptime(&t); 2578 bintime_sub(&t, &sc->attach_uptime); 2579 result = t.sec; 2580 return (sysctl_handle_int(oidp, &result, 0, req)); 2581} 2582 2583static int 2584cpsw_intr_coalesce(SYSCTL_HANDLER_ARGS) 2585{ 2586 int error; 2587 struct cpsw_softc *sc; 2588 uint32_t ctrl, intr_per_ms; 2589 2590 sc = (struct cpsw_softc *)arg1; 2591 error = sysctl_handle_int(oidp, &sc->coal_us, 0, req); 2592 if (error != 0 || req->newptr == NULL) 2593 return (error); 2594 2595 ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 2596 ctrl &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 2597 if (sc->coal_us == 0) { 2598 /* Disable the interrupt pace hardware. */ 2599 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2600 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0); 2601 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0); 2602 return (0); 2603 } 2604 2605 if (sc->coal_us > CPSW_WR_C_IMAX_US_MAX) 2606 sc->coal_us = CPSW_WR_C_IMAX_US_MAX; 2607 if (sc->coal_us < CPSW_WR_C_IMAX_US_MIN) 2608 sc->coal_us = CPSW_WR_C_IMAX_US_MIN; 2609 intr_per_ms = 1000 / sc->coal_us; 2610 /* Just to make sure... */ 2611 if (intr_per_ms > CPSW_WR_C_IMAX_MAX) 2612 intr_per_ms = CPSW_WR_C_IMAX_MAX; 2613 if (intr_per_ms < CPSW_WR_C_IMAX_MIN) 2614 intr_per_ms = CPSW_WR_C_IMAX_MIN; 2615 2616 /* Set the prescale to produce 4us pulses from the 125 Mhz clock. */ 2617 ctrl |= (125 * 4) & CPSW_WR_INT_PRESCALE_MASK; 2618 2619 /* Enable the interrupt pace hardware. */ 2620 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms); 2621 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms); 2622 ctrl |= CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE; 2623 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2624 2625 return (0); 2626} 2627 2628static int 2629cpsw_stat_uptime(SYSCTL_HANDLER_ARGS) 2630{ 2631 struct cpsw_softc *swsc; 2632 struct cpswp_softc *sc; 2633 struct bintime t; 2634 unsigned result; 2635 2636 swsc = arg1; 2637 sc = device_get_softc(swsc->port[arg2].dev); 2638 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) { 2639 getbinuptime(&t); 2640 bintime_sub(&t, &sc->init_uptime); 2641 result = t.sec; 2642 } else 2643 result = 0; 2644 return (sysctl_handle_int(oidp, &result, 0, req)); 2645} 2646 2647static void 2648cpsw_add_queue_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2649 struct cpsw_queue *queue) 2650{ 2651 struct sysctl_oid_list *parent; 2652 2653 parent = SYSCTL_CHILDREN(node); 2654 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "totalBuffers", 2655 CTLFLAG_RD, &queue->queue_slots, 0, 2656 "Total buffers currently assigned to this queue"); 2657 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "activeBuffers", 2658 CTLFLAG_RD, &queue->active_queue_len, 0, 2659 "Buffers currently registered with hardware controller"); 2660 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxActiveBuffers", 2661 CTLFLAG_RD, &queue->max_active_queue_len, 0, 2662 "Max value of activeBuffers since last driver reset"); 2663 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "availBuffers", 2664 CTLFLAG_RD, &queue->avail_queue_len, 0, 2665 "Buffers allocated to this queue but not currently " 2666 "registered with hardware controller"); 2667 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxAvailBuffers", 2668 CTLFLAG_RD, &queue->max_avail_queue_len, 0, 2669 "Max value of availBuffers since last driver reset"); 2670 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalEnqueued", 2671 CTLFLAG_RD, &queue->queue_adds, 0, 2672 "Total buffers added to queue"); 2673 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalDequeued", 2674 CTLFLAG_RD, &queue->queue_removes, 0, 2675 "Total buffers removed from queue"); 2676 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "queueRestart", 2677 CTLFLAG_RD, &queue->queue_restart, 0, 2678 "Total times the queue has been restarted"); 2679 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "longestChain", 2680 CTLFLAG_RD, &queue->longest_chain, 0, 2681 "Max buffers used for a single packet"); 2682} 2683 2684static void 2685cpsw_add_watchdog_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2686 struct cpsw_softc *sc) 2687{ 2688 struct sysctl_oid_list *parent; 2689 2690 parent = SYSCTL_CHILDREN(node); 2691 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "resets", 2692 CTLFLAG_RD, &sc->watchdog.resets, 0, 2693 "Total number of watchdog resets"); 2694} 2695 2696static void 2697cpsw_add_sysctls(struct cpsw_softc *sc) 2698{ 2699 struct sysctl_ctx_list *ctx; 2700 struct sysctl_oid *stats_node, *queue_node, *node; 2701 struct sysctl_oid_list *parent, *stats_parent, *queue_parent; 2702 struct sysctl_oid_list *ports_parent, *port_parent; 2703 char port[16]; 2704 int i; 2705 2706 ctx = device_get_sysctl_ctx(sc->dev); 2707 parent = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2708 2709 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "debug", 2710 CTLFLAG_RW, &sc->debug, 0, "Enable switch debug messages"); 2711 2712 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "attachedSecs", 2713 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, cpsw_stat_attached, "IU", 2714 "Time since driver attach"); 2715 2716 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "intr_coalesce_us", 2717 CTLTYPE_UINT | CTLFLAG_RW, sc, 0, cpsw_intr_coalesce, "IU", 2718 "minimum time between interrupts"); 2719 2720 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "ports", 2721 CTLFLAG_RD, NULL, "CPSW Ports Statistics"); 2722 ports_parent = SYSCTL_CHILDREN(node); 2723 for (i = 0; i < CPSW_PORTS; i++) { 2724 if (!sc->dualemac && i != sc->active_slave) 2725 continue; 2726 port[0] = '0' + i; 2727 port[1] = '\0'; 2728 node = SYSCTL_ADD_NODE(ctx, ports_parent, OID_AUTO, 2729 port, CTLFLAG_RD, NULL, "CPSW Port Statistics"); 2730 port_parent = SYSCTL_CHILDREN(node); 2731 SYSCTL_ADD_PROC(ctx, port_parent, OID_AUTO, "uptime", 2732 CTLTYPE_UINT | CTLFLAG_RD, sc, i, 2733 cpsw_stat_uptime, "IU", "Seconds since driver init"); 2734 } 2735 2736 stats_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 2737 CTLFLAG_RD, NULL, "CPSW Statistics"); 2738 stats_parent = SYSCTL_CHILDREN(stats_node); 2739 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2740 SYSCTL_ADD_PROC(ctx, stats_parent, i, 2741 cpsw_stat_sysctls[i].oid, 2742 CTLTYPE_U64 | CTLFLAG_RD, sc, 0, 2743 cpsw_stats_sysctl, "IU", 2744 cpsw_stat_sysctls[i].oid); 2745 } 2746 2747 queue_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "queue", 2748 CTLFLAG_RD, NULL, "CPSW Queue Statistics"); 2749 queue_parent = SYSCTL_CHILDREN(queue_node); 2750 2751 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "tx", 2752 CTLFLAG_RD, NULL, "TX Queue Statistics"); 2753 cpsw_add_queue_sysctls(ctx, node, &sc->tx); 2754 2755 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "rx", 2756 CTLFLAG_RD, NULL, "RX Queue Statistics"); 2757 cpsw_add_queue_sysctls(ctx, node, &sc->rx); 2758 2759 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "watchdog", 2760 CTLFLAG_RD, NULL, "Watchdog Statistics"); 2761 cpsw_add_watchdog_sysctls(ctx, node, sc); 2762} 2763 2764#ifdef CPSW_ETHERSWITCH 2765static etherswitch_info_t etherswitch_info = { 2766 .es_nports = CPSW_PORTS + 1, 2767 .es_nvlangroups = CPSW_VLANS, 2768 .es_name = "TI Common Platform Ethernet Switch (CPSW)", 2769 .es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q, 2770}; 2771 2772static etherswitch_info_t * 2773cpsw_getinfo(device_t dev) 2774{ 2775 return (ðerswitch_info); 2776} 2777 2778static int 2779cpsw_getport(device_t dev, etherswitch_port_t *p) 2780{ 2781 int err; 2782 struct cpsw_softc *sc; 2783 struct cpswp_softc *psc; 2784 struct ifmediareq *ifmr; 2785 uint32_t reg; 2786 2787 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2788 return (ENXIO); 2789 2790 err = 0; 2791 sc = device_get_softc(dev); 2792 if (p->es_port == CPSW_CPU_PORT) { 2793 p->es_flags |= ETHERSWITCH_PORT_CPU; 2794 ifmr = &p->es_ifmr; 2795 ifmr->ifm_current = ifmr->ifm_active = 2796 IFM_ETHER | IFM_1000_T | IFM_FDX; 2797 ifmr->ifm_mask = 0; 2798 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 2799 ifmr->ifm_count = 0; 2800 } else { 2801 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2802 err = ifmedia_ioctl(psc->ifp, &p->es_ifr, 2803 &psc->mii->mii_media, SIOCGIFMEDIA); 2804 } 2805 reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port)); 2806 p->es_pvid = reg & ETHERSWITCH_VID_MASK; 2807 2808 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2809 if (reg & ALE_PORTCTL_DROP_UNTAGGED) 2810 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 2811 if (reg & ALE_PORTCTL_INGRESS) 2812 p->es_flags |= ETHERSWITCH_PORT_INGRESS; 2813 2814 return (err); 2815} 2816 2817static int 2818cpsw_setport(device_t dev, etherswitch_port_t *p) 2819{ 2820 struct cpsw_softc *sc; 2821 struct cpswp_softc *psc; 2822 struct ifmedia *ifm; 2823 uint32_t reg; 2824 2825 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2826 return (ENXIO); 2827 2828 sc = device_get_softc(dev); 2829 if (p->es_pvid != 0) { 2830 cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port), 2831 p->es_pvid & ETHERSWITCH_VID_MASK); 2832 } 2833 2834 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2835 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 2836 reg |= ALE_PORTCTL_DROP_UNTAGGED; 2837 else 2838 reg &= ~ALE_PORTCTL_DROP_UNTAGGED; 2839 if (p->es_flags & ETHERSWITCH_PORT_INGRESS) 2840 reg |= ALE_PORTCTL_INGRESS; 2841 else 2842 reg &= ~ALE_PORTCTL_INGRESS; 2843 cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg); 2844 2845 /* CPU port does not allow media settings. */ 2846 if (p->es_port == CPSW_CPU_PORT) 2847 return (0); 2848 2849 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2850 ifm = &psc->mii->mii_media; 2851 2852 return (ifmedia_ioctl(psc->ifp, &p->es_ifr, ifm, SIOCSIFMEDIA)); 2853} 2854 2855static int 2856cpsw_getconf(device_t dev, etherswitch_conf_t *conf) 2857{ 2858 2859 /* Return the VLAN mode. */ 2860 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 2861 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 2862 2863 return (0); 2864} 2865 2866static int 2867cpsw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2868{ 2869 int i, vid; 2870 uint32_t ale_entry[3]; 2871 struct cpsw_softc *sc; 2872 2873 sc = device_get_softc(dev); 2874 2875 if (vg->es_vlangroup >= CPSW_VLANS) 2876 return (EINVAL); 2877 2878 vg->es_vid = 0; 2879 vid = cpsw_vgroups[vg->es_vlangroup].vid; 2880 if (vid == -1) 2881 return (0); 2882 2883 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2884 cpsw_ale_read_entry(sc, i, ale_entry); 2885 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2886 continue; 2887 if (vid != ALE_VLAN(ale_entry)) 2888 continue; 2889 2890 vg->es_fid = 0; 2891 vg->es_vid = ALE_VLAN(ale_entry) | ETHERSWITCH_VID_VALID; 2892 vg->es_member_ports = ALE_VLAN_MEMBERS(ale_entry); 2893 vg->es_untagged_ports = ALE_VLAN_UNTAG(ale_entry); 2894 } 2895 2896 return (0); 2897} 2898 2899static void 2900cpsw_remove_vlan(struct cpsw_softc *sc, int vlan) 2901{ 2902 int i; 2903 uint32_t ale_entry[3]; 2904 2905 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2906 cpsw_ale_read_entry(sc, i, ale_entry); 2907 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2908 continue; 2909 if (vlan != ALE_VLAN(ale_entry)) 2910 continue; 2911 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2912 cpsw_ale_write_entry(sc, i, ale_entry); 2913 break; 2914 } 2915} 2916 2917static int 2918cpsw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2919{ 2920 int i; 2921 struct cpsw_softc *sc; 2922 2923 sc = device_get_softc(dev); 2924 2925 for (i = 0; i < CPSW_VLANS; i++) { 2926 /* Is this Vlan ID in use by another vlangroup ? */ 2927 if (vg->es_vlangroup != i && cpsw_vgroups[i].vid == vg->es_vid) 2928 return (EINVAL); 2929 } 2930 2931 if (vg->es_vid == 0) { 2932 if (cpsw_vgroups[vg->es_vlangroup].vid == -1) 2933 return (0); 2934 cpsw_remove_vlan(sc, cpsw_vgroups[vg->es_vlangroup].vid); 2935 cpsw_vgroups[vg->es_vlangroup].vid = -1; 2936 vg->es_untagged_ports = 0; 2937 vg->es_member_ports = 0; 2938 vg->es_vid = 0; 2939 return (0); 2940 } 2941 2942 vg->es_vid &= ETHERSWITCH_VID_MASK; 2943 vg->es_member_ports &= CPSW_PORTS_MASK; 2944 vg->es_untagged_ports &= CPSW_PORTS_MASK; 2945 2946 if (cpsw_vgroups[vg->es_vlangroup].vid != -1 && 2947 cpsw_vgroups[vg->es_vlangroup].vid != vg->es_vid) 2948 return (EINVAL); 2949 2950 cpsw_vgroups[vg->es_vlangroup].vid = vg->es_vid; 2951 cpsw_ale_update_vlan_table(sc, vg->es_vid, vg->es_member_ports, 2952 vg->es_untagged_ports, vg->es_member_ports, 0); 2953 2954 return (0); 2955} 2956 2957static int 2958cpsw_readreg(device_t dev, int addr) 2959{ 2960 2961 /* Not supported. */ 2962 return (0); 2963} 2964 2965static int 2966cpsw_writereg(device_t dev, int addr, int value) 2967{ 2968 2969 /* Not supported. */ 2970 return (0); 2971} 2972 2973static int 2974cpsw_readphy(device_t dev, int phy, int reg) 2975{ 2976 2977 /* Not supported. */ 2978 return (0); 2979} 2980 2981static int 2982cpsw_writephy(device_t dev, int phy, int reg, int data) 2983{ 2984 2985 /* Not supported. */ 2986 return (0); 2987} 2988#endif 2989