if_cpsw.c revision 310882
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* 29 * TI Common Platform Ethernet Switch (CPSW) Driver 30 * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs. 31 * 32 * This controller is documented in the AM335x Technical Reference 33 * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM 34 * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM. 35 * 36 * It is basically a single Ethernet port (port 0) wired internally to 37 * a 3-port store-and-forward switch connected to two independent 38 * "sliver" controllers (port 1 and port 2). You can operate the 39 * controller in a variety of different ways by suitably configuring 40 * the slivers and the Address Lookup Engine (ALE) that routes packets 41 * between the ports. 42 * 43 * This code was developed and tested on a BeagleBone with 44 * an AM335x SoC. 45 */ 46 47#include <sys/cdefs.h> 48__FBSDID("$FreeBSD: stable/11/sys/arm/ti/cpsw/if_cpsw.c 310882 2016-12-31 01:54:48Z loos $"); 49 50#include "opt_cpsw.h" 51 52#include <sys/param.h> 53#include <sys/bus.h> 54#include <sys/kernel.h> 55#include <sys/lock.h> 56#include <sys/mbuf.h> 57#include <sys/module.h> 58#include <sys/mutex.h> 59#include <sys/rman.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/sysctl.h> 63 64#include <machine/bus.h> 65#include <machine/resource.h> 66#include <machine/stdarg.h> 67 68#include <net/ethernet.h> 69#include <net/bpf.h> 70#include <net/if.h> 71#include <net/if_dl.h> 72#include <net/if_media.h> 73#include <net/if_types.h> 74 75#include <arm/ti/ti_scm.h> 76#include <arm/ti/am335x/am335x_scm.h> 77 78#include <dev/mii/mii.h> 79#include <dev/mii/miivar.h> 80 81#include <dev/fdt/fdt_common.h> 82#include <dev/ofw/ofw_bus.h> 83#include <dev/ofw/ofw_bus_subr.h> 84 85#ifdef CPSW_ETHERSWITCH 86#include <dev/etherswitch/etherswitch.h> 87#include "etherswitch_if.h" 88#endif 89 90#include "if_cpswreg.h" 91#include "if_cpswvar.h" 92 93#include "miibus_if.h" 94 95/* Device probe/attach/detach. */ 96static int cpsw_probe(device_t); 97static int cpsw_attach(device_t); 98static int cpsw_detach(device_t); 99static int cpswp_probe(device_t); 100static int cpswp_attach(device_t); 101static int cpswp_detach(device_t); 102 103static phandle_t cpsw_get_node(device_t, device_t); 104 105/* Device Init/shutdown. */ 106static int cpsw_shutdown(device_t); 107static void cpswp_init(void *); 108static void cpswp_init_locked(void *); 109static void cpswp_stop_locked(struct cpswp_softc *); 110 111/* Device Suspend/Resume. */ 112static int cpsw_suspend(device_t); 113static int cpsw_resume(device_t); 114 115/* Ioctl. */ 116static int cpswp_ioctl(struct ifnet *, u_long command, caddr_t data); 117 118static int cpswp_miibus_readreg(device_t, int phy, int reg); 119static int cpswp_miibus_writereg(device_t, int phy, int reg, int value); 120static void cpswp_miibus_statchg(device_t); 121 122/* Send/Receive packets. */ 123static void cpsw_intr_rx(void *arg); 124static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *); 125static void cpsw_rx_enqueue(struct cpsw_softc *); 126static void cpswp_start(struct ifnet *); 127static void cpsw_intr_tx(void *); 128static void cpswp_tx_enqueue(struct cpswp_softc *); 129static int cpsw_tx_dequeue(struct cpsw_softc *); 130 131/* Misc interrupts and watchdog. */ 132static void cpsw_intr_rx_thresh(void *); 133static void cpsw_intr_misc(void *); 134static void cpswp_tick(void *); 135static void cpswp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 136static int cpswp_ifmedia_upd(struct ifnet *); 137static void cpsw_tx_watchdog(void *); 138 139/* ALE support */ 140static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *); 141static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *); 142static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *); 143static void cpsw_ale_dump_table(struct cpsw_softc *); 144static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int, int, 145 int); 146static int cpswp_ale_update_addresses(struct cpswp_softc *, int); 147 148/* Statistics and sysctls. */ 149static void cpsw_add_sysctls(struct cpsw_softc *); 150static void cpsw_stats_collect(struct cpsw_softc *); 151static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS); 152 153#ifdef CPSW_ETHERSWITCH 154static etherswitch_info_t *cpsw_getinfo(device_t); 155static int cpsw_getport(device_t, etherswitch_port_t *); 156static int cpsw_setport(device_t, etherswitch_port_t *); 157static int cpsw_getconf(device_t, etherswitch_conf_t *); 158static int cpsw_getvgroup(device_t, etherswitch_vlangroup_t *); 159static int cpsw_setvgroup(device_t, etherswitch_vlangroup_t *); 160static int cpsw_readreg(device_t, int); 161static int cpsw_writereg(device_t, int, int); 162static int cpsw_readphy(device_t, int, int); 163static int cpsw_writephy(device_t, int, int, int); 164#endif 165 166/* 167 * Arbitrary limit on number of segments in an mbuf to be transmitted. 168 * Packets with more segments than this will be defragmented before 169 * they are queued. 170 */ 171#define CPSW_TXFRAGS 16 172 173/* Shared resources. */ 174static device_method_t cpsw_methods[] = { 175 /* Device interface */ 176 DEVMETHOD(device_probe, cpsw_probe), 177 DEVMETHOD(device_attach, cpsw_attach), 178 DEVMETHOD(device_detach, cpsw_detach), 179 DEVMETHOD(device_shutdown, cpsw_shutdown), 180 DEVMETHOD(device_suspend, cpsw_suspend), 181 DEVMETHOD(device_resume, cpsw_resume), 182 /* Bus interface */ 183 DEVMETHOD(bus_add_child, device_add_child_ordered), 184 /* OFW methods */ 185 DEVMETHOD(ofw_bus_get_node, cpsw_get_node), 186#ifdef CPSW_ETHERSWITCH 187 /* etherswitch interface */ 188 DEVMETHOD(etherswitch_getinfo, cpsw_getinfo), 189 DEVMETHOD(etherswitch_readreg, cpsw_readreg), 190 DEVMETHOD(etherswitch_writereg, cpsw_writereg), 191 DEVMETHOD(etherswitch_readphyreg, cpsw_readphy), 192 DEVMETHOD(etherswitch_writephyreg, cpsw_writephy), 193 DEVMETHOD(etherswitch_getport, cpsw_getport), 194 DEVMETHOD(etherswitch_setport, cpsw_setport), 195 DEVMETHOD(etherswitch_getvgroup, cpsw_getvgroup), 196 DEVMETHOD(etherswitch_setvgroup, cpsw_setvgroup), 197 DEVMETHOD(etherswitch_getconf, cpsw_getconf), 198#endif 199 DEVMETHOD_END 200}; 201 202static driver_t cpsw_driver = { 203 "cpswss", 204 cpsw_methods, 205 sizeof(struct cpsw_softc), 206}; 207 208static devclass_t cpsw_devclass; 209 210DRIVER_MODULE(cpswss, simplebus, cpsw_driver, cpsw_devclass, 0, 0); 211 212/* Port/Slave resources. */ 213static device_method_t cpswp_methods[] = { 214 /* Device interface */ 215 DEVMETHOD(device_probe, cpswp_probe), 216 DEVMETHOD(device_attach, cpswp_attach), 217 DEVMETHOD(device_detach, cpswp_detach), 218 /* MII interface */ 219 DEVMETHOD(miibus_readreg, cpswp_miibus_readreg), 220 DEVMETHOD(miibus_writereg, cpswp_miibus_writereg), 221 DEVMETHOD(miibus_statchg, cpswp_miibus_statchg), 222 DEVMETHOD_END 223}; 224 225static driver_t cpswp_driver = { 226 "cpsw", 227 cpswp_methods, 228 sizeof(struct cpswp_softc), 229}; 230 231static devclass_t cpswp_devclass; 232 233#ifdef CPSW_ETHERSWITCH 234DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, etherswitch_devclass, 0, 0); 235MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1); 236#endif 237 238DRIVER_MODULE(cpsw, cpswss, cpswp_driver, cpswp_devclass, 0, 0); 239DRIVER_MODULE(miibus, cpsw, miibus_driver, miibus_devclass, 0, 0); 240MODULE_DEPEND(cpsw, ether, 1, 1, 1); 241MODULE_DEPEND(cpsw, miibus, 1, 1, 1); 242 243#ifdef CPSW_ETHERSWITCH 244static struct cpsw_vlangroups cpsw_vgroups[CPSW_VLANS]; 245#endif 246 247static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 }; 248 249static struct resource_spec irq_res_spec[] = { 250 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 251 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE }, 252 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE }, 253 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE }, 254 { -1, 0 } 255}; 256 257static struct { 258 void (*cb)(void *); 259} cpsw_intr_cb[] = { 260 { cpsw_intr_rx_thresh }, 261 { cpsw_intr_rx }, 262 { cpsw_intr_tx }, 263 { cpsw_intr_misc }, 264}; 265 266/* Number of entries here must match size of stats 267 * array in struct cpswp_softc. */ 268static struct cpsw_stat { 269 int reg; 270 char *oid; 271} cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = { 272 {0x00, "GoodRxFrames"}, 273 {0x04, "BroadcastRxFrames"}, 274 {0x08, "MulticastRxFrames"}, 275 {0x0C, "PauseRxFrames"}, 276 {0x10, "RxCrcErrors"}, 277 {0x14, "RxAlignErrors"}, 278 {0x18, "OversizeRxFrames"}, 279 {0x1c, "RxJabbers"}, 280 {0x20, "ShortRxFrames"}, 281 {0x24, "RxFragments"}, 282 {0x30, "RxOctets"}, 283 {0x34, "GoodTxFrames"}, 284 {0x38, "BroadcastTxFrames"}, 285 {0x3c, "MulticastTxFrames"}, 286 {0x40, "PauseTxFrames"}, 287 {0x44, "DeferredTxFrames"}, 288 {0x48, "CollisionsTxFrames"}, 289 {0x4c, "SingleCollisionTxFrames"}, 290 {0x50, "MultipleCollisionTxFrames"}, 291 {0x54, "ExcessiveCollisions"}, 292 {0x58, "LateCollisions"}, 293 {0x5c, "TxUnderrun"}, 294 {0x60, "CarrierSenseErrors"}, 295 {0x64, "TxOctets"}, 296 {0x68, "RxTx64OctetFrames"}, 297 {0x6c, "RxTx65to127OctetFrames"}, 298 {0x70, "RxTx128to255OctetFrames"}, 299 {0x74, "RxTx256to511OctetFrames"}, 300 {0x78, "RxTx512to1024OctetFrames"}, 301 {0x7c, "RxTx1024upOctetFrames"}, 302 {0x80, "NetOctets"}, 303 {0x84, "RxStartOfFrameOverruns"}, 304 {0x88, "RxMiddleOfFrameOverruns"}, 305 {0x8c, "RxDmaOverruns"} 306}; 307 308/* 309 * Basic debug support. 310 */ 311 312static void 313cpsw_debugf_head(const char *funcname) 314{ 315 int t = (int)(time_second % (24 * 60 * 60)); 316 317 printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname); 318} 319 320static void 321cpsw_debugf(const char *fmt, ...) 322{ 323 va_list ap; 324 325 va_start(ap, fmt); 326 vprintf(fmt, ap); 327 va_end(ap); 328 printf("\n"); 329 330} 331 332#define CPSW_DEBUGF(_sc, a) do { \ 333 if ((_sc)->debug) { \ 334 cpsw_debugf_head(__func__); \ 335 cpsw_debugf a; \ 336 } \ 337} while (0) 338 339/* 340 * Locking macros 341 */ 342#define CPSW_TX_LOCK(sc) do { \ 343 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \ 344 mtx_lock(&(sc)->tx.lock); \ 345} while (0) 346 347#define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock) 348#define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED) 349 350#define CPSW_RX_LOCK(sc) do { \ 351 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \ 352 mtx_lock(&(sc)->rx.lock); \ 353} while (0) 354 355#define CPSW_RX_UNLOCK(sc) mtx_unlock(&(sc)->rx.lock) 356#define CPSW_RX_LOCK_ASSERT(sc) mtx_assert(&(sc)->rx.lock, MA_OWNED) 357 358#define CPSW_PORT_LOCK(_sc) do { \ 359 mtx_assert(&(_sc)->lock, MA_NOTOWNED); \ 360 mtx_lock(&(_sc)->lock); \ 361} while (0) 362 363#define CPSW_PORT_UNLOCK(_sc) mtx_unlock(&(_sc)->lock) 364#define CPSW_PORT_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->lock, MA_OWNED) 365 366/* 367 * Read/Write macros 368 */ 369#define cpsw_read_4(_sc, _reg) bus_read_4((_sc)->mem_res, (_reg)) 370#define cpsw_write_4(_sc, _reg, _val) \ 371 bus_write_4((_sc)->mem_res, (_reg), (_val)) 372 373#define cpsw_cpdma_bd_offset(i) (CPSW_CPPI_RAM_OFFSET + ((i)*16)) 374 375#define cpsw_cpdma_bd_paddr(sc, slot) \ 376 BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset) 377#define cpsw_cpdma_read_bd(sc, slot, val) \ 378 bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 379#define cpsw_cpdma_write_bd(sc, slot, val) \ 380 bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4) 381#define cpsw_cpdma_write_bd_next(sc, slot, next_slot) \ 382 cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot)) 383#define cpsw_cpdma_write_bd_flags(sc, slot, val) \ 384 bus_write_2(sc->mem_res, slot->bd_offset + 14, val) 385#define cpsw_cpdma_read_bd_flags(sc, slot) \ 386 bus_read_2(sc->mem_res, slot->bd_offset + 14) 387#define cpsw_write_hdp_slot(sc, queue, slot) \ 388 cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot)) 389#define CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0)) 390#define cpsw_read_cp(sc, queue) \ 391 cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET) 392#define cpsw_write_cp(sc, queue, val) \ 393 cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val)) 394#define cpsw_write_cp_slot(sc, queue, slot) \ 395 cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot)) 396 397#if 0 398/* XXX temporary function versions for debugging. */ 399static void 400cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 401{ 402 uint32_t reg = queue->hdp_offset; 403 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 404 CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg))); 405 cpsw_write_4(sc, reg, v); 406} 407 408static void 409cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot) 410{ 411 uint32_t v = cpsw_cpdma_bd_paddr(sc, slot); 412 CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue))); 413 cpsw_write_cp(sc, queue, v); 414} 415#endif 416 417/* 418 * Expanded dump routines for verbose debugging. 419 */ 420static void 421cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 422{ 423 static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ", 424 "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun", 425 "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1", 426 "Port0"}; 427 struct cpsw_cpdma_bd bd; 428 const char *sep; 429 int i; 430 431 cpsw_cpdma_read_bd(sc, slot, &bd); 432 printf("BD Addr : 0x%08x Next : 0x%08x\n", 433 cpsw_cpdma_bd_paddr(sc, slot), bd.next); 434 printf(" BufPtr: 0x%08x BufLen: 0x%08x\n", bd.bufptr, bd.buflen); 435 printf(" BufOff: 0x%08x PktLen: 0x%08x\n", bd.bufoff, bd.pktlen); 436 printf(" Flags: "); 437 sep = ""; 438 for (i = 0; i < 16; ++i) { 439 if (bd.flags & (1 << (15 - i))) { 440 printf("%s%s", sep, flags[i]); 441 sep = ","; 442 } 443 } 444 printf("\n"); 445 if (slot->mbuf) { 446 printf(" Ether: %14D\n", 447 (char *)(slot->mbuf->m_data), " "); 448 printf(" Packet: %16D\n", 449 (char *)(slot->mbuf->m_data) + 14, " "); 450 } 451} 452 453#define CPSW_DUMP_SLOT(cs, slot) do { \ 454 IF_DEBUG(sc) { \ 455 cpsw_dump_slot(sc, slot); \ 456 } \ 457} while (0) 458 459static void 460cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q) 461{ 462 struct cpsw_slot *slot; 463 int i = 0; 464 int others = 0; 465 466 STAILQ_FOREACH(slot, q, next) { 467 if (i > CPSW_TXFRAGS) 468 ++others; 469 else 470 cpsw_dump_slot(sc, slot); 471 ++i; 472 } 473 if (others) 474 printf(" ... and %d more.\n", others); 475 printf("\n"); 476} 477 478#define CPSW_DUMP_QUEUE(sc, q) do { \ 479 IF_DEBUG(sc) { \ 480 cpsw_dump_queue(sc, q); \ 481 } \ 482} while (0) 483 484static void 485cpsw_init_slots(struct cpsw_softc *sc) 486{ 487 struct cpsw_slot *slot; 488 int i; 489 490 STAILQ_INIT(&sc->avail); 491 492 /* Put the slot descriptors onto the global avail list. */ 493 for (i = 0; i < nitems(sc->_slots); i++) { 494 slot = &sc->_slots[i]; 495 slot->bd_offset = cpsw_cpdma_bd_offset(i); 496 STAILQ_INSERT_TAIL(&sc->avail, slot, next); 497 } 498} 499 500static int 501cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested) 502{ 503 const int max_slots = nitems(sc->_slots); 504 struct cpsw_slot *slot; 505 int i; 506 507 if (requested < 0) 508 requested = max_slots; 509 510 for (i = 0; i < requested; ++i) { 511 slot = STAILQ_FIRST(&sc->avail); 512 if (slot == NULL) 513 return (0); 514 if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) { 515 device_printf(sc->dev, "failed to create dmamap\n"); 516 return (ENOMEM); 517 } 518 STAILQ_REMOVE_HEAD(&sc->avail, next); 519 STAILQ_INSERT_TAIL(&queue->avail, slot, next); 520 ++queue->avail_queue_len; 521 ++queue->queue_slots; 522 } 523 return (0); 524} 525 526static void 527cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot) 528{ 529 int error; 530 531 if (slot->dmamap) { 532 if (slot->mbuf) 533 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 534 error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap); 535 KASSERT(error == 0, ("Mapping still active")); 536 slot->dmamap = NULL; 537 } 538 if (slot->mbuf) { 539 m_freem(slot->mbuf); 540 slot->mbuf = NULL; 541 } 542} 543 544static void 545cpsw_reset(struct cpsw_softc *sc) 546{ 547 int i; 548 549 callout_stop(&sc->watchdog.callout); 550 551 /* Reset RMII/RGMII wrapper. */ 552 cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1); 553 while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1) 554 ; 555 556 /* Disable TX and RX interrupts for all cores. */ 557 for (i = 0; i < 3; ++i) { 558 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00); 559 cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00); 560 cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00); 561 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00); 562 } 563 564 /* Reset CPSW subsystem. */ 565 cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1); 566 while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1) 567 ; 568 569 /* Reset Sliver port 1 and 2 */ 570 for (i = 0; i < 2; i++) { 571 /* Reset */ 572 cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1); 573 while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1) 574 ; 575 } 576 577 /* Reset DMA controller. */ 578 cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1); 579 while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1) 580 ; 581 582 /* Disable TX & RX DMA */ 583 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0); 584 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0); 585 586 /* Clear all queues. */ 587 for (i = 0; i < 8; i++) { 588 cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0); 589 cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0); 590 cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0); 591 cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0); 592 } 593 594 /* Clear all interrupt Masks */ 595 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF); 596 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF); 597} 598 599static void 600cpsw_init(struct cpsw_softc *sc) 601{ 602 struct cpsw_slot *slot; 603 uint32_t reg; 604 605 /* Disable the interrupt pacing. */ 606 reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 607 reg &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 608 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg); 609 610 /* Clear ALE */ 611 cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL); 612 613 /* Enable ALE */ 614 reg = CPSW_ALE_CTL_ENABLE; 615 if (sc->dualemac) 616 reg |= CPSW_ALE_CTL_VLAN_AWARE; 617 cpsw_write_4(sc, CPSW_ALE_CONTROL, reg); 618 619 /* Set Host Port Mapping. */ 620 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210); 621 cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0); 622 623 /* Initialize ALE: set host port to forwarding(3). */ 624 cpsw_write_4(sc, CPSW_ALE_PORTCTL(0), 625 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 626 627 cpsw_write_4(sc, CPSW_SS_PTYPE, 0); 628 629 /* Enable statistics for ports 0, 1 and 2 */ 630 cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7); 631 632 /* Turn off flow control. */ 633 cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0); 634 635 /* Make IP hdr aligned with 4 */ 636 cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2); 637 638 /* Initialize RX Buffer Descriptors */ 639 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0); 640 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0); 641 642 /* Enable TX & RX DMA */ 643 cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1); 644 cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1); 645 646 /* Enable Interrupts for core 0 */ 647 cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF); 648 cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF); 649 cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF); 650 cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F); 651 652 /* Enable host Error Interrupt */ 653 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3); 654 655 /* Enable interrupts for RX and TX on Channel 0 */ 656 cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET, 657 CPSW_CPDMA_RX_INT(0) | CPSW_CPDMA_RX_INT_THRESH(0)); 658 cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1); 659 660 /* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */ 661 /* TODO Calculate MDCLK=CLK/(CLKDIV+1) */ 662 cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff); 663 664 /* Select MII in GMII_SEL, Internal Delay mode */ 665 //ti_scm_reg_write_4(0x650, 0); 666 667 /* Initialize active queues. */ 668 slot = STAILQ_FIRST(&sc->tx.active); 669 if (slot != NULL) 670 cpsw_write_hdp_slot(sc, &sc->tx, slot); 671 slot = STAILQ_FIRST(&sc->rx.active); 672 if (slot != NULL) 673 cpsw_write_hdp_slot(sc, &sc->rx, slot); 674 cpsw_rx_enqueue(sc); 675 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len); 676 cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS); 677 678 /* Activate network interface. */ 679 sc->rx.running = 1; 680 sc->tx.running = 1; 681 sc->watchdog.timer = 0; 682 callout_init(&sc->watchdog.callout, 0); 683 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 684} 685 686/* 687 * 688 * Device Probe, Attach, Detach. 689 * 690 */ 691 692static int 693cpsw_probe(device_t dev) 694{ 695 696 if (!ofw_bus_status_okay(dev)) 697 return (ENXIO); 698 699 if (!ofw_bus_is_compatible(dev, "ti,cpsw")) 700 return (ENXIO); 701 702 device_set_desc(dev, "3-port Switch Ethernet Subsystem"); 703 return (BUS_PROBE_DEFAULT); 704} 705 706static int 707cpsw_intr_attach(struct cpsw_softc *sc) 708{ 709 int i; 710 711 for (i = 0; i < CPSW_INTR_COUNT; i++) { 712 if (bus_setup_intr(sc->dev, sc->irq_res[i], 713 INTR_TYPE_NET | INTR_MPSAFE, NULL, 714 cpsw_intr_cb[i].cb, sc, &sc->ih_cookie[i]) != 0) { 715 return (-1); 716 } 717 } 718 719 return (0); 720} 721 722static void 723cpsw_intr_detach(struct cpsw_softc *sc) 724{ 725 int i; 726 727 for (i = 0; i < CPSW_INTR_COUNT; i++) { 728 if (sc->ih_cookie[i]) { 729 bus_teardown_intr(sc->dev, sc->irq_res[i], 730 sc->ih_cookie[i]); 731 } 732 } 733} 734 735static int 736cpsw_get_fdt_data(struct cpsw_softc *sc, int port) 737{ 738 char *name; 739 int len, phy, vlan; 740 pcell_t phy_id[3], vlan_id; 741 phandle_t child; 742 unsigned long mdio_child_addr; 743 744 /* Find any slave with phy_id */ 745 phy = -1; 746 vlan = -1; 747 for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) { 748 if (OF_getprop_alloc(child, "name", 1, (void **)&name) < 0) 749 continue; 750 if (sscanf(name, "slave@%x", &mdio_child_addr) != 1) { 751 OF_prop_free(name); 752 continue; 753 } 754 OF_prop_free(name); 755 if (mdio_child_addr != slave_mdio_addr[port]) 756 continue; 757 758 len = OF_getproplen(child, "phy_id"); 759 if (len / sizeof(pcell_t) == 2) { 760 /* Get phy address from fdt */ 761 if (OF_getencprop(child, "phy_id", phy_id, len) > 0) 762 phy = phy_id[1]; 763 } 764 765 len = OF_getproplen(child, "dual_emac_res_vlan"); 766 if (len / sizeof(pcell_t) == 1) { 767 /* Get phy address from fdt */ 768 if (OF_getencprop(child, "dual_emac_res_vlan", 769 &vlan_id, len) > 0) { 770 vlan = vlan_id; 771 } 772 } 773 774 break; 775 } 776 if (phy == -1) 777 return (ENXIO); 778 sc->port[port].phy = phy; 779 sc->port[port].vlan = vlan; 780 781 return (0); 782} 783 784static int 785cpsw_attach(device_t dev) 786{ 787 bus_dma_segment_t segs[1]; 788 int error, i, nsegs; 789 struct cpsw_softc *sc; 790 uint32_t reg; 791 792 sc = device_get_softc(dev); 793 sc->dev = dev; 794 sc->node = ofw_bus_get_node(dev); 795 getbinuptime(&sc->attach_uptime); 796 797 if (OF_getencprop(sc->node, "active_slave", &sc->active_slave, 798 sizeof(sc->active_slave)) <= 0) { 799 sc->active_slave = 0; 800 } 801 if (sc->active_slave > 1) 802 sc->active_slave = 1; 803 804 if (OF_hasprop(sc->node, "dual_emac")) 805 sc->dualemac = 1; 806 807 for (i = 0; i < CPSW_PORTS; i++) { 808 if (!sc->dualemac && i != sc->active_slave) 809 continue; 810 if (cpsw_get_fdt_data(sc, i) != 0) { 811 device_printf(dev, 812 "failed to get PHY address from FDT\n"); 813 return (ENXIO); 814 } 815 } 816 817 /* Initialize mutexes */ 818 mtx_init(&sc->tx.lock, device_get_nameunit(dev), 819 "cpsw TX lock", MTX_DEF); 820 mtx_init(&sc->rx.lock, device_get_nameunit(dev), 821 "cpsw RX lock", MTX_DEF); 822 823 /* Allocate IRQ resources */ 824 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 825 if (error) { 826 device_printf(dev, "could not allocate IRQ resources\n"); 827 cpsw_detach(dev); 828 return (ENXIO); 829 } 830 831 sc->mem_rid = 0; 832 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 833 &sc->mem_rid, RF_ACTIVE); 834 if (sc->mem_res == NULL) { 835 device_printf(sc->dev, "failed to allocate memory resource\n"); 836 cpsw_detach(dev); 837 return (ENXIO); 838 } 839 840 reg = cpsw_read_4(sc, CPSW_SS_IDVER); 841 device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7), 842 reg & 0xFF, (reg >> 11) & 0x1F); 843 844 cpsw_add_sysctls(sc); 845 846 /* Allocate a busdma tag and DMA safe memory for mbufs. */ 847 error = bus_dma_tag_create( 848 bus_get_dma_tag(sc->dev), /* parent */ 849 1, 0, /* alignment, boundary */ 850 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 851 BUS_SPACE_MAXADDR, /* highaddr */ 852 NULL, NULL, /* filtfunc, filtfuncarg */ 853 MCLBYTES, CPSW_TXFRAGS, /* maxsize, nsegments */ 854 MCLBYTES, 0, /* maxsegsz, flags */ 855 NULL, NULL, /* lockfunc, lockfuncarg */ 856 &sc->mbuf_dtag); /* dmatag */ 857 if (error) { 858 device_printf(dev, "bus_dma_tag_create failed\n"); 859 cpsw_detach(dev); 860 return (error); 861 } 862 863 /* Allocate the null mbuf and pre-sync it. */ 864 sc->null_mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 865 memset(sc->null_mbuf->m_data, 0, sc->null_mbuf->m_ext.ext_size); 866 bus_dmamap_create(sc->mbuf_dtag, 0, &sc->null_mbuf_dmamap); 867 bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, sc->null_mbuf_dmamap, 868 sc->null_mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 869 bus_dmamap_sync(sc->mbuf_dtag, sc->null_mbuf_dmamap, 870 BUS_DMASYNC_PREWRITE); 871 sc->null_mbuf_paddr = segs[0].ds_addr; 872 873 cpsw_init_slots(sc); 874 875 /* Allocate slots to TX and RX queues. */ 876 STAILQ_INIT(&sc->rx.avail); 877 STAILQ_INIT(&sc->rx.active); 878 STAILQ_INIT(&sc->tx.avail); 879 STAILQ_INIT(&sc->tx.active); 880 // For now: 128 slots to TX, rest to RX. 881 // XXX TODO: start with 32/64 and grow dynamically based on demand. 882 if (cpsw_add_slots(sc, &sc->tx, 128) || 883 cpsw_add_slots(sc, &sc->rx, -1)) { 884 device_printf(dev, "failed to allocate dmamaps\n"); 885 cpsw_detach(dev); 886 return (ENOMEM); 887 } 888 device_printf(dev, "Initial queue size TX=%d RX=%d\n", 889 sc->tx.queue_slots, sc->rx.queue_slots); 890 891 sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0); 892 sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0); 893 894 if (cpsw_intr_attach(sc) == -1) { 895 device_printf(dev, "failed to setup interrupts\n"); 896 cpsw_detach(dev); 897 return (ENXIO); 898 } 899 900#ifdef CPSW_ETHERSWITCH 901 for (i = 0; i < CPSW_VLANS; i++) 902 cpsw_vgroups[i].vid = -1; 903#endif 904 905 /* Reset the controller. */ 906 cpsw_reset(sc); 907 cpsw_init(sc); 908 909 for (i = 0; i < CPSW_PORTS; i++) { 910 if (!sc->dualemac && i != sc->active_slave) 911 continue; 912 sc->port[i].dev = device_add_child(dev, "cpsw", i); 913 if (sc->port[i].dev == NULL) { 914 cpsw_detach(dev); 915 return (ENXIO); 916 } 917 } 918 bus_generic_probe(dev); 919 bus_generic_attach(dev); 920 921 return (0); 922} 923 924static int 925cpsw_detach(device_t dev) 926{ 927 struct cpsw_softc *sc; 928 int error, i; 929 930 bus_generic_detach(dev); 931 sc = device_get_softc(dev); 932 933 for (i = 0; i < CPSW_PORTS; i++) { 934 if (sc->port[i].dev) 935 device_delete_child(dev, sc->port[i].dev); 936 } 937 938 if (device_is_attached(dev)) { 939 callout_stop(&sc->watchdog.callout); 940 callout_drain(&sc->watchdog.callout); 941 } 942 943 /* Stop and release all interrupts */ 944 cpsw_intr_detach(sc); 945 946 /* Free dmamaps and mbufs */ 947 for (i = 0; i < nitems(sc->_slots); ++i) 948 cpsw_free_slot(sc, &sc->_slots[i]); 949 950 /* Free null mbuf. */ 951 if (sc->null_mbuf_dmamap) { 952 bus_dmamap_unload(sc->mbuf_dtag, sc->null_mbuf_dmamap); 953 error = bus_dmamap_destroy(sc->mbuf_dtag, sc->null_mbuf_dmamap); 954 KASSERT(error == 0, ("Mapping still active")); 955 m_freem(sc->null_mbuf); 956 } 957 958 /* Free DMA tag */ 959 if (sc->mbuf_dtag) { 960 error = bus_dma_tag_destroy(sc->mbuf_dtag); 961 KASSERT(error == 0, ("Unable to destroy DMA tag")); 962 } 963 964 /* Free IO memory handler */ 965 if (sc->mem_res != NULL) 966 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 967 bus_release_resources(dev, irq_res_spec, sc->irq_res); 968 969 /* Destroy mutexes */ 970 mtx_destroy(&sc->rx.lock); 971 mtx_destroy(&sc->tx.lock); 972 973 /* Detach the switch device, if present. */ 974 error = bus_generic_detach(dev); 975 if (error != 0) 976 return (error); 977 978 return (device_delete_children(dev)); 979} 980 981static phandle_t 982cpsw_get_node(device_t bus, device_t dev) 983{ 984 985 /* Share controller node with port device. */ 986 return (ofw_bus_get_node(bus)); 987} 988 989static int 990cpswp_probe(device_t dev) 991{ 992 993 if (device_get_unit(dev) > 1) { 994 device_printf(dev, "Only two ports are supported.\n"); 995 return (ENXIO); 996 } 997 device_set_desc(dev, "Ethernet Switch Port"); 998 999 return (BUS_PROBE_DEFAULT); 1000} 1001 1002static int 1003cpswp_attach(device_t dev) 1004{ 1005 int error; 1006 struct ifnet *ifp; 1007 struct cpswp_softc *sc; 1008 uint32_t reg; 1009 uint8_t mac_addr[ETHER_ADDR_LEN]; 1010 1011 sc = device_get_softc(dev); 1012 sc->dev = dev; 1013 sc->pdev = device_get_parent(dev); 1014 sc->swsc = device_get_softc(sc->pdev); 1015 sc->unit = device_get_unit(dev); 1016 sc->phy = sc->swsc->port[sc->unit].phy; 1017 sc->vlan = sc->swsc->port[sc->unit].vlan; 1018 if (sc->swsc->dualemac && sc->vlan == -1) 1019 sc->vlan = sc->unit + 1; 1020 1021 if (sc->unit == 0) { 1022 sc->physel = MDIOUSERPHYSEL0; 1023 sc->phyaccess = MDIOUSERACCESS0; 1024 } else { 1025 sc->physel = MDIOUSERPHYSEL1; 1026 sc->phyaccess = MDIOUSERACCESS1; 1027 } 1028 1029 mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock", 1030 MTX_DEF); 1031 1032 /* Allocate network interface */ 1033 ifp = sc->ifp = if_alloc(IFT_ETHER); 1034 if (ifp == NULL) { 1035 cpswp_detach(dev); 1036 return (ENXIO); 1037 } 1038 1039 if_initname(ifp, device_get_name(sc->dev), sc->unit); 1040 ifp->if_softc = sc; 1041 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 1042 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM; //FIXME VLAN? 1043 ifp->if_capenable = ifp->if_capabilities; 1044 1045 ifp->if_init = cpswp_init; 1046 ifp->if_start = cpswp_start; 1047 ifp->if_ioctl = cpswp_ioctl; 1048 1049 ifp->if_snd.ifq_drv_maxlen = sc->swsc->tx.queue_slots; 1050 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1051 IFQ_SET_READY(&ifp->if_snd); 1052 1053 /* Get high part of MAC address from control module (mac_id[0|1]_hi) */ 1054 ti_scm_reg_read_4(SCM_MAC_ID0_HI + sc->unit * 8, ®); 1055 mac_addr[0] = reg & 0xFF; 1056 mac_addr[1] = (reg >> 8) & 0xFF; 1057 mac_addr[2] = (reg >> 16) & 0xFF; 1058 mac_addr[3] = (reg >> 24) & 0xFF; 1059 1060 /* Get low part of MAC address from control module (mac_id[0|1]_lo) */ 1061 ti_scm_reg_read_4(SCM_MAC_ID0_LO + sc->unit * 8, ®); 1062 mac_addr[4] = reg & 0xFF; 1063 mac_addr[5] = (reg >> 8) & 0xFF; 1064 1065 error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd, 1066 cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0); 1067 if (error) { 1068 device_printf(dev, "attaching PHYs failed\n"); 1069 cpswp_detach(dev); 1070 return (error); 1071 } 1072 sc->mii = device_get_softc(sc->miibus); 1073 1074 /* Select PHY and enable interrupts */ 1075 cpsw_write_4(sc->swsc, sc->physel, 1076 MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F)); 1077 1078 ether_ifattach(sc->ifp, mac_addr); 1079 callout_init(&sc->mii_callout, 0); 1080 1081 return (0); 1082} 1083 1084static int 1085cpswp_detach(device_t dev) 1086{ 1087 struct cpswp_softc *sc; 1088 1089 sc = device_get_softc(dev); 1090 CPSW_DEBUGF(sc->swsc, ("")); 1091 if (device_is_attached(dev)) { 1092 ether_ifdetach(sc->ifp); 1093 CPSW_PORT_LOCK(sc); 1094 cpswp_stop_locked(sc); 1095 CPSW_PORT_UNLOCK(sc); 1096 callout_drain(&sc->mii_callout); 1097 } 1098 1099 bus_generic_detach(dev); 1100 1101 if_free(sc->ifp); 1102 mtx_destroy(&sc->lock); 1103 1104 return (0); 1105} 1106 1107/* 1108 * 1109 * Init/Shutdown. 1110 * 1111 */ 1112 1113static int 1114cpsw_ports_down(struct cpsw_softc *sc) 1115{ 1116 struct cpswp_softc *psc; 1117 struct ifnet *ifp1, *ifp2; 1118 1119 if (!sc->dualemac) 1120 return (1); 1121 psc = device_get_softc(sc->port[0].dev); 1122 ifp1 = psc->ifp; 1123 psc = device_get_softc(sc->port[1].dev); 1124 ifp2 = psc->ifp; 1125 if ((ifp1->if_flags & IFF_UP) == 0 && (ifp2->if_flags & IFF_UP) == 0) 1126 return (1); 1127 1128 return (0); 1129} 1130 1131static void 1132cpswp_init(void *arg) 1133{ 1134 struct cpswp_softc *sc = arg; 1135 1136 CPSW_DEBUGF(sc->swsc, ("")); 1137 CPSW_PORT_LOCK(sc); 1138 cpswp_init_locked(arg); 1139 CPSW_PORT_UNLOCK(sc); 1140} 1141 1142static void 1143cpswp_init_locked(void *arg) 1144{ 1145#ifdef CPSW_ETHERSWITCH 1146 int i; 1147#endif 1148 struct cpswp_softc *sc = arg; 1149 struct ifnet *ifp; 1150 uint32_t reg; 1151 1152 CPSW_DEBUGF(sc->swsc, ("")); 1153 CPSW_PORT_LOCK_ASSERT(sc); 1154 ifp = sc->ifp; 1155 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1156 return; 1157 1158 getbinuptime(&sc->init_uptime); 1159 1160 if (!sc->swsc->rx.running && !sc->swsc->tx.running) { 1161 /* Reset the controller. */ 1162 cpsw_reset(sc->swsc); 1163 cpsw_init(sc->swsc); 1164 } 1165 1166 /* Set Slave Mapping. */ 1167 cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210); 1168 cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1), 1169 0x33221100); 1170 cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2); 1171 /* Enable MAC RX/TX modules. */ 1172 /* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */ 1173 /* Huh? Docs call bit 0 "Loopback" some places, "FullDuplex" others. */ 1174 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1175 reg |= CPSW_SL_MACTL_GMII_ENABLE; 1176 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1177 1178 /* Initialize ALE: set port to forwarding, initialize addrs */ 1179 cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1), 1180 ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD); 1181 cpswp_ale_update_addresses(sc, 1); 1182 1183 if (sc->swsc->dualemac) { 1184 /* Set Port VID. */ 1185 cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1), 1186 sc->vlan & 0xfff); 1187 cpsw_ale_update_vlan_table(sc->swsc, sc->vlan, 1188 (1 << (sc->unit + 1)) | (1 << 0), /* Member list */ 1189 (1 << (sc->unit + 1)) | (1 << 0), /* Untagged egress */ 1190 (1 << (sc->unit + 1)) | (1 << 0), 0); /* mcast reg flood */ 1191#ifdef CPSW_ETHERSWITCH 1192 for (i = 0; i < CPSW_VLANS; i++) { 1193 if (cpsw_vgroups[i].vid != -1) 1194 continue; 1195 cpsw_vgroups[i].vid = sc->vlan; 1196 break; 1197 } 1198#endif 1199 } 1200 1201 mii_mediachg(sc->mii); 1202 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 1203 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1204 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1205} 1206 1207static int 1208cpsw_shutdown(device_t dev) 1209{ 1210 struct cpsw_softc *sc; 1211 struct cpswp_softc *psc; 1212 int i; 1213 1214 sc = device_get_softc(dev); 1215 CPSW_DEBUGF(sc, ("")); 1216 for (i = 0; i < CPSW_PORTS; i++) { 1217 if (!sc->dualemac && i != sc->active_slave) 1218 continue; 1219 psc = device_get_softc(sc->port[i].dev); 1220 CPSW_PORT_LOCK(psc); 1221 cpswp_stop_locked(psc); 1222 CPSW_PORT_UNLOCK(psc); 1223 } 1224 1225 return (0); 1226} 1227 1228static void 1229cpsw_rx_teardown(struct cpsw_softc *sc) 1230{ 1231 int i = 0; 1232 1233 CPSW_RX_LOCK(sc); 1234 CPSW_DEBUGF(sc, ("starting RX teardown")); 1235 sc->rx.teardown = 1; 1236 cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0); 1237 CPSW_RX_UNLOCK(sc); 1238 while (sc->rx.running) { 1239 if (++i > 10) { 1240 device_printf(sc->dev, 1241 "Unable to cleanly shutdown receiver\n"); 1242 return; 1243 } 1244 DELAY(200); 1245 } 1246 if (!sc->rx.running) 1247 CPSW_DEBUGF(sc, ("finished RX teardown (%d retries)", i)); 1248} 1249 1250static void 1251cpsw_tx_teardown(struct cpsw_softc *sc) 1252{ 1253 int i = 0; 1254 1255 CPSW_TX_LOCK(sc); 1256 CPSW_DEBUGF(sc, ("starting TX teardown")); 1257 /* Start the TX queue teardown if queue is not empty. */ 1258 if (STAILQ_FIRST(&sc->tx.active) != NULL) 1259 cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0); 1260 else 1261 sc->tx.teardown = 1; 1262 cpsw_tx_dequeue(sc); 1263 while (sc->tx.running && ++i < 10) { 1264 DELAY(200); 1265 cpsw_tx_dequeue(sc); 1266 } 1267 if (sc->tx.running) { 1268 device_printf(sc->dev, 1269 "Unable to cleanly shutdown transmitter\n"); 1270 } 1271 CPSW_DEBUGF(sc, 1272 ("finished TX teardown (%d retries, %d idle buffers)", i, 1273 sc->tx.active_queue_len)); 1274 CPSW_TX_UNLOCK(sc); 1275} 1276 1277static void 1278cpswp_stop_locked(struct cpswp_softc *sc) 1279{ 1280 struct ifnet *ifp; 1281 uint32_t reg; 1282 1283 ifp = sc->ifp; 1284 CPSW_DEBUGF(sc->swsc, ("")); 1285 CPSW_PORT_LOCK_ASSERT(sc); 1286 1287 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1288 return; 1289 1290 /* Disable interface */ 1291 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1292 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1293 1294 /* Stop ticker */ 1295 callout_stop(&sc->mii_callout); 1296 1297 /* Tear down the RX/TX queues. */ 1298 if (cpsw_ports_down(sc->swsc)) { 1299 cpsw_rx_teardown(sc->swsc); 1300 cpsw_tx_teardown(sc->swsc); 1301 } 1302 1303 /* Stop MAC RX/TX modules. */ 1304 reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit)); 1305 reg &= ~CPSW_SL_MACTL_GMII_ENABLE; 1306 cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg); 1307 1308 if (cpsw_ports_down(sc->swsc)) { 1309 /* Capture stats before we reset controller. */ 1310 cpsw_stats_collect(sc->swsc); 1311 1312 cpsw_reset(sc->swsc); 1313 cpsw_init(sc->swsc); 1314 } 1315} 1316 1317/* 1318 * Suspend/Resume. 1319 */ 1320 1321static int 1322cpsw_suspend(device_t dev) 1323{ 1324 struct cpsw_softc *sc; 1325 struct cpswp_softc *psc; 1326 int i; 1327 1328 sc = device_get_softc(dev); 1329 CPSW_DEBUGF(sc, ("")); 1330 for (i = 0; i < CPSW_PORTS; i++) { 1331 if (!sc->dualemac && i != sc->active_slave) 1332 continue; 1333 psc = device_get_softc(sc->port[i].dev); 1334 CPSW_PORT_LOCK(psc); 1335 cpswp_stop_locked(psc); 1336 CPSW_PORT_UNLOCK(psc); 1337 } 1338 1339 return (0); 1340} 1341 1342static int 1343cpsw_resume(device_t dev) 1344{ 1345 struct cpsw_softc *sc; 1346 1347 sc = device_get_softc(dev); 1348 CPSW_DEBUGF(sc, ("UNIMPLEMENTED")); 1349 1350 return (0); 1351} 1352 1353/* 1354 * 1355 * IOCTL 1356 * 1357 */ 1358 1359static void 1360cpsw_set_promisc(struct cpswp_softc *sc, int set) 1361{ 1362 uint32_t reg; 1363 1364 /* 1365 * Enabling promiscuous mode requires ALE_BYPASS to be enabled. 1366 * That disables the ALE forwarding logic and causes every 1367 * packet to be sent only to the host port. In bypass mode, 1368 * the ALE processes host port transmit packets the same as in 1369 * normal mode. 1370 */ 1371 reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL); 1372 reg &= ~CPSW_ALE_CTL_BYPASS; 1373 if (set) 1374 reg |= CPSW_ALE_CTL_BYPASS; 1375 cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg); 1376} 1377 1378static void 1379cpsw_set_allmulti(struct cpswp_softc *sc, int set) 1380{ 1381 if (set) { 1382 printf("All-multicast mode unimplemented\n"); 1383 } 1384} 1385 1386static int 1387cpswp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1388{ 1389 struct cpswp_softc *sc; 1390 struct ifreq *ifr; 1391 int error; 1392 uint32_t changed; 1393 1394 error = 0; 1395 sc = ifp->if_softc; 1396 ifr = (struct ifreq *)data; 1397 1398 switch (command) { 1399 case SIOCSIFFLAGS: 1400 CPSW_PORT_LOCK(sc); 1401 if (ifp->if_flags & IFF_UP) { 1402 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1403 changed = ifp->if_flags ^ sc->if_flags; 1404 CPSW_DEBUGF(sc->swsc, 1405 ("SIOCSIFFLAGS: UP & RUNNING (changed=0x%x)", 1406 changed)); 1407 if (changed & IFF_PROMISC) 1408 cpsw_set_promisc(sc, 1409 ifp->if_flags & IFF_PROMISC); 1410 if (changed & IFF_ALLMULTI) 1411 cpsw_set_allmulti(sc, 1412 ifp->if_flags & IFF_ALLMULTI); 1413 } else { 1414 CPSW_DEBUGF(sc->swsc, 1415 ("SIOCSIFFLAGS: starting up")); 1416 cpswp_init_locked(sc); 1417 } 1418 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1419 CPSW_DEBUGF(sc->swsc, ("SIOCSIFFLAGS: shutting down")); 1420 cpswp_stop_locked(sc); 1421 } 1422 1423 sc->if_flags = ifp->if_flags; 1424 CPSW_PORT_UNLOCK(sc); 1425 break; 1426 case SIOCADDMULTI: 1427 cpswp_ale_update_addresses(sc, 0); 1428 break; 1429 case SIOCDELMULTI: 1430 /* Ugh. DELMULTI doesn't provide the specific address 1431 being removed, so the best we can do is remove 1432 everything and rebuild it all. */ 1433 cpswp_ale_update_addresses(sc, 1); 1434 break; 1435 case SIOCGIFMEDIA: 1436 case SIOCSIFMEDIA: 1437 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command); 1438 break; 1439 default: 1440 error = ether_ioctl(ifp, command, data); 1441 } 1442 return (error); 1443} 1444 1445/* 1446 * 1447 * MIIBUS 1448 * 1449 */ 1450static int 1451cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg) 1452{ 1453 uint32_t r, retries = CPSW_MIIBUS_RETRIES; 1454 1455 while (--retries) { 1456 r = cpsw_read_4(sc, reg); 1457 if ((r & MDIO_PHYACCESS_GO) == 0) 1458 return (1); 1459 DELAY(CPSW_MIIBUS_DELAY); 1460 } 1461 1462 return (0); 1463} 1464 1465static int 1466cpswp_miibus_readreg(device_t dev, int phy, int reg) 1467{ 1468 struct cpswp_softc *sc; 1469 uint32_t cmd, r; 1470 1471 sc = device_get_softc(dev); 1472 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1473 device_printf(dev, "MDIO not ready to read\n"); 1474 return (0); 1475 } 1476 1477 /* Set GO, reg, phy */ 1478 cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16; 1479 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1480 1481 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1482 device_printf(dev, "MDIO timed out during read\n"); 1483 return (0); 1484 } 1485 1486 r = cpsw_read_4(sc->swsc, sc->phyaccess); 1487 if ((r & MDIO_PHYACCESS_ACK) == 0) { 1488 device_printf(dev, "Failed to read from PHY.\n"); 1489 r = 0; 1490 } 1491 return (r & 0xFFFF); 1492} 1493 1494static int 1495cpswp_miibus_writereg(device_t dev, int phy, int reg, int value) 1496{ 1497 struct cpswp_softc *sc; 1498 uint32_t cmd; 1499 1500 sc = device_get_softc(dev); 1501 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1502 device_printf(dev, "MDIO not ready to write\n"); 1503 return (0); 1504 } 1505 1506 /* Set GO, WRITE, reg, phy, and value */ 1507 cmd = MDIO_PHYACCESS_GO | MDIO_PHYACCESS_WRITE | 1508 (reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF); 1509 cpsw_write_4(sc->swsc, sc->phyaccess, cmd); 1510 1511 if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) { 1512 device_printf(dev, "MDIO timed out during write\n"); 1513 return (0); 1514 } 1515 1516 return (0); 1517} 1518 1519static void 1520cpswp_miibus_statchg(device_t dev) 1521{ 1522 struct cpswp_softc *sc; 1523 uint32_t mac_control, reg; 1524 1525 sc = device_get_softc(dev); 1526 CPSW_DEBUGF(sc->swsc, ("")); 1527 1528 reg = CPSW_SL_MACCONTROL(sc->unit); 1529 mac_control = cpsw_read_4(sc->swsc, reg); 1530 mac_control &= ~(CPSW_SL_MACTL_GIG | CPSW_SL_MACTL_IFCTL_A | 1531 CPSW_SL_MACTL_IFCTL_B | CPSW_SL_MACTL_FULLDUPLEX); 1532 1533 switch(IFM_SUBTYPE(sc->mii->mii_media_active)) { 1534 case IFM_1000_SX: 1535 case IFM_1000_LX: 1536 case IFM_1000_CX: 1537 case IFM_1000_T: 1538 mac_control |= CPSW_SL_MACTL_GIG; 1539 break; 1540 1541 case IFM_100_TX: 1542 mac_control |= CPSW_SL_MACTL_IFCTL_A; 1543 break; 1544 } 1545 if (sc->mii->mii_media_active & IFM_FDX) 1546 mac_control |= CPSW_SL_MACTL_FULLDUPLEX; 1547 1548 cpsw_write_4(sc->swsc, reg, mac_control); 1549} 1550 1551/* 1552 * 1553 * Transmit/Receive Packets. 1554 * 1555 */ 1556static void 1557cpsw_intr_rx(void *arg) 1558{ 1559 struct cpsw_softc *sc; 1560 struct ifnet *ifp; 1561 struct mbuf *received, *next; 1562 1563 sc = (struct cpsw_softc *)arg; 1564 CPSW_RX_LOCK(sc); 1565 if (sc->rx.teardown) { 1566 sc->rx.running = 0; 1567 sc->rx.teardown = 0; 1568 cpsw_write_cp(sc, &sc->rx, 0xfffffffc); 1569 } 1570 received = cpsw_rx_dequeue(sc); 1571 cpsw_rx_enqueue(sc); 1572 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1); 1573 CPSW_RX_UNLOCK(sc); 1574 1575 while (received != NULL) { 1576 next = received->m_nextpkt; 1577 received->m_nextpkt = NULL; 1578 ifp = received->m_pkthdr.rcvif; 1579 (*ifp->if_input)(ifp, received); 1580 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1581 received = next; 1582 } 1583} 1584 1585static struct mbuf * 1586cpsw_rx_dequeue(struct cpsw_softc *sc) 1587{ 1588 struct cpsw_cpdma_bd bd; 1589 struct cpsw_slot *last, *slot; 1590 struct cpswp_softc *psc; 1591 struct mbuf *mb_head, *mb_tail; 1592 int port, removed = 0; 1593 1594 last = NULL; 1595 mb_head = mb_tail = NULL; 1596 1597 /* Pull completed packets off hardware RX queue. */ 1598 while ((slot = STAILQ_FIRST(&sc->rx.active)) != NULL) { 1599 cpsw_cpdma_read_bd(sc, slot, &bd); 1600 1601 /* 1602 * Stop on packets still in use by hardware, but do not stop 1603 * on packets with the teardown complete flag, they will be 1604 * discarded later. 1605 */ 1606 if ((bd.flags & (CPDMA_BD_OWNER | CPDMA_BD_TDOWNCMPLT)) == 1607 CPDMA_BD_OWNER) 1608 break; 1609 1610 last = slot; 1611 ++removed; 1612 STAILQ_REMOVE_HEAD(&sc->rx.active, next); 1613 STAILQ_INSERT_TAIL(&sc->rx.avail, slot, next); 1614 1615 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTREAD); 1616 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1617 1618 if (bd.flags & CPDMA_BD_TDOWNCMPLT) { 1619 CPSW_DEBUGF(sc, ("RX teardown is complete")); 1620 m_freem(slot->mbuf); 1621 slot->mbuf = NULL; 1622 sc->rx.running = 0; 1623 sc->rx.teardown = 0; 1624 break; 1625 } 1626 1627 port = (bd.flags & CPDMA_BD_PORT_MASK) - 1; 1628 KASSERT(port >= 0 && port <= 1, 1629 ("patcket received with invalid port: %d", port)); 1630 psc = device_get_softc(sc->port[port].dev); 1631 1632 /* Set up mbuf */ 1633 /* TODO: track SOP/EOP bits to assemble a full mbuf 1634 out of received fragments. */ 1635 slot->mbuf->m_data += bd.bufoff; 1636 slot->mbuf->m_len = bd.pktlen - 4; 1637 slot->mbuf->m_pkthdr.len = bd.pktlen - 4; 1638 slot->mbuf->m_flags |= M_PKTHDR; 1639 slot->mbuf->m_pkthdr.rcvif = psc->ifp; 1640 slot->mbuf->m_nextpkt = NULL; 1641 1642 if ((psc->ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1643 /* check for valid CRC by looking into pkt_err[5:4] */ 1644 if ((bd.flags & CPDMA_BD_PKT_ERR_MASK) == 0) { 1645 slot->mbuf->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1646 slot->mbuf->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1647 slot->mbuf->m_pkthdr.csum_data = 0xffff; 1648 } 1649 } 1650 1651 /* Add mbuf to packet list to be returned. */ 1652 if (mb_tail) { 1653 mb_tail->m_nextpkt = slot->mbuf; 1654 } else { 1655 mb_head = slot->mbuf; 1656 } 1657 mb_tail = slot->mbuf; 1658 slot->mbuf = NULL; 1659 if (sc->rx_batch > 0 && sc->rx_batch == removed) 1660 break; 1661 } 1662 1663 if (removed != 0) { 1664 cpsw_write_cp_slot(sc, &sc->rx, last); 1665 sc->rx.queue_removes += removed; 1666 sc->rx.avail_queue_len += removed; 1667 sc->rx.active_queue_len -= removed; 1668 if (sc->rx.avail_queue_len > sc->rx.max_avail_queue_len) 1669 sc->rx.max_avail_queue_len = sc->rx.avail_queue_len; 1670 CPSW_DEBUGF(sc, ("Removed %d received packet(s) from RX queue", removed)); 1671 } 1672 1673 return (mb_head); 1674} 1675 1676static void 1677cpsw_rx_enqueue(struct cpsw_softc *sc) 1678{ 1679 bus_dma_segment_t seg[1]; 1680 struct cpsw_cpdma_bd bd; 1681 struct cpsw_slot *first_new_slot, *last_old_slot, *next, *slot; 1682 int error, nsegs, added = 0; 1683 uint32_t flags; 1684 1685 /* Register new mbufs with hardware. */ 1686 first_new_slot = NULL; 1687 last_old_slot = STAILQ_LAST(&sc->rx.active, cpsw_slot, next); 1688 while ((slot = STAILQ_FIRST(&sc->rx.avail)) != NULL) { 1689 if (first_new_slot == NULL) 1690 first_new_slot = slot; 1691 if (slot->mbuf == NULL) { 1692 slot->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1693 if (slot->mbuf == NULL) { 1694 device_printf(sc->dev, 1695 "Unable to fill RX queue\n"); 1696 break; 1697 } 1698 slot->mbuf->m_len = 1699 slot->mbuf->m_pkthdr.len = 1700 slot->mbuf->m_ext.ext_size; 1701 } 1702 1703 error = bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, slot->dmamap, 1704 slot->mbuf, seg, &nsegs, BUS_DMA_NOWAIT); 1705 1706 KASSERT(nsegs == 1, ("More than one segment (nsegs=%d)", nsegs)); 1707 KASSERT(error == 0, ("DMA error (error=%d)", error)); 1708 if (error != 0 || nsegs != 1) { 1709 device_printf(sc->dev, 1710 "%s: Can't prep RX buf for DMA (nsegs=%d, error=%d)\n", 1711 __func__, nsegs, error); 1712 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1713 m_freem(slot->mbuf); 1714 slot->mbuf = NULL; 1715 break; 1716 } 1717 1718 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_PREREAD); 1719 1720 /* Create and submit new rx descriptor. */ 1721 if ((next = STAILQ_NEXT(slot, next)) != NULL) 1722 bd.next = cpsw_cpdma_bd_paddr(sc, next); 1723 else 1724 bd.next = 0; 1725 bd.bufptr = seg->ds_addr; 1726 bd.bufoff = 0; 1727 bd.buflen = MCLBYTES - 1; 1728 bd.pktlen = bd.buflen; 1729 bd.flags = CPDMA_BD_OWNER; 1730 cpsw_cpdma_write_bd(sc, slot, &bd); 1731 ++added; 1732 1733 STAILQ_REMOVE_HEAD(&sc->rx.avail, next); 1734 STAILQ_INSERT_TAIL(&sc->rx.active, slot, next); 1735 } 1736 1737 if (added == 0 || first_new_slot == NULL) 1738 return; 1739 1740 CPSW_DEBUGF(sc, ("Adding %d buffers to RX queue", added)); 1741 1742 /* Link new entries to hardware RX queue. */ 1743 if (last_old_slot == NULL) { 1744 /* Start a fresh queue. */ 1745 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1746 } else { 1747 /* Add buffers to end of current queue. */ 1748 cpsw_cpdma_write_bd_next(sc, last_old_slot, first_new_slot); 1749 /* If underrun, restart queue. */ 1750 if ((flags = cpsw_cpdma_read_bd_flags(sc, last_old_slot)) & 1751 CPDMA_BD_EOQ) { 1752 flags &= ~CPDMA_BD_EOQ; 1753 cpsw_cpdma_write_bd_flags(sc, last_old_slot, flags); 1754 cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot); 1755 sc->rx.queue_restart++; 1756 } 1757 } 1758 sc->rx.queue_adds += added; 1759 sc->rx.avail_queue_len -= added; 1760 sc->rx.active_queue_len += added; 1761 cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added); 1762 if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) { 1763 sc->rx.max_active_queue_len = sc->rx.active_queue_len; 1764 } 1765} 1766 1767static void 1768cpswp_start(struct ifnet *ifp) 1769{ 1770 struct cpswp_softc *sc; 1771 1772 sc = ifp->if_softc; 1773 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1774 sc->swsc->tx.running == 0) { 1775 return; 1776 } 1777 CPSW_TX_LOCK(sc->swsc); 1778 cpswp_tx_enqueue(sc); 1779 cpsw_tx_dequeue(sc->swsc); 1780 CPSW_TX_UNLOCK(sc->swsc); 1781} 1782 1783static void 1784cpsw_intr_tx(void *arg) 1785{ 1786 struct cpsw_softc *sc; 1787 1788 sc = (struct cpsw_softc *)arg; 1789 CPSW_TX_LOCK(sc); 1790 if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc) 1791 cpsw_write_cp(sc, &sc->tx, 0xfffffffc); 1792 cpsw_tx_dequeue(sc); 1793 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2); 1794 CPSW_TX_UNLOCK(sc); 1795} 1796 1797static void 1798cpswp_tx_enqueue(struct cpswp_softc *sc) 1799{ 1800 bus_dma_segment_t segs[CPSW_TXFRAGS]; 1801 struct cpsw_cpdma_bd bd; 1802 struct cpsw_slot *first_new_slot, *last, *last_old_slot, *next, *slot; 1803 struct mbuf *m0; 1804 int error, flags, nsegs, seg, added = 0, padlen; 1805 1806 flags = 0; 1807 if (sc->swsc->dualemac) { 1808 flags = CPDMA_BD_TO_PORT | 1809 ((sc->unit + 1) & CPDMA_BD_PORT_MASK); 1810 } 1811 /* Pull pending packets from IF queue and prep them for DMA. */ 1812 last = NULL; 1813 first_new_slot = NULL; 1814 last_old_slot = STAILQ_LAST(&sc->swsc->tx.active, cpsw_slot, next); 1815 while ((slot = STAILQ_FIRST(&sc->swsc->tx.avail)) != NULL) { 1816 IF_DEQUEUE(&sc->ifp->if_snd, m0); 1817 if (m0 == NULL) 1818 break; 1819 1820 slot->mbuf = m0; 1821 padlen = ETHER_MIN_LEN - slot->mbuf->m_pkthdr.len; 1822 if (padlen < 0) 1823 padlen = 0; 1824 1825 /* Create mapping in DMA memory */ 1826 error = bus_dmamap_load_mbuf_sg(sc->swsc->mbuf_dtag, 1827 slot->dmamap, slot->mbuf, segs, &nsegs, BUS_DMA_NOWAIT); 1828 /* If the packet is too fragmented, try to simplify. */ 1829 if (error == EFBIG || 1830 (error == 0 && 1831 nsegs + (padlen > 0 ? 1 : 0) > sc->swsc->tx.avail_queue_len)) { 1832 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1833 if (padlen > 0) /* May as well add padding. */ 1834 m_append(slot->mbuf, padlen, 1835 sc->swsc->null_mbuf->m_data); 1836 m0 = m_defrag(slot->mbuf, M_NOWAIT); 1837 if (m0 == NULL) { 1838 device_printf(sc->dev, 1839 "Can't defragment packet; dropping\n"); 1840 m_freem(slot->mbuf); 1841 } else { 1842 CPSW_DEBUGF(sc->swsc, 1843 ("Requeueing defragmented packet")); 1844 IF_PREPEND(&sc->ifp->if_snd, m0); 1845 } 1846 slot->mbuf = NULL; 1847 continue; 1848 } 1849 if (error != 0) { 1850 device_printf(sc->dev, 1851 "%s: Can't setup DMA (error=%d), dropping packet\n", 1852 __func__, error); 1853 bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap); 1854 m_freem(slot->mbuf); 1855 slot->mbuf = NULL; 1856 break; 1857 } 1858 1859 bus_dmamap_sync(sc->swsc->mbuf_dtag, slot->dmamap, 1860 BUS_DMASYNC_PREWRITE); 1861 1862 CPSW_DEBUGF(sc->swsc, 1863 ("Queueing TX packet: %d segments + %d pad bytes", 1864 nsegs, padlen)); 1865 1866 if (first_new_slot == NULL) 1867 first_new_slot = slot; 1868 1869 /* Link from the previous descriptor. */ 1870 if (last != NULL) 1871 cpsw_cpdma_write_bd_next(sc->swsc, last, slot); 1872 1873 slot->ifp = sc->ifp; 1874 1875 /* If there is only one segment, the for() loop 1876 * gets skipped and the single buffer gets set up 1877 * as both SOP and EOP. */ 1878 if (nsegs > 1) { 1879 next = STAILQ_NEXT(slot, next); 1880 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1881 } else 1882 bd.next = 0; 1883 /* Start by setting up the first buffer. */ 1884 bd.bufptr = segs[0].ds_addr; 1885 bd.bufoff = 0; 1886 bd.buflen = segs[0].ds_len; 1887 bd.pktlen = m_length(slot->mbuf, NULL) + padlen; 1888 bd.flags = CPDMA_BD_SOP | CPDMA_BD_OWNER | flags; 1889 for (seg = 1; seg < nsegs; ++seg) { 1890 /* Save the previous buffer (which isn't EOP) */ 1891 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1892 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1893 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1894 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1895 1896 /* Setup next buffer (which isn't SOP) */ 1897 if (nsegs > seg + 1) { 1898 next = STAILQ_NEXT(slot, next); 1899 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1900 } else 1901 bd.next = 0; 1902 bd.bufptr = segs[seg].ds_addr; 1903 bd.bufoff = 0; 1904 bd.buflen = segs[seg].ds_len; 1905 bd.pktlen = 0; 1906 bd.flags = CPDMA_BD_OWNER | flags; 1907 } 1908 /* Save the final buffer. */ 1909 if (padlen <= 0) 1910 bd.flags |= CPDMA_BD_EOP; 1911 else { 1912 next = STAILQ_NEXT(slot, next); 1913 bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next); 1914 } 1915 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1916 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1917 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1918 1919 if (padlen > 0) { 1920 slot = STAILQ_FIRST(&sc->swsc->tx.avail); 1921 1922 /* Setup buffer of null pad bytes (definitely EOP). */ 1923 bd.next = 0; 1924 bd.bufptr = sc->swsc->null_mbuf_paddr; 1925 bd.bufoff = 0; 1926 bd.buflen = padlen; 1927 bd.pktlen = 0; 1928 bd.flags = CPDMA_BD_EOP | CPDMA_BD_OWNER | flags; 1929 cpsw_cpdma_write_bd(sc->swsc, slot, &bd); 1930 ++nsegs; 1931 1932 STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next); 1933 STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next); 1934 } 1935 1936 last = slot; 1937 1938 added += nsegs; 1939 if (nsegs > sc->swsc->tx.longest_chain) 1940 sc->swsc->tx.longest_chain = nsegs; 1941 1942 // TODO: Should we defer the BPF tap until 1943 // after all packets are queued? 1944 BPF_MTAP(sc->ifp, m0); 1945 } 1946 1947 if (first_new_slot == NULL) 1948 return; 1949 1950 /* Attach the list of new buffers to the hardware TX queue. */ 1951 if (last_old_slot != NULL && 1952 (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) & 1953 CPDMA_BD_EOQ) == 0) { 1954 /* Add buffers to end of current queue. */ 1955 cpsw_cpdma_write_bd_next(sc->swsc, last_old_slot, 1956 first_new_slot); 1957 } else { 1958 /* Start a fresh queue. */ 1959 cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot); 1960 } 1961 sc->swsc->tx.queue_adds += added; 1962 sc->swsc->tx.avail_queue_len -= added; 1963 sc->swsc->tx.active_queue_len += added; 1964 if (sc->swsc->tx.active_queue_len > sc->swsc->tx.max_active_queue_len) { 1965 sc->swsc->tx.max_active_queue_len = sc->swsc->tx.active_queue_len; 1966 } 1967 CPSW_DEBUGF(sc->swsc, ("Queued %d TX packet(s)", added)); 1968} 1969 1970static int 1971cpsw_tx_dequeue(struct cpsw_softc *sc) 1972{ 1973 struct cpsw_slot *slot, *last_removed_slot = NULL; 1974 struct cpsw_cpdma_bd bd; 1975 uint32_t flags, removed = 0; 1976 1977 /* Pull completed buffers off the hardware TX queue. */ 1978 slot = STAILQ_FIRST(&sc->tx.active); 1979 while (slot != NULL) { 1980 flags = cpsw_cpdma_read_bd_flags(sc, slot); 1981 1982 /* TearDown complete is only marked on the SOP for the packet. */ 1983 if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) == 1984 (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) { 1985 sc->tx.teardown = 1; 1986 } 1987 1988 if ((flags & CPDMA_BD_OWNER) != 0 && sc->tx.teardown == 0) 1989 break; /* Hardware is still using this packet. */ 1990 1991 bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTWRITE); 1992 bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap); 1993 m_freem(slot->mbuf); 1994 slot->mbuf = NULL; 1995 1996 if (slot->ifp) { 1997 if (sc->tx.teardown == 0) 1998 if_inc_counter(slot->ifp, IFCOUNTER_OPACKETS, 1); 1999 else 2000 if_inc_counter(slot->ifp, IFCOUNTER_OQDROPS, 1); 2001 } 2002 2003 /* Dequeue any additional buffers used by this packet. */ 2004 while (slot != NULL && slot->mbuf == NULL) { 2005 STAILQ_REMOVE_HEAD(&sc->tx.active, next); 2006 STAILQ_INSERT_TAIL(&sc->tx.avail, slot, next); 2007 ++removed; 2008 last_removed_slot = slot; 2009 slot = STAILQ_FIRST(&sc->tx.active); 2010 } 2011 2012 cpsw_write_cp_slot(sc, &sc->tx, last_removed_slot); 2013 2014 /* Restart the TX queue if necessary. */ 2015 cpsw_cpdma_read_bd(sc, last_removed_slot, &bd); 2016 if (slot != NULL && bd.next != 0 && (bd.flags & 2017 (CPDMA_BD_EOP | CPDMA_BD_OWNER | CPDMA_BD_EOQ)) == 2018 (CPDMA_BD_EOP | CPDMA_BD_EOQ)) { 2019 cpsw_write_hdp_slot(sc, &sc->tx, slot); 2020 sc->tx.queue_restart++; 2021 break; 2022 } 2023 } 2024 2025 if (removed != 0) { 2026 sc->tx.queue_removes += removed; 2027 sc->tx.active_queue_len -= removed; 2028 sc->tx.avail_queue_len += removed; 2029 if (sc->tx.avail_queue_len > sc->tx.max_avail_queue_len) 2030 sc->tx.max_avail_queue_len = sc->tx.avail_queue_len; 2031 CPSW_DEBUGF(sc, ("TX removed %d completed packet(s)", removed)); 2032 } 2033 2034 if (sc->tx.teardown && STAILQ_EMPTY(&sc->tx.active)) { 2035 CPSW_DEBUGF(sc, ("TX teardown is complete")); 2036 sc->tx.teardown = 0; 2037 sc->tx.running = 0; 2038 } 2039 2040 return (removed); 2041} 2042 2043/* 2044 * 2045 * Miscellaneous interrupts. 2046 * 2047 */ 2048 2049static void 2050cpsw_intr_rx_thresh(void *arg) 2051{ 2052 struct cpsw_softc *sc; 2053 struct ifnet *ifp; 2054 struct mbuf *received, *next; 2055 2056 sc = (struct cpsw_softc *)arg; 2057 CPSW_RX_LOCK(sc); 2058 received = cpsw_rx_dequeue(sc); 2059 cpsw_rx_enqueue(sc); 2060 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0); 2061 CPSW_RX_UNLOCK(sc); 2062 2063 while (received != NULL) { 2064 next = received->m_nextpkt; 2065 received->m_nextpkt = NULL; 2066 ifp = received->m_pkthdr.rcvif; 2067 (*ifp->if_input)(ifp, received); 2068 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2069 received = next; 2070 } 2071} 2072 2073static void 2074cpsw_intr_misc_host_error(struct cpsw_softc *sc) 2075{ 2076 uint32_t intstat; 2077 uint32_t dmastat; 2078 int txerr, rxerr, txchan, rxchan; 2079 2080 printf("\n\n"); 2081 device_printf(sc->dev, 2082 "HOST ERROR: PROGRAMMING ERROR DETECTED BY HARDWARE\n"); 2083 printf("\n\n"); 2084 intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED); 2085 device_printf(sc->dev, "CPSW_CPDMA_DMA_INTSTAT_MASKED=0x%x\n", intstat); 2086 dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS); 2087 device_printf(sc->dev, "CPSW_CPDMA_DMASTATUS=0x%x\n", dmastat); 2088 2089 txerr = (dmastat >> 20) & 15; 2090 txchan = (dmastat >> 16) & 7; 2091 rxerr = (dmastat >> 12) & 15; 2092 rxchan = (dmastat >> 8) & 7; 2093 2094 switch (txerr) { 2095 case 0: break; 2096 case 1: printf("SOP error on TX channel %d\n", txchan); 2097 break; 2098 case 2: printf("Ownership bit not set on SOP buffer on TX channel %d\n", txchan); 2099 break; 2100 case 3: printf("Zero Next Buffer but not EOP on TX channel %d\n", txchan); 2101 break; 2102 case 4: printf("Zero Buffer Pointer on TX channel %d\n", txchan); 2103 break; 2104 case 5: printf("Zero Buffer Length on TX channel %d\n", txchan); 2105 break; 2106 case 6: printf("Packet length error on TX channel %d\n", txchan); 2107 break; 2108 default: printf("Unknown error on TX channel %d\n", txchan); 2109 break; 2110 } 2111 2112 if (txerr != 0) { 2113 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 2114 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan))); 2115 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 2116 txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan))); 2117 cpsw_dump_queue(sc, &sc->tx.active); 2118 } 2119 2120 switch (rxerr) { 2121 case 0: break; 2122 case 2: printf("Ownership bit not set on RX channel %d\n", rxchan); 2123 break; 2124 case 4: printf("Zero Buffer Pointer on RX channel %d\n", rxchan); 2125 break; 2126 case 5: printf("Zero Buffer Length on RX channel %d\n", rxchan); 2127 break; 2128 case 6: printf("Buffer offset too big on RX channel %d\n", rxchan); 2129 break; 2130 default: printf("Unknown RX error on RX channel %d\n", rxchan); 2131 break; 2132 } 2133 2134 if (rxerr != 0) { 2135 printf("CPSW_CPDMA_RX%d_HDP=0x%x\n", 2136 rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan))); 2137 printf("CPSW_CPDMA_RX%d_CP=0x%x\n", 2138 rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan))); 2139 cpsw_dump_queue(sc, &sc->rx.active); 2140 } 2141 2142 printf("\nALE Table\n"); 2143 cpsw_ale_dump_table(sc); 2144 2145 // XXX do something useful here?? 2146 panic("CPSW HOST ERROR INTERRUPT"); 2147 2148 // Suppress this interrupt in the future. 2149 cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat); 2150 printf("XXX HOST ERROR INTERRUPT SUPPRESSED\n"); 2151 // The watchdog will probably reset the controller 2152 // in a little while. It will probably fail again. 2153} 2154 2155static void 2156cpsw_intr_misc(void *arg) 2157{ 2158 struct cpsw_softc *sc = arg; 2159 uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0)); 2160 2161 if (stat & CPSW_WR_C_MISC_EVNT_PEND) 2162 CPSW_DEBUGF(sc, ("Time sync event interrupt unimplemented")); 2163 if (stat & CPSW_WR_C_MISC_STAT_PEND) 2164 cpsw_stats_collect(sc); 2165 if (stat & CPSW_WR_C_MISC_HOST_PEND) 2166 cpsw_intr_misc_host_error(sc); 2167 if (stat & CPSW_WR_C_MISC_MDIOLINK) { 2168 cpsw_write_4(sc, MDIOLINKINTMASKED, 2169 cpsw_read_4(sc, MDIOLINKINTMASKED)); 2170 } 2171 if (stat & CPSW_WR_C_MISC_MDIOUSER) { 2172 CPSW_DEBUGF(sc, 2173 ("MDIO operation completed interrupt unimplemented")); 2174 } 2175 cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3); 2176} 2177 2178/* 2179 * 2180 * Periodic Checks and Watchdog. 2181 * 2182 */ 2183 2184static void 2185cpswp_tick(void *msc) 2186{ 2187 struct cpswp_softc *sc = msc; 2188 2189 /* Check for media type change */ 2190 mii_tick(sc->mii); 2191 if (sc->media_status != sc->mii->mii_media.ifm_media) { 2192 printf("%s: media type changed (ifm_media=%x)\n", __func__, 2193 sc->mii->mii_media.ifm_media); 2194 cpswp_ifmedia_upd(sc->ifp); 2195 } 2196 2197 /* Schedule another timeout one second from now */ 2198 callout_reset(&sc->mii_callout, hz, cpswp_tick, sc); 2199} 2200 2201static void 2202cpswp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2203{ 2204 struct cpswp_softc *sc; 2205 struct mii_data *mii; 2206 2207 sc = ifp->if_softc; 2208 CPSW_DEBUGF(sc->swsc, ("")); 2209 CPSW_PORT_LOCK(sc); 2210 2211 mii = sc->mii; 2212 mii_pollstat(mii); 2213 2214 ifmr->ifm_active = mii->mii_media_active; 2215 ifmr->ifm_status = mii->mii_media_status; 2216 CPSW_PORT_UNLOCK(sc); 2217} 2218 2219static int 2220cpswp_ifmedia_upd(struct ifnet *ifp) 2221{ 2222 struct cpswp_softc *sc; 2223 2224 sc = ifp->if_softc; 2225 CPSW_DEBUGF(sc->swsc, ("")); 2226 CPSW_PORT_LOCK(sc); 2227 mii_mediachg(sc->mii); 2228 sc->media_status = sc->mii->mii_media.ifm_media; 2229 CPSW_PORT_UNLOCK(sc); 2230 2231 return (0); 2232} 2233 2234static void 2235cpsw_tx_watchdog_full_reset(struct cpsw_softc *sc) 2236{ 2237 struct cpswp_softc *psc; 2238 int i; 2239 2240 cpsw_debugf_head("CPSW watchdog"); 2241 device_printf(sc->dev, "watchdog timeout\n"); 2242 printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 0, 2243 cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0))); 2244 printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 0, 2245 cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0))); 2246 cpsw_dump_queue(sc, &sc->tx.active); 2247 for (i = 0; i < CPSW_PORTS; i++) { 2248 if (!sc->dualemac && i != sc->active_slave) 2249 continue; 2250 psc = device_get_softc(sc->port[i].dev); 2251 CPSW_PORT_LOCK(psc); 2252 cpswp_stop_locked(psc); 2253 CPSW_PORT_UNLOCK(psc); 2254 } 2255} 2256 2257static void 2258cpsw_tx_watchdog(void *msc) 2259{ 2260 struct cpsw_softc *sc; 2261 2262 sc = msc; 2263 CPSW_TX_LOCK(sc); 2264 if (sc->tx.active_queue_len == 0 || !sc->tx.running) { 2265 sc->watchdog.timer = 0; /* Nothing to do. */ 2266 } else if (sc->tx.queue_removes > sc->tx.queue_removes_at_last_tick) { 2267 sc->watchdog.timer = 0; /* Stuff done while we weren't looking. */ 2268 } else if (cpsw_tx_dequeue(sc) > 0) { 2269 sc->watchdog.timer = 0; /* We just did something. */ 2270 } else { 2271 /* There was something to do but it didn't get done. */ 2272 ++sc->watchdog.timer; 2273 if (sc->watchdog.timer > 5) { 2274 sc->watchdog.timer = 0; 2275 ++sc->watchdog.resets; 2276 cpsw_tx_watchdog_full_reset(sc); 2277 } 2278 } 2279 sc->tx.queue_removes_at_last_tick = sc->tx.queue_removes; 2280 CPSW_TX_UNLOCK(sc); 2281 2282 /* Schedule another timeout one second from now */ 2283 callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc); 2284} 2285 2286/* 2287 * 2288 * ALE support routines. 2289 * 2290 */ 2291 2292static void 2293cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2294{ 2295 cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023); 2296 ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0); 2297 ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1); 2298 ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2); 2299} 2300 2301static void 2302cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry) 2303{ 2304 cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]); 2305 cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]); 2306 cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]); 2307 cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023)); 2308} 2309 2310static void 2311cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc) 2312{ 2313 int i; 2314 uint32_t ale_entry[3]; 2315 2316 /* First four entries are link address and broadcast. */ 2317 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2318 cpsw_ale_read_entry(sc, i, ale_entry); 2319 if ((ALE_TYPE(ale_entry) == ALE_TYPE_ADDR || 2320 ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) && 2321 ALE_MCAST(ale_entry) == 1) { /* MCast link addr */ 2322 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2323 cpsw_ale_write_entry(sc, i, ale_entry); 2324 } 2325 } 2326} 2327 2328static int 2329cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, int vlan, 2330 uint8_t *mac) 2331{ 2332 int free_index = -1, matching_index = -1, i; 2333 uint32_t ale_entry[3], ale_type; 2334 2335 /* Find a matching entry or a free entry. */ 2336 for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) { 2337 cpsw_ale_read_entry(sc, i, ale_entry); 2338 2339 /* Entry Type[61:60] is 0 for free entry */ 2340 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2341 free_index = i; 2342 2343 if ((((ale_entry[1] >> 8) & 0xFF) == mac[0]) && 2344 (((ale_entry[1] >> 0) & 0xFF) == mac[1]) && 2345 (((ale_entry[0] >>24) & 0xFF) == mac[2]) && 2346 (((ale_entry[0] >>16) & 0xFF) == mac[3]) && 2347 (((ale_entry[0] >> 8) & 0xFF) == mac[4]) && 2348 (((ale_entry[0] >> 0) & 0xFF) == mac[5])) { 2349 matching_index = i; 2350 break; 2351 } 2352 } 2353 2354 if (matching_index < 0) { 2355 if (free_index < 0) 2356 return (ENOMEM); 2357 i = free_index; 2358 } 2359 2360 if (vlan != -1) 2361 ale_type = ALE_TYPE_VLAN_ADDR << 28 | vlan << 16; 2362 else 2363 ale_type = ALE_TYPE_ADDR << 28; 2364 2365 /* Set MAC address */ 2366 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2367 ale_entry[1] = mac[0] << 8 | mac[1]; 2368 2369 /* Entry type[61:60] and Mcast fwd state[63:62] is fw(3). */ 2370 ale_entry[1] |= ALE_MCAST_FWD | ale_type; 2371 2372 /* Set portmask [68:66] */ 2373 ale_entry[2] = (portmap & 7) << 2; 2374 2375 cpsw_ale_write_entry(sc, i, ale_entry); 2376 2377 return 0; 2378} 2379 2380static void 2381cpsw_ale_dump_table(struct cpsw_softc *sc) { 2382 int i; 2383 uint32_t ale_entry[3]; 2384 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2385 cpsw_ale_read_entry(sc, i, ale_entry); 2386 switch (ALE_TYPE(ale_entry)) { 2387 case ALE_TYPE_VLAN: 2388 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2389 ale_entry[1], ale_entry[0]); 2390 printf("type: %u ", ALE_TYPE(ale_entry)); 2391 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2392 printf("untag: %u ", ALE_VLAN_UNTAG(ale_entry)); 2393 printf("reg flood: %u ", ALE_VLAN_REGFLOOD(ale_entry)); 2394 printf("unreg flood: %u ", ALE_VLAN_UNREGFLOOD(ale_entry)); 2395 printf("members: %u ", ALE_VLAN_MEMBERS(ale_entry)); 2396 printf("\n"); 2397 break; 2398 case ALE_TYPE_ADDR: 2399 case ALE_TYPE_VLAN_ADDR: 2400 printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2], 2401 ale_entry[1], ale_entry[0]); 2402 printf("type: %u ", ALE_TYPE(ale_entry)); 2403 printf("mac: %02x:%02x:%02x:%02x:%02x:%02x ", 2404 (ale_entry[1] >> 8) & 0xFF, 2405 (ale_entry[1] >> 0) & 0xFF, 2406 (ale_entry[0] >>24) & 0xFF, 2407 (ale_entry[0] >>16) & 0xFF, 2408 (ale_entry[0] >> 8) & 0xFF, 2409 (ale_entry[0] >> 0) & 0xFF); 2410 printf(ALE_MCAST(ale_entry) ? "mcast " : "ucast "); 2411 if (ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) 2412 printf("vlan: %u ", ALE_VLAN(ale_entry)); 2413 printf("port: %u ", ALE_PORTS(ale_entry)); 2414 printf("\n"); 2415 break; 2416 } 2417 } 2418 printf("\n"); 2419} 2420 2421static int 2422cpswp_ale_update_addresses(struct cpswp_softc *sc, int purge) 2423{ 2424 uint8_t *mac; 2425 uint32_t ale_entry[3], ale_type, portmask; 2426 struct ifmultiaddr *ifma; 2427 2428 if (sc->swsc->dualemac) { 2429 ale_type = ALE_TYPE_VLAN_ADDR << 28 | sc->vlan << 16; 2430 portmask = 1 << (sc->unit + 1) | 1 << 0; 2431 } else { 2432 ale_type = ALE_TYPE_ADDR << 28; 2433 portmask = 7; 2434 } 2435 2436 /* 2437 * Route incoming packets for our MAC address to Port 0 (host). 2438 * For simplicity, keep this entry at table index 0 for port 1 and 2439 * at index 2 for port 2 in the ALE. 2440 */ 2441 if_addr_rlock(sc->ifp); 2442 mac = LLADDR((struct sockaddr_dl *)sc->ifp->if_addr->ifa_addr); 2443 ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; 2444 ale_entry[1] = ale_type | mac[0] << 8 | mac[1]; /* addr entry + mac */ 2445 ale_entry[2] = 0; /* port = 0 */ 2446 cpsw_ale_write_entry(sc->swsc, 0 + 2 * sc->unit, ale_entry); 2447 2448 /* Set outgoing MAC Address for slave port. */ 2449 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1), 2450 mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]); 2451 cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1), 2452 mac[5] << 8 | mac[4]); 2453 if_addr_runlock(sc->ifp); 2454 2455 /* Keep the broadcast address at table entry 1 (or 3). */ 2456 ale_entry[0] = 0xffffffff; /* Lower 32 bits of MAC */ 2457 /* ALE_MCAST_FWD, Addr type, upper 16 bits of Mac */ 2458 ale_entry[1] = ALE_MCAST_FWD | ale_type | 0xffff; 2459 ale_entry[2] = portmask << 2; 2460 cpsw_ale_write_entry(sc->swsc, 1 + 2 * sc->unit, ale_entry); 2461 2462 /* SIOCDELMULTI doesn't specify the particular address 2463 being removed, so we have to remove all and rebuild. */ 2464 if (purge) 2465 cpsw_ale_remove_all_mc_entries(sc->swsc); 2466 2467 /* Set other multicast addrs desired. */ 2468 if_maddr_rlock(sc->ifp); 2469 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 2470 if (ifma->ifma_addr->sa_family != AF_LINK) 2471 continue; 2472 cpsw_ale_mc_entry_set(sc->swsc, portmask, sc->vlan, 2473 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 2474 } 2475 if_maddr_runlock(sc->ifp); 2476 2477 return (0); 2478} 2479 2480static int 2481cpsw_ale_update_vlan_table(struct cpsw_softc *sc, int vlan, int ports, 2482 int untag, int mcregflood, int mcunregflood) 2483{ 2484 int free_index, i, matching_index; 2485 uint32_t ale_entry[3]; 2486 2487 free_index = matching_index = -1; 2488 /* Find a matching entry or a free entry. */ 2489 for (i = 5; i < CPSW_MAX_ALE_ENTRIES; i++) { 2490 cpsw_ale_read_entry(sc, i, ale_entry); 2491 2492 /* Entry Type[61:60] is 0 for free entry */ 2493 if (free_index < 0 && ALE_TYPE(ale_entry) == 0) 2494 free_index = i; 2495 2496 if (ALE_VLAN(ale_entry) == vlan) { 2497 matching_index = i; 2498 break; 2499 } 2500 } 2501 2502 if (matching_index < 0) { 2503 if (free_index < 0) 2504 return (-1); 2505 i = free_index; 2506 } 2507 2508 ale_entry[0] = (untag & 7) << 24 | (mcregflood & 7) << 16 | 2509 (mcunregflood & 7) << 8 | (ports & 7); 2510 ale_entry[1] = ALE_TYPE_VLAN << 28 | vlan << 16; 2511 ale_entry[2] = 0; 2512 cpsw_ale_write_entry(sc, i, ale_entry); 2513 2514 return (0); 2515} 2516 2517/* 2518 * 2519 * Statistics and Sysctls. 2520 * 2521 */ 2522 2523#if 0 2524static void 2525cpsw_stats_dump(struct cpsw_softc *sc) 2526{ 2527 int i; 2528 uint32_t r; 2529 2530 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2531 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2532 cpsw_stat_sysctls[i].reg); 2533 CPSW_DEBUGF(sc, ("%s: %ju + %u = %ju", cpsw_stat_sysctls[i].oid, 2534 (intmax_t)sc->shadow_stats[i], r, 2535 (intmax_t)sc->shadow_stats[i] + r)); 2536 } 2537} 2538#endif 2539 2540static void 2541cpsw_stats_collect(struct cpsw_softc *sc) 2542{ 2543 int i; 2544 uint32_t r; 2545 2546 CPSW_DEBUGF(sc, ("Controller shadow statistics updated.")); 2547 2548 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2549 r = cpsw_read_4(sc, CPSW_STATS_OFFSET + 2550 cpsw_stat_sysctls[i].reg); 2551 sc->shadow_stats[i] += r; 2552 cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg, 2553 r); 2554 } 2555} 2556 2557static int 2558cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS) 2559{ 2560 struct cpsw_softc *sc; 2561 struct cpsw_stat *stat; 2562 uint64_t result; 2563 2564 sc = (struct cpsw_softc *)arg1; 2565 stat = &cpsw_stat_sysctls[oidp->oid_number]; 2566 result = sc->shadow_stats[oidp->oid_number]; 2567 result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg); 2568 return (sysctl_handle_64(oidp, &result, 0, req)); 2569} 2570 2571static int 2572cpsw_stat_attached(SYSCTL_HANDLER_ARGS) 2573{ 2574 struct cpsw_softc *sc; 2575 struct bintime t; 2576 unsigned result; 2577 2578 sc = (struct cpsw_softc *)arg1; 2579 getbinuptime(&t); 2580 bintime_sub(&t, &sc->attach_uptime); 2581 result = t.sec; 2582 return (sysctl_handle_int(oidp, &result, 0, req)); 2583} 2584 2585static int 2586cpsw_intr_coalesce(SYSCTL_HANDLER_ARGS) 2587{ 2588 int error; 2589 struct cpsw_softc *sc; 2590 uint32_t ctrl, intr_per_ms; 2591 2592 sc = (struct cpsw_softc *)arg1; 2593 error = sysctl_handle_int(oidp, &sc->coal_us, 0, req); 2594 if (error != 0 || req->newptr == NULL) 2595 return (error); 2596 2597 ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL); 2598 ctrl &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK); 2599 if (sc->coal_us == 0) { 2600 /* Disable the interrupt pace hardware. */ 2601 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2602 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0); 2603 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0); 2604 return (0); 2605 } 2606 2607 if (sc->coal_us > CPSW_WR_C_IMAX_US_MAX) 2608 sc->coal_us = CPSW_WR_C_IMAX_US_MAX; 2609 if (sc->coal_us < CPSW_WR_C_IMAX_US_MIN) 2610 sc->coal_us = CPSW_WR_C_IMAX_US_MIN; 2611 intr_per_ms = 1000 / sc->coal_us; 2612 /* Just to make sure... */ 2613 if (intr_per_ms > CPSW_WR_C_IMAX_MAX) 2614 intr_per_ms = CPSW_WR_C_IMAX_MAX; 2615 if (intr_per_ms < CPSW_WR_C_IMAX_MIN) 2616 intr_per_ms = CPSW_WR_C_IMAX_MIN; 2617 2618 /* Set the prescale to produce 4us pulses from the 125 Mhz clock. */ 2619 ctrl |= (125 * 4) & CPSW_WR_INT_PRESCALE_MASK; 2620 2621 /* Enable the interrupt pace hardware. */ 2622 cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms); 2623 cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms); 2624 ctrl |= CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE; 2625 cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl); 2626 2627 return (0); 2628} 2629 2630static int 2631cpsw_stat_uptime(SYSCTL_HANDLER_ARGS) 2632{ 2633 struct cpsw_softc *swsc; 2634 struct cpswp_softc *sc; 2635 struct bintime t; 2636 unsigned result; 2637 2638 swsc = arg1; 2639 sc = device_get_softc(swsc->port[arg2].dev); 2640 if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) { 2641 getbinuptime(&t); 2642 bintime_sub(&t, &sc->init_uptime); 2643 result = t.sec; 2644 } else 2645 result = 0; 2646 return (sysctl_handle_int(oidp, &result, 0, req)); 2647} 2648 2649static void 2650cpsw_add_queue_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2651 struct cpsw_queue *queue) 2652{ 2653 struct sysctl_oid_list *parent; 2654 2655 parent = SYSCTL_CHILDREN(node); 2656 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "totalBuffers", 2657 CTLFLAG_RD, &queue->queue_slots, 0, 2658 "Total buffers currently assigned to this queue"); 2659 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "activeBuffers", 2660 CTLFLAG_RD, &queue->active_queue_len, 0, 2661 "Buffers currently registered with hardware controller"); 2662 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxActiveBuffers", 2663 CTLFLAG_RD, &queue->max_active_queue_len, 0, 2664 "Max value of activeBuffers since last driver reset"); 2665 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "availBuffers", 2666 CTLFLAG_RD, &queue->avail_queue_len, 0, 2667 "Buffers allocated to this queue but not currently " 2668 "registered with hardware controller"); 2669 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxAvailBuffers", 2670 CTLFLAG_RD, &queue->max_avail_queue_len, 0, 2671 "Max value of availBuffers since last driver reset"); 2672 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalEnqueued", 2673 CTLFLAG_RD, &queue->queue_adds, 0, 2674 "Total buffers added to queue"); 2675 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalDequeued", 2676 CTLFLAG_RD, &queue->queue_removes, 0, 2677 "Total buffers removed from queue"); 2678 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "queueRestart", 2679 CTLFLAG_RD, &queue->queue_restart, 0, 2680 "Total times the queue has been restarted"); 2681 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "longestChain", 2682 CTLFLAG_RD, &queue->longest_chain, 0, 2683 "Max buffers used for a single packet"); 2684} 2685 2686static void 2687cpsw_add_watchdog_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node, 2688 struct cpsw_softc *sc) 2689{ 2690 struct sysctl_oid_list *parent; 2691 2692 parent = SYSCTL_CHILDREN(node); 2693 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "resets", 2694 CTLFLAG_RD, &sc->watchdog.resets, 0, 2695 "Total number of watchdog resets"); 2696} 2697 2698static void 2699cpsw_add_sysctls(struct cpsw_softc *sc) 2700{ 2701 struct sysctl_ctx_list *ctx; 2702 struct sysctl_oid *stats_node, *queue_node, *node; 2703 struct sysctl_oid_list *parent, *stats_parent, *queue_parent; 2704 struct sysctl_oid_list *ports_parent, *port_parent; 2705 char port[16]; 2706 int i; 2707 2708 ctx = device_get_sysctl_ctx(sc->dev); 2709 parent = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2710 2711 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "debug", 2712 CTLFLAG_RW, &sc->debug, 0, "Enable switch debug messages"); 2713 2714 SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "rx_batch", 2715 CTLFLAG_RW, &sc->rx_batch, 0, "Set the rx batch size"); 2716 2717 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "attachedSecs", 2718 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, cpsw_stat_attached, "IU", 2719 "Time since driver attach"); 2720 2721 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "intr_coalesce_us", 2722 CTLTYPE_UINT | CTLFLAG_RW, sc, 0, cpsw_intr_coalesce, "IU", 2723 "minimum time between interrupts"); 2724 2725 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "ports", 2726 CTLFLAG_RD, NULL, "CPSW Ports Statistics"); 2727 ports_parent = SYSCTL_CHILDREN(node); 2728 for (i = 0; i < CPSW_PORTS; i++) { 2729 if (!sc->dualemac && i != sc->active_slave) 2730 continue; 2731 port[0] = '0' + i; 2732 port[1] = '\0'; 2733 node = SYSCTL_ADD_NODE(ctx, ports_parent, OID_AUTO, 2734 port, CTLFLAG_RD, NULL, "CPSW Port Statistics"); 2735 port_parent = SYSCTL_CHILDREN(node); 2736 SYSCTL_ADD_PROC(ctx, port_parent, OID_AUTO, "uptime", 2737 CTLTYPE_UINT | CTLFLAG_RD, sc, i, 2738 cpsw_stat_uptime, "IU", "Seconds since driver init"); 2739 } 2740 2741 stats_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", 2742 CTLFLAG_RD, NULL, "CPSW Statistics"); 2743 stats_parent = SYSCTL_CHILDREN(stats_node); 2744 for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) { 2745 SYSCTL_ADD_PROC(ctx, stats_parent, i, 2746 cpsw_stat_sysctls[i].oid, 2747 CTLTYPE_U64 | CTLFLAG_RD, sc, 0, 2748 cpsw_stats_sysctl, "IU", 2749 cpsw_stat_sysctls[i].oid); 2750 } 2751 2752 queue_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "queue", 2753 CTLFLAG_RD, NULL, "CPSW Queue Statistics"); 2754 queue_parent = SYSCTL_CHILDREN(queue_node); 2755 2756 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "tx", 2757 CTLFLAG_RD, NULL, "TX Queue Statistics"); 2758 cpsw_add_queue_sysctls(ctx, node, &sc->tx); 2759 2760 node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "rx", 2761 CTLFLAG_RD, NULL, "RX Queue Statistics"); 2762 cpsw_add_queue_sysctls(ctx, node, &sc->rx); 2763 2764 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "watchdog", 2765 CTLFLAG_RD, NULL, "Watchdog Statistics"); 2766 cpsw_add_watchdog_sysctls(ctx, node, sc); 2767} 2768 2769#ifdef CPSW_ETHERSWITCH 2770static etherswitch_info_t etherswitch_info = { 2771 .es_nports = CPSW_PORTS + 1, 2772 .es_nvlangroups = CPSW_VLANS, 2773 .es_name = "TI Common Platform Ethernet Switch (CPSW)", 2774 .es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q, 2775}; 2776 2777static etherswitch_info_t * 2778cpsw_getinfo(device_t dev) 2779{ 2780 return (ðerswitch_info); 2781} 2782 2783static int 2784cpsw_getport(device_t dev, etherswitch_port_t *p) 2785{ 2786 int err; 2787 struct cpsw_softc *sc; 2788 struct cpswp_softc *psc; 2789 struct ifmediareq *ifmr; 2790 uint32_t reg; 2791 2792 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2793 return (ENXIO); 2794 2795 err = 0; 2796 sc = device_get_softc(dev); 2797 if (p->es_port == CPSW_CPU_PORT) { 2798 p->es_flags |= ETHERSWITCH_PORT_CPU; 2799 ifmr = &p->es_ifmr; 2800 ifmr->ifm_current = ifmr->ifm_active = 2801 IFM_ETHER | IFM_1000_T | IFM_FDX; 2802 ifmr->ifm_mask = 0; 2803 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID; 2804 ifmr->ifm_count = 0; 2805 } else { 2806 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2807 err = ifmedia_ioctl(psc->ifp, &p->es_ifr, 2808 &psc->mii->mii_media, SIOCGIFMEDIA); 2809 } 2810 reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port)); 2811 p->es_pvid = reg & ETHERSWITCH_VID_MASK; 2812 2813 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2814 if (reg & ALE_PORTCTL_DROP_UNTAGGED) 2815 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED; 2816 if (reg & ALE_PORTCTL_INGRESS) 2817 p->es_flags |= ETHERSWITCH_PORT_INGRESS; 2818 2819 return (err); 2820} 2821 2822static int 2823cpsw_setport(device_t dev, etherswitch_port_t *p) 2824{ 2825 struct cpsw_softc *sc; 2826 struct cpswp_softc *psc; 2827 struct ifmedia *ifm; 2828 uint32_t reg; 2829 2830 if (p->es_port < 0 || p->es_port > CPSW_PORTS) 2831 return (ENXIO); 2832 2833 sc = device_get_softc(dev); 2834 if (p->es_pvid != 0) { 2835 cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port), 2836 p->es_pvid & ETHERSWITCH_VID_MASK); 2837 } 2838 2839 reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port)); 2840 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED) 2841 reg |= ALE_PORTCTL_DROP_UNTAGGED; 2842 else 2843 reg &= ~ALE_PORTCTL_DROP_UNTAGGED; 2844 if (p->es_flags & ETHERSWITCH_PORT_INGRESS) 2845 reg |= ALE_PORTCTL_INGRESS; 2846 else 2847 reg &= ~ALE_PORTCTL_INGRESS; 2848 cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg); 2849 2850 /* CPU port does not allow media settings. */ 2851 if (p->es_port == CPSW_CPU_PORT) 2852 return (0); 2853 2854 psc = device_get_softc(sc->port[p->es_port - 1].dev); 2855 ifm = &psc->mii->mii_media; 2856 2857 return (ifmedia_ioctl(psc->ifp, &p->es_ifr, ifm, SIOCSIFMEDIA)); 2858} 2859 2860static int 2861cpsw_getconf(device_t dev, etherswitch_conf_t *conf) 2862{ 2863 2864 /* Return the VLAN mode. */ 2865 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE; 2866 conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q; 2867 2868 return (0); 2869} 2870 2871static int 2872cpsw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2873{ 2874 int i, vid; 2875 uint32_t ale_entry[3]; 2876 struct cpsw_softc *sc; 2877 2878 sc = device_get_softc(dev); 2879 2880 if (vg->es_vlangroup >= CPSW_VLANS) 2881 return (EINVAL); 2882 2883 vg->es_vid = 0; 2884 vid = cpsw_vgroups[vg->es_vlangroup].vid; 2885 if (vid == -1) 2886 return (0); 2887 2888 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2889 cpsw_ale_read_entry(sc, i, ale_entry); 2890 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2891 continue; 2892 if (vid != ALE_VLAN(ale_entry)) 2893 continue; 2894 2895 vg->es_fid = 0; 2896 vg->es_vid = ALE_VLAN(ale_entry) | ETHERSWITCH_VID_VALID; 2897 vg->es_member_ports = ALE_VLAN_MEMBERS(ale_entry); 2898 vg->es_untagged_ports = ALE_VLAN_UNTAG(ale_entry); 2899 } 2900 2901 return (0); 2902} 2903 2904static void 2905cpsw_remove_vlan(struct cpsw_softc *sc, int vlan) 2906{ 2907 int i; 2908 uint32_t ale_entry[3]; 2909 2910 for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) { 2911 cpsw_ale_read_entry(sc, i, ale_entry); 2912 if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN) 2913 continue; 2914 if (vlan != ALE_VLAN(ale_entry)) 2915 continue; 2916 ale_entry[0] = ale_entry[1] = ale_entry[2] = 0; 2917 cpsw_ale_write_entry(sc, i, ale_entry); 2918 break; 2919 } 2920} 2921 2922static int 2923cpsw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg) 2924{ 2925 int i; 2926 struct cpsw_softc *sc; 2927 2928 sc = device_get_softc(dev); 2929 2930 for (i = 0; i < CPSW_VLANS; i++) { 2931 /* Is this Vlan ID in use by another vlangroup ? */ 2932 if (vg->es_vlangroup != i && cpsw_vgroups[i].vid == vg->es_vid) 2933 return (EINVAL); 2934 } 2935 2936 if (vg->es_vid == 0) { 2937 if (cpsw_vgroups[vg->es_vlangroup].vid == -1) 2938 return (0); 2939 cpsw_remove_vlan(sc, cpsw_vgroups[vg->es_vlangroup].vid); 2940 cpsw_vgroups[vg->es_vlangroup].vid = -1; 2941 vg->es_untagged_ports = 0; 2942 vg->es_member_ports = 0; 2943 vg->es_vid = 0; 2944 return (0); 2945 } 2946 2947 vg->es_vid &= ETHERSWITCH_VID_MASK; 2948 vg->es_member_ports &= CPSW_PORTS_MASK; 2949 vg->es_untagged_ports &= CPSW_PORTS_MASK; 2950 2951 if (cpsw_vgroups[vg->es_vlangroup].vid != -1 && 2952 cpsw_vgroups[vg->es_vlangroup].vid != vg->es_vid) 2953 return (EINVAL); 2954 2955 cpsw_vgroups[vg->es_vlangroup].vid = vg->es_vid; 2956 cpsw_ale_update_vlan_table(sc, vg->es_vid, vg->es_member_ports, 2957 vg->es_untagged_ports, vg->es_member_ports, 0); 2958 2959 return (0); 2960} 2961 2962static int 2963cpsw_readreg(device_t dev, int addr) 2964{ 2965 2966 /* Not supported. */ 2967 return (0); 2968} 2969 2970static int 2971cpsw_writereg(device_t dev, int addr, int value) 2972{ 2973 2974 /* Not supported. */ 2975 return (0); 2976} 2977 2978static int 2979cpsw_readphy(device_t dev, int phy, int reg) 2980{ 2981 2982 /* Not supported. */ 2983 return (0); 2984} 2985 2986static int 2987cpsw_writephy(device_t dev, int phy, int reg, int data) 2988{ 2989 2990 /* Not supported. */ 2991 return (0); 2992} 2993#endif 2994