am335x_prcm.c revision 284532
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/ti/am335x/am335x_prcm.c 284532 2015-06-17 23:26:00Z gonzo $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/malloc.h> 36#include <sys/rman.h> 37#include <sys/timeet.h> 38#include <sys/timetc.h> 39#include <sys/watchdog.h> 40#include <machine/bus.h> 41#include <machine/cpu.h> 42#include <machine/intr.h> 43 44#include <arm/ti/tivar.h> 45#include <arm/ti/ti_scm.h> 46#include <arm/ti/ti_prcm.h> 47 48#include <dev/fdt/fdt_common.h> 49#include <dev/ofw/openfirm.h> 50#include <dev/ofw/ofw_bus.h> 51#include <dev/ofw/ofw_bus_subr.h> 52 53#include <machine/bus.h> 54 55#define CM_PER 0 56#define CM_PER_L4LS_CLKSTCTRL (CM_PER + 0x000) 57#define CM_PER_L3S_CLKSTCTRL (CM_PER + 0x004) 58#define CM_PER_L3_CLKSTCTRL (CM_PER + 0x00C) 59#define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x014) 60#define CM_PER_LCDC_CLKCTRL (CM_PER + 0x018) 61#define CM_PER_USB0_CLKCTRL (CM_PER + 0x01C) 62#define CM_PER_TPTC0_CLKCTRL (CM_PER + 0x024) 63#define CM_PER_UART5_CLKCTRL (CM_PER + 0x038) 64#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x03C) 65#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x044) 66#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x048) 67#define CM_PER_UART1_CLKCTRL (CM_PER + 0x06C) 68#define CM_PER_UART2_CLKCTRL (CM_PER + 0x070) 69#define CM_PER_UART3_CLKCTRL (CM_PER + 0x074) 70#define CM_PER_UART4_CLKCTRL (CM_PER + 0x078) 71#define CM_PER_TIMER7_CLKCTRL (CM_PER + 0x07C) 72#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x080) 73#define CM_PER_TIMER3_CLKCTRL (CM_PER + 0x084) 74#define CM_PER_TIMER4_CLKCTRL (CM_PER + 0x088) 75#define CM_PER_GPIO1_CLKCTRL (CM_PER + 0x0AC) 76#define CM_PER_GPIO2_CLKCTRL (CM_PER + 0x0B0) 77#define CM_PER_GPIO3_CLKCTRL (CM_PER + 0x0B4) 78#define CM_PER_TPCC_CLKCTRL (CM_PER + 0x0BC) 79#define CM_PER_EPWMSS1_CLKCTRL (CM_PER + 0x0CC) 80#define CM_PER_EPWMSS0_CLKCTRL (CM_PER + 0x0D4) 81#define CM_PER_EPWMSS2_CLKCTRL (CM_PER + 0x0D8) 82#define CM_PER_L3_INSTR_CLKCTRL (CM_PER + 0x0DC) 83#define CM_PER_L3_CLKCTRL (CM_PER + 0x0E0) 84#define CM_PER_PRUSS_CLKCTRL (CM_PER + 0x0E8) 85#define CM_PER_TIMER5_CLKCTRL (CM_PER + 0x0EC) 86#define CM_PER_TIMER6_CLKCTRL (CM_PER + 0x0F0) 87#define CM_PER_MMC1_CLKCTRL (CM_PER + 0x0F4) 88#define CM_PER_MMC2_CLKCTRL (CM_PER + 0x0F8) 89#define CM_PER_TPTC1_CLKCTRL (CM_PER + 0x0FC) 90#define CM_PER_TPTC2_CLKCTRL (CM_PER + 0x100) 91#define CM_PER_SPINLOCK0_CLKCTRL (CM_PER + 0x10C) 92#define CM_PER_MAILBOX0_CLKCTRL (CM_PER + 0x110) 93#define CM_PER_OCPWP_L3_CLKSTCTRL (CM_PER + 0x12C) 94#define CM_PER_OCPWP_CLKCTRL (CM_PER + 0x130) 95#define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144) 96#define CM_PER_PRUSS_CLKSTCTRL (CM_PER + 0x140) 97 98#define CM_WKUP 0x400 99#define CM_WKUP_CLKSTCTRL (CM_WKUP + 0x000) 100#define CM_WKUP_CONTROL_CLKCTRL (CM_WKUP + 0x004) 101#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x008) 102#define CM_WKUP_CM_L3_AON_CLKSTCTRL (CM_WKUP + 0x01C) 103#define CM_WKUP_CM_CLKSEL_DPLL_MPU (CM_WKUP + 0x02C) 104#define CM_WKUP_CM_IDLEST_DPLL_DISP (CM_WKUP + 0x048) 105#define CM_WKUP_CM_CLKSEL_DPLL_DISP (CM_WKUP + 0x054) 106#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER (CM_WKUP + 0x07C) 107#define CM_WKUP_CM_CLKMODE_DPLL_DISP (CM_WKUP + 0x098) 108#define CM_WKUP_I2C0_CLKCTRL (CM_WKUP + 0x0B8) 109#define CM_WKUP_ADC_TSC_CLKCTRL (CM_WKUP + 0x0BC) 110 111#define CM_DPLL 0x500 112#define CLKSEL_TIMER7_CLK (CM_DPLL + 0x004) 113#define CLKSEL_TIMER2_CLK (CM_DPLL + 0x008) 114#define CLKSEL_TIMER3_CLK (CM_DPLL + 0x00C) 115#define CLKSEL_TIMER4_CLK (CM_DPLL + 0x010) 116#define CLKSEL_TIMER5_CLK (CM_DPLL + 0x018) 117#define CLKSEL_TIMER6_CLK (CM_DPLL + 0x01C) 118#define CLKSEL_PRUSS_OCP_CLK (CM_DPLL + 0x030) 119 120#define CM_RTC 0x800 121#define CM_RTC_RTC_CLKCTRL (CM_RTC + 0x000) 122#define CM_RTC_CLKSTCTRL (CM_RTC + 0x004) 123 124#define PRM_PER 0xC00 125#define PRM_PER_RSTCTRL (PRM_PER + 0x00) 126 127#define PRM_DEVICE_OFFSET 0xF00 128#define PRM_RSTCTRL (PRM_DEVICE_OFFSET + 0x00) 129 130struct am335x_prcm_softc { 131 struct resource * res[2]; 132 bus_space_tag_t bst; 133 bus_space_handle_t bsh; 134}; 135 136static struct resource_spec am335x_prcm_spec[] = { 137 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 138 { -1, 0 } 139}; 140 141static struct am335x_prcm_softc *am335x_prcm_sc = NULL; 142 143static int am335x_clk_noop_activate(struct ti_clock_dev *clkdev); 144static int am335x_clk_generic_activate(struct ti_clock_dev *clkdev); 145static int am335x_clk_gpio_activate(struct ti_clock_dev *clkdev); 146static int am335x_clk_noop_deactivate(struct ti_clock_dev *clkdev); 147static int am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev); 148static int am335x_clk_noop_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 149static int am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 150static int am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 151static int am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 152static int am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 153static int am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 154static int am335x_clk_set_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int freq); 155static void am335x_prcm_reset(void); 156static int am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev); 157static int am335x_clk_musb0_activate(struct ti_clock_dev *clkdev); 158static int am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev); 159static int am335x_clk_pruss_activate(struct ti_clock_dev *clkdev); 160 161#define AM335X_NOOP_CLOCK_DEV(i) \ 162 { .id = (i), \ 163 .clk_activate = am335x_clk_noop_activate, \ 164 .clk_deactivate = am335x_clk_noop_deactivate, \ 165 .clk_set_source = am335x_clk_noop_set_source, \ 166 .clk_accessible = NULL, \ 167 .clk_get_source_freq = NULL, \ 168 .clk_set_source_freq = NULL \ 169 } 170 171#define AM335X_GENERIC_CLOCK_DEV(i) \ 172 { .id = (i), \ 173 .clk_activate = am335x_clk_generic_activate, \ 174 .clk_deactivate = am335x_clk_generic_deactivate, \ 175 .clk_set_source = am335x_clk_generic_set_source, \ 176 .clk_accessible = NULL, \ 177 .clk_get_source_freq = NULL, \ 178 .clk_set_source_freq = NULL \ 179 } 180 181#define AM335X_GPIO_CLOCK_DEV(i) \ 182 { .id = (i), \ 183 .clk_activate = am335x_clk_gpio_activate, \ 184 .clk_deactivate = am335x_clk_generic_deactivate, \ 185 .clk_set_source = am335x_clk_generic_set_source, \ 186 .clk_accessible = NULL, \ 187 .clk_get_source_freq = NULL, \ 188 .clk_set_source_freq = NULL \ 189 } 190 191#define AM335X_MMCHS_CLOCK_DEV(i) \ 192 { .id = (i), \ 193 .clk_activate = am335x_clk_generic_activate, \ 194 .clk_deactivate = am335x_clk_generic_deactivate, \ 195 .clk_set_source = am335x_clk_generic_set_source, \ 196 .clk_accessible = NULL, \ 197 .clk_get_source_freq = am335x_clk_hsmmc_get_source_freq, \ 198 .clk_set_source_freq = NULL \ 199 } 200 201struct ti_clock_dev ti_am335x_clk_devmap[] = { 202 /* System clocks */ 203 { .id = SYS_CLK, 204 .clk_activate = NULL, 205 .clk_deactivate = NULL, 206 .clk_set_source = NULL, 207 .clk_accessible = NULL, 208 .clk_get_source_freq = am335x_clk_get_sysclk_freq, 209 .clk_set_source_freq = NULL, 210 }, 211 /* MPU (ARM) core clocks */ 212 { .id = MPU_CLK, 213 .clk_activate = NULL, 214 .clk_deactivate = NULL, 215 .clk_set_source = NULL, 216 .clk_accessible = NULL, 217 .clk_get_source_freq = am335x_clk_get_arm_fclk_freq, 218 .clk_set_source_freq = NULL, 219 }, 220 /* CPSW Ethernet Switch core clocks */ 221 { .id = CPSW_CLK, 222 .clk_activate = am335x_clk_cpsw_activate, 223 .clk_deactivate = NULL, 224 .clk_set_source = NULL, 225 .clk_accessible = NULL, 226 .clk_get_source_freq = NULL, 227 .clk_set_source_freq = NULL, 228 }, 229 230 /* Mentor USB HS controller core clocks */ 231 { .id = MUSB0_CLK, 232 .clk_activate = am335x_clk_musb0_activate, 233 .clk_deactivate = NULL, 234 .clk_set_source = NULL, 235 .clk_accessible = NULL, 236 .clk_get_source_freq = NULL, 237 .clk_set_source_freq = NULL, 238 }, 239 240 /* LCD controller clocks */ 241 { .id = LCDC_CLK, 242 .clk_activate = am335x_clk_lcdc_activate, 243 .clk_deactivate = NULL, 244 .clk_set_source = NULL, 245 .clk_accessible = NULL, 246 .clk_get_source_freq = am335x_clk_get_arm_disp_freq, 247 .clk_set_source_freq = am335x_clk_set_arm_disp_freq, 248 }, 249 250 /* UART */ 251 AM335X_NOOP_CLOCK_DEV(UART1_CLK), 252 AM335X_GENERIC_CLOCK_DEV(UART2_CLK), 253 AM335X_GENERIC_CLOCK_DEV(UART3_CLK), 254 AM335X_GENERIC_CLOCK_DEV(UART4_CLK), 255 AM335X_GENERIC_CLOCK_DEV(UART5_CLK), 256 AM335X_GENERIC_CLOCK_DEV(UART6_CLK), 257 258 /* DMTimer */ 259 AM335X_GENERIC_CLOCK_DEV(TIMER2_CLK), 260 AM335X_GENERIC_CLOCK_DEV(TIMER3_CLK), 261 AM335X_GENERIC_CLOCK_DEV(TIMER4_CLK), 262 AM335X_GENERIC_CLOCK_DEV(TIMER5_CLK), 263 AM335X_GENERIC_CLOCK_DEV(TIMER6_CLK), 264 AM335X_GENERIC_CLOCK_DEV(TIMER7_CLK), 265 266 /* GPIO, we use hwmods as reference, not units in spec */ 267 AM335X_GPIO_CLOCK_DEV(GPIO1_CLK), 268 AM335X_GPIO_CLOCK_DEV(GPIO2_CLK), 269 AM335X_GPIO_CLOCK_DEV(GPIO3_CLK), 270 AM335X_GPIO_CLOCK_DEV(GPIO4_CLK), 271 272 /* I2C we use hwmods as reference, not units in spec */ 273 AM335X_GENERIC_CLOCK_DEV(I2C1_CLK), 274 AM335X_GENERIC_CLOCK_DEV(I2C2_CLK), 275 AM335X_GENERIC_CLOCK_DEV(I2C3_CLK), 276 277 /* TSC_ADC */ 278 AM335X_GENERIC_CLOCK_DEV(TSC_ADC_CLK), 279 280 /* EDMA */ 281 AM335X_GENERIC_CLOCK_DEV(EDMA_TPCC_CLK), 282 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC0_CLK), 283 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC1_CLK), 284 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC2_CLK), 285 286 /* MMCHS */ 287 AM335X_MMCHS_CLOCK_DEV(MMC1_CLK), 288 AM335X_MMCHS_CLOCK_DEV(MMC2_CLK), 289 AM335X_MMCHS_CLOCK_DEV(MMC3_CLK), 290 291 /* PWMSS */ 292 AM335X_GENERIC_CLOCK_DEV(PWMSS0_CLK), 293 AM335X_GENERIC_CLOCK_DEV(PWMSS1_CLK), 294 AM335X_GENERIC_CLOCK_DEV(PWMSS2_CLK), 295 296 /* System Mailbox clock */ 297 AM335X_GENERIC_CLOCK_DEV(MAILBOX0_CLK), 298 299 /* SPINLOCK */ 300 AM335X_GENERIC_CLOCK_DEV(SPINLOCK0_CLK), 301 302 /* PRU-ICSS */ 303 { .id = PRUSS_CLK, 304 .clk_activate = am335x_clk_pruss_activate, 305 .clk_deactivate = NULL, 306 .clk_set_source = NULL, 307 .clk_accessible = NULL, 308 .clk_get_source_freq = NULL, 309 .clk_set_source_freq = NULL, 310 }, 311 312 /* RTC */ 313 AM335X_GENERIC_CLOCK_DEV(RTC_CLK), 314 315 { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } 316}; 317 318struct am335x_clk_details { 319 clk_ident_t id; 320 uint32_t clkctrl_reg; 321 uint32_t clksel_reg; 322}; 323 324#define _CLK_DETAIL(i, c, s) \ 325 { .id = (i), \ 326 .clkctrl_reg = (c), \ 327 .clksel_reg = (s), \ 328 } 329 330static struct am335x_clk_details g_am335x_clk_details[] = { 331 332 /* UART. UART0 clock not controllable. */ 333 _CLK_DETAIL(UART1_CLK, 0, 0), 334 _CLK_DETAIL(UART2_CLK, CM_PER_UART1_CLKCTRL, 0), 335 _CLK_DETAIL(UART3_CLK, CM_PER_UART2_CLKCTRL, 0), 336 _CLK_DETAIL(UART4_CLK, CM_PER_UART3_CLKCTRL, 0), 337 _CLK_DETAIL(UART5_CLK, CM_PER_UART4_CLKCTRL, 0), 338 _CLK_DETAIL(UART6_CLK, CM_PER_UART5_CLKCTRL, 0), 339 340 /* DMTimer modules */ 341 _CLK_DETAIL(TIMER2_CLK, CM_PER_TIMER2_CLKCTRL, CLKSEL_TIMER2_CLK), 342 _CLK_DETAIL(TIMER3_CLK, CM_PER_TIMER3_CLKCTRL, CLKSEL_TIMER3_CLK), 343 _CLK_DETAIL(TIMER4_CLK, CM_PER_TIMER4_CLKCTRL, CLKSEL_TIMER4_CLK), 344 _CLK_DETAIL(TIMER5_CLK, CM_PER_TIMER5_CLKCTRL, CLKSEL_TIMER5_CLK), 345 _CLK_DETAIL(TIMER6_CLK, CM_PER_TIMER6_CLKCTRL, CLKSEL_TIMER6_CLK), 346 _CLK_DETAIL(TIMER7_CLK, CM_PER_TIMER7_CLKCTRL, CLKSEL_TIMER7_CLK), 347 348 /* GPIO modules, hwmods start with gpio1 */ 349 _CLK_DETAIL(GPIO1_CLK, CM_WKUP_GPIO0_CLKCTRL, 0), 350 _CLK_DETAIL(GPIO2_CLK, CM_PER_GPIO1_CLKCTRL, 0), 351 _CLK_DETAIL(GPIO3_CLK, CM_PER_GPIO2_CLKCTRL, 0), 352 _CLK_DETAIL(GPIO4_CLK, CM_PER_GPIO3_CLKCTRL, 0), 353 354 /* I2C modules, hwmods start with i2c1 */ 355 _CLK_DETAIL(I2C1_CLK, CM_WKUP_I2C0_CLKCTRL, 0), 356 _CLK_DETAIL(I2C2_CLK, CM_PER_I2C1_CLKCTRL, 0), 357 _CLK_DETAIL(I2C3_CLK, CM_PER_I2C2_CLKCTRL, 0), 358 359 /* TSC_ADC module */ 360 _CLK_DETAIL(TSC_ADC_CLK, CM_WKUP_ADC_TSC_CLKCTRL, 0), 361 362 /* EDMA modules */ 363 _CLK_DETAIL(EDMA_TPCC_CLK, CM_PER_TPCC_CLKCTRL, 0), 364 _CLK_DETAIL(EDMA_TPTC0_CLK, CM_PER_TPTC0_CLKCTRL, 0), 365 _CLK_DETAIL(EDMA_TPTC1_CLK, CM_PER_TPTC1_CLKCTRL, 0), 366 _CLK_DETAIL(EDMA_TPTC2_CLK, CM_PER_TPTC2_CLKCTRL, 0), 367 368 /* MMCHS modules, hwmods start with mmc1*/ 369 _CLK_DETAIL(MMC1_CLK, CM_PER_MMC0_CLKCTRL, 0), 370 _CLK_DETAIL(MMC2_CLK, CM_PER_MMC1_CLKCTRL, 0), 371 _CLK_DETAIL(MMC3_CLK, CM_PER_MMC1_CLKCTRL, 0), 372 373 /* PWMSS modules */ 374 _CLK_DETAIL(PWMSS0_CLK, CM_PER_EPWMSS0_CLKCTRL, 0), 375 _CLK_DETAIL(PWMSS1_CLK, CM_PER_EPWMSS1_CLKCTRL, 0), 376 _CLK_DETAIL(PWMSS2_CLK, CM_PER_EPWMSS2_CLKCTRL, 0), 377 378 _CLK_DETAIL(MAILBOX0_CLK, CM_PER_MAILBOX0_CLKCTRL, 0), 379 _CLK_DETAIL(SPINLOCK0_CLK, CM_PER_SPINLOCK0_CLKCTRL, 0), 380 381 /* RTC module */ 382 _CLK_DETAIL(RTC_CLK, CM_RTC_RTC_CLKCTRL, 0), 383 384 { INVALID_CLK_IDENT, 0}, 385}; 386 387/* Read/Write macros */ 388#define prcm_read_4(reg) \ 389 bus_space_read_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg) 390#define prcm_write_4(reg, val) \ 391 bus_space_write_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg, val) 392 393void am335x_prcm_setup_dmtimer(int); 394 395static int 396am335x_prcm_probe(device_t dev) 397{ 398 399 if (!ofw_bus_status_okay(dev)) 400 return (ENXIO); 401 402 if (ofw_bus_is_compatible(dev, "ti,am3-prcm")) { 403 device_set_desc(dev, "AM335x Power and Clock Management"); 404 return(BUS_PROBE_DEFAULT); 405 } 406 407 return (ENXIO); 408} 409 410static int 411am335x_prcm_attach(device_t dev) 412{ 413 struct am335x_prcm_softc *sc = device_get_softc(dev); 414 unsigned int sysclk, fclk; 415 416 if (am335x_prcm_sc) 417 return (ENXIO); 418 419 if (bus_alloc_resources(dev, am335x_prcm_spec, sc->res)) { 420 device_printf(dev, "could not allocate resources\n"); 421 return (ENXIO); 422 } 423 424 sc->bst = rman_get_bustag(sc->res[0]); 425 sc->bsh = rman_get_bushandle(sc->res[0]); 426 427 am335x_prcm_sc = sc; 428 ti_cpu_reset = am335x_prcm_reset; 429 430 if (am335x_clk_get_sysclk_freq(NULL, &sysclk) != 0) 431 sysclk = 0; 432 if (am335x_clk_get_arm_fclk_freq(NULL, &fclk) != 0) 433 fclk = 0; 434 if (sysclk && fclk) 435 device_printf(dev, "Clocks: System %u.%01u MHz, CPU %u MHz\n", 436 sysclk/1000000, (sysclk % 1000000)/100000, fclk/1000000); 437 else 438 device_printf(dev, "can't read frequencies yet (SCM device not ready?)\n"); 439 440 return (0); 441} 442 443static device_method_t am335x_prcm_methods[] = { 444 DEVMETHOD(device_probe, am335x_prcm_probe), 445 DEVMETHOD(device_attach, am335x_prcm_attach), 446 { 0, 0 } 447}; 448 449static driver_t am335x_prcm_driver = { 450 "am335x_prcm", 451 am335x_prcm_methods, 452 sizeof(struct am335x_prcm_softc), 453}; 454 455static devclass_t am335x_prcm_devclass; 456 457DRIVER_MODULE(am335x_prcm, simplebus, am335x_prcm_driver, 458 am335x_prcm_devclass, 0, 0); 459MODULE_DEPEND(am335x_prcm, ti_scm, 1, 1, 1); 460 461static struct am335x_clk_details* 462am335x_clk_details(clk_ident_t id) 463{ 464 struct am335x_clk_details *walker; 465 466 for (walker = g_am335x_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { 467 if (id == walker->id) 468 return (walker); 469 } 470 471 return NULL; 472} 473 474static int 475am335x_clk_noop_activate(struct ti_clock_dev *clkdev) 476{ 477 478 return (0); 479} 480 481static int 482am335x_clk_generic_activate(struct ti_clock_dev *clkdev) 483{ 484 struct am335x_prcm_softc *sc = am335x_prcm_sc; 485 struct am335x_clk_details* clk_details; 486 487 if (sc == NULL) 488 return ENXIO; 489 490 clk_details = am335x_clk_details(clkdev->id); 491 492 if (clk_details == NULL) 493 return (ENXIO); 494 495 /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ 496 prcm_write_4(clk_details->clkctrl_reg, 2); 497 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 2) 498 DELAY(10); 499 500 return (0); 501} 502 503static int 504am335x_clk_gpio_activate(struct ti_clock_dev *clkdev) 505{ 506 struct am335x_prcm_softc *sc = am335x_prcm_sc; 507 struct am335x_clk_details* clk_details; 508 509 if (sc == NULL) 510 return ENXIO; 511 512 clk_details = am335x_clk_details(clkdev->id); 513 514 if (clk_details == NULL) 515 return (ENXIO); 516 517 /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ 518 /* set *_CLKCTRL register OPTFCLKEN_GPIO_1_G DBCLK[18] to FCLK_EN(1) */ 519 prcm_write_4(clk_details->clkctrl_reg, 2 | (1 << 18)); 520 while ((prcm_read_4(clk_details->clkctrl_reg) & 521 (3 | (1 << 18) )) != (2 | (1 << 18))) 522 DELAY(10); 523 524 return (0); 525} 526 527static int 528am335x_clk_noop_deactivate(struct ti_clock_dev *clkdev) 529{ 530 531 return(0); 532} 533 534static int 535am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev) 536{ 537 struct am335x_prcm_softc *sc = am335x_prcm_sc; 538 struct am335x_clk_details* clk_details; 539 540 if (sc == NULL) 541 return ENXIO; 542 543 clk_details = am335x_clk_details(clkdev->id); 544 545 if (clk_details == NULL) 546 return (ENXIO); 547 548 /* set *_CLKCTRL register MODULEMODE[1:0] to disable(0) */ 549 prcm_write_4(clk_details->clkctrl_reg, 0); 550 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 0) 551 DELAY(10); 552 553 return (0); 554} 555 556static int 557am335x_clk_noop_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc) 558{ 559 560 return (0); 561} 562 563static int 564am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc) 565{ 566 struct am335x_prcm_softc *sc = am335x_prcm_sc; 567 struct am335x_clk_details* clk_details; 568 uint32_t reg; 569 570 if (sc == NULL) 571 return ENXIO; 572 573 clk_details = am335x_clk_details(clkdev->id); 574 575 if (clk_details == NULL) 576 return (ENXIO); 577 578 switch (clksrc) { 579 case EXT_CLK: 580 reg = 0; /* SEL2: TCLKIN clock */ 581 break; 582 case SYSCLK_CLK: 583 reg = 1; /* SEL1: CLK_M_OSC clock */ 584 break; 585 case F32KHZ_CLK: 586 reg = 2; /* SEL3: CLK_32KHZ clock */ 587 break; 588 default: 589 return (ENXIO); 590 } 591 592 prcm_write_4(clk_details->clksel_reg, reg); 593 while ((prcm_read_4(clk_details->clksel_reg) & 0x3) != reg) 594 DELAY(10); 595 596 return (0); 597} 598 599static int 600am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 601{ 602 *freq = 96000000; 603 return (0); 604} 605 606static int 607am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 608{ 609 uint32_t ctrl_status; 610 611 /* Read the input clock freq from the control module */ 612 /* control_status reg (0x40) */ 613 if (ti_scm_reg_read_4(0x40, &ctrl_status)) 614 return ENXIO; 615 616 switch ((ctrl_status>>22) & 0x3) { 617 case 0x0: 618 /* 19.2Mhz */ 619 *freq = 19200000; 620 break; 621 case 0x1: 622 /* 24Mhz */ 623 *freq = 24000000; 624 break; 625 case 0x2: 626 /* 25Mhz */ 627 *freq = 25000000; 628 break; 629 case 0x3: 630 /* 26Mhz */ 631 *freq = 26000000; 632 break; 633 } 634 635 return (0); 636} 637 638#define DPLL_BYP_CLKSEL(reg) ((reg>>23) & 1) 639#define DPLL_DIV(reg) ((reg & 0x7f)+1) 640#define DPLL_MULT(reg) ((reg>>8) & 0x7FF) 641#define DPLL_MAX_MUL 0x800 642#define DPLL_MAX_DIV 0x80 643 644static int 645am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 646{ 647 uint32_t reg; 648 uint32_t sysclk; 649 650 reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_MPU); 651 652 /*Check if we are running in bypass */ 653 if (DPLL_BYP_CLKSEL(reg)) 654 return ENXIO; 655 656 am335x_clk_get_sysclk_freq(NULL, &sysclk); 657 *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg)); 658 return(0); 659} 660 661static int 662am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 663{ 664 uint32_t reg; 665 uint32_t sysclk; 666 667 reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_DISP); 668 669 /*Check if we are running in bypass */ 670 if (DPLL_BYP_CLKSEL(reg)) 671 return ENXIO; 672 673 am335x_clk_get_sysclk_freq(NULL, &sysclk); 674 *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg)); 675 return(0); 676} 677 678static int 679am335x_clk_set_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int freq) 680{ 681 uint32_t sysclk; 682 uint32_t mul, div; 683 uint32_t i, j; 684 unsigned int delta, min_delta; 685 686 am335x_clk_get_sysclk_freq(NULL, &sysclk); 687 688 /* Bypass mode */ 689 prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x4); 690 691 /* Make sure it's in bypass mode */ 692 while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) 693 & (1 << 8))) 694 DELAY(10); 695 696 /* Dumb and non-optimal implementation */ 697 min_delta = freq; 698 for (i = 1; i < DPLL_MAX_MUL; i++) { 699 for (j = 1; j < DPLL_MAX_DIV; j++) { 700 delta = abs(freq - i*(sysclk/j)); 701 if (delta < min_delta) { 702 mul = i; 703 div = j; 704 min_delta = delta; 705 } 706 if (min_delta == 0) 707 break; 708 } 709 } 710 711 prcm_write_4(CM_WKUP_CM_CLKSEL_DPLL_DISP, (mul << 8) | (div - 1)); 712 713 /* Locked mode */ 714 prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7); 715 716 int timeout = 10000; 717 while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) 718 & (1 << 0))) && timeout--) 719 DELAY(10); 720 721 return(0); 722} 723 724static void 725am335x_prcm_reset(void) 726{ 727 prcm_write_4(PRM_RSTCTRL, (1<<1)); 728} 729 730static int 731am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev) 732{ 733 struct am335x_prcm_softc *sc = am335x_prcm_sc; 734 735 if (sc == NULL) 736 return ENXIO; 737 738 /* set MODULENAME to ENABLE */ 739 prcm_write_4(CM_PER_CPGMAC0_CLKCTRL, 2); 740 741 /* wait for IDLEST to become Func(0) */ 742 while(prcm_read_4(CM_PER_CPGMAC0_CLKCTRL) & (3<<16)); 743 744 /*set CLKTRCTRL to SW_WKUP(2) */ 745 prcm_write_4(CM_PER_CPSW_CLKSTCTRL, 2); 746 747 /* wait for 125 MHz OCP clock to become active */ 748 while((prcm_read_4(CM_PER_CPSW_CLKSTCTRL) & (1<<4)) == 0); 749 return(0); 750} 751 752static int 753am335x_clk_musb0_activate(struct ti_clock_dev *clkdev) 754{ 755 struct am335x_prcm_softc *sc = am335x_prcm_sc; 756 757 if (sc == NULL) 758 return ENXIO; 759 760 /* set ST_DPLL_CLKDCOLDO(9) to CLK_GATED(1) */ 761 /* set DPLL_CLKDCOLDO_GATE_CTRL(8) to CLK_ENABLE(1)*/ 762 prcm_write_4(CM_WKUP_CM_CLKDCOLDO_DPLL_PER, 0x300); 763 764 /*set MODULEMODE to ENABLE(2) */ 765 prcm_write_4(CM_PER_USB0_CLKCTRL, 2); 766 767 /* wait for MODULEMODE to become ENABLE(2) */ 768 while ((prcm_read_4(CM_PER_USB0_CLKCTRL) & 0x3) != 2) 769 DELAY(10); 770 771 /* wait for IDLEST to become Func(0) */ 772 while(prcm_read_4(CM_PER_USB0_CLKCTRL) & (3<<16)) 773 DELAY(10); 774 775 return(0); 776} 777 778static int 779am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev) 780{ 781 struct am335x_prcm_softc *sc = am335x_prcm_sc; 782 783 if (sc == NULL) 784 return (ENXIO); 785 786 /* 787 * For now set frequency to 2*VGA_PIXEL_CLOCK 788 */ 789 am335x_clk_set_arm_disp_freq(clkdev, 25175000*2); 790 791 /*set MODULEMODE to ENABLE(2) */ 792 prcm_write_4(CM_PER_LCDC_CLKCTRL, 2); 793 794 /* wait for MODULEMODE to become ENABLE(2) */ 795 while ((prcm_read_4(CM_PER_LCDC_CLKCTRL) & 0x3) != 2) 796 DELAY(10); 797 798 /* wait for IDLEST to become Func(0) */ 799 while(prcm_read_4(CM_PER_LCDC_CLKCTRL) & (3<<16)) 800 DELAY(10); 801 802 return (0); 803} 804 805static int 806am335x_clk_pruss_activate(struct ti_clock_dev *clkdev) 807{ 808 struct am335x_prcm_softc *sc = am335x_prcm_sc; 809 810 if (sc == NULL) 811 return (ENXIO); 812 813 /* Set MODULEMODE to ENABLE(2) */ 814 prcm_write_4(CM_PER_PRUSS_CLKCTRL, 2); 815 816 /* Wait for MODULEMODE to become ENABLE(2) */ 817 while ((prcm_read_4(CM_PER_PRUSS_CLKCTRL) & 0x3) != 2) 818 DELAY(10); 819 820 /* Set CLKTRCTRL to SW_WKUP(2) */ 821 prcm_write_4(CM_PER_PRUSS_CLKSTCTRL, 2); 822 823 /* Wait for the 200 MHz OCP clock to become active */ 824 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<4)) == 0) 825 DELAY(10); 826 827 /* Wait for the 200 MHz IEP clock to become active */ 828 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<5)) == 0) 829 DELAY(10); 830 831 /* Wait for the 192 MHz UART clock to become active */ 832 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<6)) == 0) 833 DELAY(10); 834 835 /* Select L3F as OCP clock */ 836 prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 0); 837 while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 0) 838 DELAY(10); 839 840 /* Clear the RESET bit */ 841 prcm_write_4(PRM_PER_RSTCTRL, prcm_read_4(PRM_PER_RSTCTRL) & ~2); 842 843 return (0); 844} 845