am335x_prcm.c revision 281085
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/ti/am335x/am335x_prcm.c 281085 2015-04-04 21:34:26Z andrew $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/malloc.h> 36#include <sys/rman.h> 37#include <sys/timeet.h> 38#include <sys/timetc.h> 39#include <sys/watchdog.h> 40#include <machine/bus.h> 41#include <machine/cpu.h> 42#include <machine/intr.h> 43 44#include <arm/ti/tivar.h> 45#include <arm/ti/ti_scm.h> 46#include <arm/ti/ti_prcm.h> 47 48#include <dev/fdt/fdt_common.h> 49#include <dev/ofw/openfirm.h> 50#include <dev/ofw/ofw_bus.h> 51#include <dev/ofw/ofw_bus_subr.h> 52 53#include <machine/bus.h> 54 55#define CM_PER 0 56#define CM_PER_L4LS_CLKSTCTRL (CM_PER + 0x000) 57#define CM_PER_L3S_CLKSTCTRL (CM_PER + 0x004) 58#define CM_PER_L3_CLKSTCTRL (CM_PER + 0x00C) 59#define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x014) 60#define CM_PER_LCDC_CLKCTRL (CM_PER + 0x018) 61#define CM_PER_USB0_CLKCTRL (CM_PER + 0x01C) 62#define CM_PER_TPTC0_CLKCTRL (CM_PER + 0x024) 63#define CM_PER_UART5_CLKCTRL (CM_PER + 0x038) 64#define CM_PER_MMC0_CLKCTRL (CM_PER + 0x03C) 65#define CM_PER_I2C2_CLKCTRL (CM_PER + 0x044) 66#define CM_PER_I2C1_CLKCTRL (CM_PER + 0x048) 67#define CM_PER_UART1_CLKCTRL (CM_PER + 0x06C) 68#define CM_PER_UART2_CLKCTRL (CM_PER + 0x070) 69#define CM_PER_UART3_CLKCTRL (CM_PER + 0x074) 70#define CM_PER_UART4_CLKCTRL (CM_PER + 0x078) 71#define CM_PER_TIMER7_CLKCTRL (CM_PER + 0x07C) 72#define CM_PER_TIMER2_CLKCTRL (CM_PER + 0x080) 73#define CM_PER_TIMER3_CLKCTRL (CM_PER + 0x084) 74#define CM_PER_TIMER4_CLKCTRL (CM_PER + 0x088) 75#define CM_PER_GPIO1_CLKCTRL (CM_PER + 0x0AC) 76#define CM_PER_GPIO2_CLKCTRL (CM_PER + 0x0B0) 77#define CM_PER_GPIO3_CLKCTRL (CM_PER + 0x0B4) 78#define CM_PER_TPCC_CLKCTRL (CM_PER + 0x0BC) 79#define CM_PER_EPWMSS1_CLKCTRL (CM_PER + 0x0CC) 80#define CM_PER_EPWMSS0_CLKCTRL (CM_PER + 0x0D4) 81#define CM_PER_EPWMSS2_CLKCTRL (CM_PER + 0x0D8) 82#define CM_PER_L3_INSTR_CLKCTRL (CM_PER + 0x0DC) 83#define CM_PER_L3_CLKCTRL (CM_PER + 0x0E0) 84#define CM_PER_PRUSS_CLKCTRL (CM_PER + 0x0E8) 85#define CM_PER_TIMER5_CLKCTRL (CM_PER + 0x0EC) 86#define CM_PER_TIMER6_CLKCTRL (CM_PER + 0x0F0) 87#define CM_PER_MMC1_CLKCTRL (CM_PER + 0x0F4) 88#define CM_PER_MMC2_CLKCTRL (CM_PER + 0x0F8) 89#define CM_PER_TPTC1_CLKCTRL (CM_PER + 0x0FC) 90#define CM_PER_TPTC2_CLKCTRL (CM_PER + 0x100) 91#define CM_PER_SPINLOCK0_CLKCTRL (CM_PER + 0x10C) 92#define CM_PER_MAILBOX0_CLKCTRL (CM_PER + 0x110) 93#define CM_PER_OCPWP_L3_CLKSTCTRL (CM_PER + 0x12C) 94#define CM_PER_OCPWP_CLKCTRL (CM_PER + 0x130) 95#define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144) 96#define CM_PER_PRUSS_CLKSTCTRL (CM_PER + 0x140) 97 98#define CM_WKUP 0x400 99#define CM_WKUP_CLKSTCTRL (CM_WKUP + 0x000) 100#define CM_WKUP_CONTROL_CLKCTRL (CM_WKUP + 0x004) 101#define CM_WKUP_GPIO0_CLKCTRL (CM_WKUP + 0x008) 102#define CM_WKUP_CM_L3_AON_CLKSTCTRL (CM_WKUP + 0x01C) 103#define CM_WKUP_CM_CLKSEL_DPLL_MPU (CM_WKUP + 0x02C) 104#define CM_WKUP_CM_IDLEST_DPLL_DISP (CM_WKUP + 0x048) 105#define CM_WKUP_CM_CLKSEL_DPLL_DISP (CM_WKUP + 0x054) 106#define CM_WKUP_CM_CLKDCOLDO_DPLL_PER (CM_WKUP + 0x07C) 107#define CM_WKUP_CM_CLKMODE_DPLL_DISP (CM_WKUP + 0x098) 108#define CM_WKUP_I2C0_CLKCTRL (CM_WKUP + 0x0B8) 109#define CM_WKUP_ADC_TSC_CLKCTRL (CM_WKUP + 0x0BC) 110 111#define CM_DPLL 0x500 112#define CLKSEL_TIMER7_CLK (CM_DPLL + 0x004) 113#define CLKSEL_TIMER2_CLK (CM_DPLL + 0x008) 114#define CLKSEL_TIMER3_CLK (CM_DPLL + 0x00C) 115#define CLKSEL_TIMER4_CLK (CM_DPLL + 0x010) 116#define CLKSEL_TIMER5_CLK (CM_DPLL + 0x018) 117#define CLKSEL_TIMER6_CLK (CM_DPLL + 0x01C) 118#define CLKSEL_PRUSS_OCP_CLK (CM_DPLL + 0x030) 119 120#define CM_RTC 0x800 121#define CM_RTC_RTC_CLKCTRL (CM_RTC + 0x000) 122#define CM_RTC_CLKSTCTRL (CM_RTC + 0x004) 123 124#define PRM_PER 0xC00 125#define PRM_PER_RSTCTRL (PRM_PER + 0x00) 126 127#define PRM_DEVICE_OFFSET 0xF00 128#define PRM_RSTCTRL (PRM_DEVICE_OFFSET + 0x00) 129 130struct am335x_prcm_softc { 131 struct resource * res[2]; 132 bus_space_tag_t bst; 133 bus_space_handle_t bsh; 134}; 135 136static struct resource_spec am335x_prcm_spec[] = { 137 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 138 { -1, 0 } 139}; 140 141static struct am335x_prcm_softc *am335x_prcm_sc = NULL; 142 143static int am335x_clk_noop_activate(struct ti_clock_dev *clkdev); 144static int am335x_clk_generic_activate(struct ti_clock_dev *clkdev); 145static int am335x_clk_gpio_activate(struct ti_clock_dev *clkdev); 146static int am335x_clk_noop_deactivate(struct ti_clock_dev *clkdev); 147static int am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev); 148static int am335x_clk_noop_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 149static int am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 150static int am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 151static int am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 152static int am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 153static int am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 154static void am335x_prcm_reset(void); 155static int am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev); 156static int am335x_clk_musb0_activate(struct ti_clock_dev *clkdev); 157static int am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev); 158static int am335x_clk_pruss_activate(struct ti_clock_dev *clkdev); 159 160#define AM335X_NOOP_CLOCK_DEV(i) \ 161 { .id = (i), \ 162 .clk_activate = am335x_clk_noop_activate, \ 163 .clk_deactivate = am335x_clk_noop_deactivate, \ 164 .clk_set_source = am335x_clk_noop_set_source, \ 165 .clk_accessible = NULL, \ 166 .clk_get_source_freq = NULL \ 167 } 168 169#define AM335X_GENERIC_CLOCK_DEV(i) \ 170 { .id = (i), \ 171 .clk_activate = am335x_clk_generic_activate, \ 172 .clk_deactivate = am335x_clk_generic_deactivate, \ 173 .clk_set_source = am335x_clk_generic_set_source, \ 174 .clk_accessible = NULL, \ 175 .clk_get_source_freq = NULL \ 176 } 177 178#define AM335X_GPIO_CLOCK_DEV(i) \ 179 { .id = (i), \ 180 .clk_activate = am335x_clk_gpio_activate, \ 181 .clk_deactivate = am335x_clk_generic_deactivate, \ 182 .clk_set_source = am335x_clk_generic_set_source, \ 183 .clk_accessible = NULL, \ 184 .clk_get_source_freq = NULL \ 185 } 186 187#define AM335X_MMCHS_CLOCK_DEV(i) \ 188 { .id = (i), \ 189 .clk_activate = am335x_clk_generic_activate, \ 190 .clk_deactivate = am335x_clk_generic_deactivate, \ 191 .clk_set_source = am335x_clk_generic_set_source, \ 192 .clk_accessible = NULL, \ 193 .clk_get_source_freq = am335x_clk_hsmmc_get_source_freq \ 194 } 195 196struct ti_clock_dev ti_am335x_clk_devmap[] = { 197 /* System clocks */ 198 { .id = SYS_CLK, 199 .clk_activate = NULL, 200 .clk_deactivate = NULL, 201 .clk_set_source = NULL, 202 .clk_accessible = NULL, 203 .clk_get_source_freq = am335x_clk_get_sysclk_freq, 204 }, 205 /* MPU (ARM) core clocks */ 206 { .id = MPU_CLK, 207 .clk_activate = NULL, 208 .clk_deactivate = NULL, 209 .clk_set_source = NULL, 210 .clk_accessible = NULL, 211 .clk_get_source_freq = am335x_clk_get_arm_fclk_freq, 212 }, 213 /* CPSW Ethernet Switch core clocks */ 214 { .id = CPSW_CLK, 215 .clk_activate = am335x_clk_cpsw_activate, 216 .clk_deactivate = NULL, 217 .clk_set_source = NULL, 218 .clk_accessible = NULL, 219 .clk_get_source_freq = NULL, 220 }, 221 222 /* Mentor USB HS controller core clocks */ 223 { .id = MUSB0_CLK, 224 .clk_activate = am335x_clk_musb0_activate, 225 .clk_deactivate = NULL, 226 .clk_set_source = NULL, 227 .clk_accessible = NULL, 228 .clk_get_source_freq = NULL, 229 }, 230 231 /* LCD controller clocks */ 232 { .id = LCDC_CLK, 233 .clk_activate = am335x_clk_lcdc_activate, 234 .clk_deactivate = NULL, 235 .clk_set_source = NULL, 236 .clk_accessible = NULL, 237 .clk_get_source_freq = am335x_clk_get_arm_disp_freq, 238 }, 239 240 /* UART. Uart0 clock cannot be controlled. */ 241 AM335X_NOOP_CLOCK_DEV(UART0_CLK), 242 AM335X_GENERIC_CLOCK_DEV(UART1_CLK), 243 AM335X_GENERIC_CLOCK_DEV(UART2_CLK), 244 AM335X_GENERIC_CLOCK_DEV(UART3_CLK), 245 AM335X_GENERIC_CLOCK_DEV(UART4_CLK), 246 AM335X_GENERIC_CLOCK_DEV(UART5_CLK), 247 248 /* DMTimer */ 249 AM335X_GENERIC_CLOCK_DEV(DMTIMER2_CLK), 250 AM335X_GENERIC_CLOCK_DEV(DMTIMER3_CLK), 251 AM335X_GENERIC_CLOCK_DEV(DMTIMER4_CLK), 252 AM335X_GENERIC_CLOCK_DEV(DMTIMER5_CLK), 253 AM335X_GENERIC_CLOCK_DEV(DMTIMER6_CLK), 254 AM335X_GENERIC_CLOCK_DEV(DMTIMER7_CLK), 255 256 /* GPIO */ 257 AM335X_GPIO_CLOCK_DEV(GPIO0_CLK), 258 AM335X_GPIO_CLOCK_DEV(GPIO1_CLK), 259 AM335X_GPIO_CLOCK_DEV(GPIO2_CLK), 260 AM335X_GPIO_CLOCK_DEV(GPIO3_CLK), 261 262 /* I2C */ 263 AM335X_GENERIC_CLOCK_DEV(I2C0_CLK), 264 AM335X_GENERIC_CLOCK_DEV(I2C1_CLK), 265 AM335X_GENERIC_CLOCK_DEV(I2C2_CLK), 266 267 /* TSC_ADC */ 268 AM335X_GENERIC_CLOCK_DEV(TSC_ADC_CLK), 269 270 /* EDMA */ 271 AM335X_GENERIC_CLOCK_DEV(EDMA_TPCC_CLK), 272 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC0_CLK), 273 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC1_CLK), 274 AM335X_GENERIC_CLOCK_DEV(EDMA_TPTC2_CLK), 275 276 /* MMCHS */ 277 AM335X_MMCHS_CLOCK_DEV(MMC0_CLK), 278 AM335X_MMCHS_CLOCK_DEV(MMC1_CLK), 279 AM335X_MMCHS_CLOCK_DEV(MMC2_CLK), 280 281 /* PWMSS */ 282 AM335X_GENERIC_CLOCK_DEV(PWMSS0_CLK), 283 AM335X_GENERIC_CLOCK_DEV(PWMSS1_CLK), 284 AM335X_GENERIC_CLOCK_DEV(PWMSS2_CLK), 285 286 /* System Mailbox clock */ 287 AM335X_GENERIC_CLOCK_DEV(MAILBOX0_CLK), 288 289 /* SPINLOCK */ 290 AM335X_GENERIC_CLOCK_DEV(SPINLOCK0_CLK), 291 292 /* PRU-ICSS */ 293 { .id = PRUSS_CLK, 294 .clk_activate = am335x_clk_pruss_activate, 295 .clk_deactivate = NULL, 296 .clk_set_source = NULL, 297 .clk_accessible = NULL, 298 .clk_get_source_freq = NULL, 299 }, 300 301 /* RTC */ 302 AM335X_GENERIC_CLOCK_DEV(RTC_CLK), 303 304 { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } 305}; 306 307struct am335x_clk_details { 308 clk_ident_t id; 309 uint32_t clkctrl_reg; 310 uint32_t clksel_reg; 311}; 312 313#define _CLK_DETAIL(i, c, s) \ 314 { .id = (i), \ 315 .clkctrl_reg = (c), \ 316 .clksel_reg = (s), \ 317 } 318 319static struct am335x_clk_details g_am335x_clk_details[] = { 320 321 /* UART. UART0 clock not controllable. */ 322 _CLK_DETAIL(UART0_CLK, 0, 0), 323 _CLK_DETAIL(UART1_CLK, CM_PER_UART1_CLKCTRL, 0), 324 _CLK_DETAIL(UART2_CLK, CM_PER_UART2_CLKCTRL, 0), 325 _CLK_DETAIL(UART3_CLK, CM_PER_UART3_CLKCTRL, 0), 326 _CLK_DETAIL(UART4_CLK, CM_PER_UART4_CLKCTRL, 0), 327 _CLK_DETAIL(UART5_CLK, CM_PER_UART5_CLKCTRL, 0), 328 329 /* DMTimer modules */ 330 _CLK_DETAIL(DMTIMER2_CLK, CM_PER_TIMER2_CLKCTRL, CLKSEL_TIMER2_CLK), 331 _CLK_DETAIL(DMTIMER3_CLK, CM_PER_TIMER3_CLKCTRL, CLKSEL_TIMER3_CLK), 332 _CLK_DETAIL(DMTIMER4_CLK, CM_PER_TIMER4_CLKCTRL, CLKSEL_TIMER4_CLK), 333 _CLK_DETAIL(DMTIMER5_CLK, CM_PER_TIMER5_CLKCTRL, CLKSEL_TIMER5_CLK), 334 _CLK_DETAIL(DMTIMER6_CLK, CM_PER_TIMER6_CLKCTRL, CLKSEL_TIMER6_CLK), 335 _CLK_DETAIL(DMTIMER7_CLK, CM_PER_TIMER7_CLKCTRL, CLKSEL_TIMER7_CLK), 336 337 /* GPIO modules */ 338 _CLK_DETAIL(GPIO0_CLK, CM_WKUP_GPIO0_CLKCTRL, 0), 339 _CLK_DETAIL(GPIO1_CLK, CM_PER_GPIO1_CLKCTRL, 0), 340 _CLK_DETAIL(GPIO2_CLK, CM_PER_GPIO2_CLKCTRL, 0), 341 _CLK_DETAIL(GPIO3_CLK, CM_PER_GPIO3_CLKCTRL, 0), 342 343 /* I2C modules */ 344 _CLK_DETAIL(I2C0_CLK, CM_WKUP_I2C0_CLKCTRL, 0), 345 _CLK_DETAIL(I2C1_CLK, CM_PER_I2C1_CLKCTRL, 0), 346 _CLK_DETAIL(I2C2_CLK, CM_PER_I2C2_CLKCTRL, 0), 347 348 /* TSC_ADC module */ 349 _CLK_DETAIL(TSC_ADC_CLK, CM_WKUP_ADC_TSC_CLKCTRL, 0), 350 351 /* EDMA modules */ 352 _CLK_DETAIL(EDMA_TPCC_CLK, CM_PER_TPCC_CLKCTRL, 0), 353 _CLK_DETAIL(EDMA_TPTC0_CLK, CM_PER_TPTC0_CLKCTRL, 0), 354 _CLK_DETAIL(EDMA_TPTC1_CLK, CM_PER_TPTC1_CLKCTRL, 0), 355 _CLK_DETAIL(EDMA_TPTC2_CLK, CM_PER_TPTC2_CLKCTRL, 0), 356 357 /* MMCHS modules*/ 358 _CLK_DETAIL(MMC0_CLK, CM_PER_MMC0_CLKCTRL, 0), 359 _CLK_DETAIL(MMC1_CLK, CM_PER_MMC1_CLKCTRL, 0), 360 _CLK_DETAIL(MMC2_CLK, CM_PER_MMC1_CLKCTRL, 0), 361 362 /* PWMSS modules */ 363 _CLK_DETAIL(PWMSS0_CLK, CM_PER_EPWMSS0_CLKCTRL, 0), 364 _CLK_DETAIL(PWMSS1_CLK, CM_PER_EPWMSS1_CLKCTRL, 0), 365 _CLK_DETAIL(PWMSS2_CLK, CM_PER_EPWMSS2_CLKCTRL, 0), 366 367 _CLK_DETAIL(MAILBOX0_CLK, CM_PER_MAILBOX0_CLKCTRL, 0), 368 _CLK_DETAIL(SPINLOCK0_CLK, CM_PER_SPINLOCK0_CLKCTRL, 0), 369 370 /* RTC module */ 371 _CLK_DETAIL(RTC_CLK, CM_RTC_RTC_CLKCTRL, 0), 372 373 { INVALID_CLK_IDENT, 0}, 374}; 375 376/* Read/Write macros */ 377#define prcm_read_4(reg) \ 378 bus_space_read_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg) 379#define prcm_write_4(reg, val) \ 380 bus_space_write_4(am335x_prcm_sc->bst, am335x_prcm_sc->bsh, reg, val) 381 382void am335x_prcm_setup_dmtimer(int); 383 384static int 385am335x_prcm_probe(device_t dev) 386{ 387 388 if (!ofw_bus_status_okay(dev)) 389 return (ENXIO); 390 391 if (ofw_bus_is_compatible(dev, "am335x,prcm")) { 392 device_set_desc(dev, "AM335x Power and Clock Management"); 393 return(BUS_PROBE_DEFAULT); 394 } 395 396 return (ENXIO); 397} 398 399static int 400am335x_prcm_attach(device_t dev) 401{ 402 struct am335x_prcm_softc *sc = device_get_softc(dev); 403 unsigned int sysclk, fclk; 404 405 if (am335x_prcm_sc) 406 return (ENXIO); 407 408 if (bus_alloc_resources(dev, am335x_prcm_spec, sc->res)) { 409 device_printf(dev, "could not allocate resources\n"); 410 return (ENXIO); 411 } 412 413 sc->bst = rman_get_bustag(sc->res[0]); 414 sc->bsh = rman_get_bushandle(sc->res[0]); 415 416 am335x_prcm_sc = sc; 417 ti_cpu_reset = am335x_prcm_reset; 418 419 am335x_clk_get_sysclk_freq(NULL, &sysclk); 420 am335x_clk_get_arm_fclk_freq(NULL, &fclk); 421 device_printf(dev, "Clocks: System %u.%01u MHz, CPU %u MHz\n", 422 sysclk/1000000, (sysclk % 1000000)/100000, fclk/1000000); 423 424 return (0); 425} 426 427static device_method_t am335x_prcm_methods[] = { 428 DEVMETHOD(device_probe, am335x_prcm_probe), 429 DEVMETHOD(device_attach, am335x_prcm_attach), 430 { 0, 0 } 431}; 432 433static driver_t am335x_prcm_driver = { 434 "am335x_prcm", 435 am335x_prcm_methods, 436 sizeof(struct am335x_prcm_softc), 437}; 438 439static devclass_t am335x_prcm_devclass; 440 441DRIVER_MODULE(am335x_prcm, simplebus, am335x_prcm_driver, 442 am335x_prcm_devclass, 0, 0); 443MODULE_DEPEND(am335x_prcm, ti_scm, 1, 1, 1); 444 445static struct am335x_clk_details* 446am335x_clk_details(clk_ident_t id) 447{ 448 struct am335x_clk_details *walker; 449 450 for (walker = g_am335x_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { 451 if (id == walker->id) 452 return (walker); 453 } 454 455 return NULL; 456} 457 458static int 459am335x_clk_noop_activate(struct ti_clock_dev *clkdev) 460{ 461 462 return (0); 463} 464 465static int 466am335x_clk_generic_activate(struct ti_clock_dev *clkdev) 467{ 468 struct am335x_prcm_softc *sc = am335x_prcm_sc; 469 struct am335x_clk_details* clk_details; 470 471 if (sc == NULL) 472 return ENXIO; 473 474 clk_details = am335x_clk_details(clkdev->id); 475 476 if (clk_details == NULL) 477 return (ENXIO); 478 479 /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ 480 prcm_write_4(clk_details->clkctrl_reg, 2); 481 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 2) 482 DELAY(10); 483 484 return (0); 485} 486 487static int 488am335x_clk_gpio_activate(struct ti_clock_dev *clkdev) 489{ 490 struct am335x_prcm_softc *sc = am335x_prcm_sc; 491 struct am335x_clk_details* clk_details; 492 493 if (sc == NULL) 494 return ENXIO; 495 496 clk_details = am335x_clk_details(clkdev->id); 497 498 if (clk_details == NULL) 499 return (ENXIO); 500 501 /* set *_CLKCTRL register MODULEMODE[1:0] to enable(2) */ 502 /* set *_CLKCTRL register OPTFCLKEN_GPIO_1_G DBCLK[18] to FCLK_EN(1) */ 503 prcm_write_4(clk_details->clkctrl_reg, 2 | (1 << 18)); 504 while ((prcm_read_4(clk_details->clkctrl_reg) & 505 (3 | (1 << 18) )) != (2 | (1 << 18))) 506 DELAY(10); 507 508 return (0); 509} 510 511static int 512am335x_clk_noop_deactivate(struct ti_clock_dev *clkdev) 513{ 514 515 return(0); 516} 517 518static int 519am335x_clk_generic_deactivate(struct ti_clock_dev *clkdev) 520{ 521 struct am335x_prcm_softc *sc = am335x_prcm_sc; 522 struct am335x_clk_details* clk_details; 523 524 if (sc == NULL) 525 return ENXIO; 526 527 clk_details = am335x_clk_details(clkdev->id); 528 529 if (clk_details == NULL) 530 return (ENXIO); 531 532 /* set *_CLKCTRL register MODULEMODE[1:0] to disable(0) */ 533 prcm_write_4(clk_details->clkctrl_reg, 0); 534 while ((prcm_read_4(clk_details->clkctrl_reg) & 0x3) != 0) 535 DELAY(10); 536 537 return (0); 538} 539 540static int 541am335x_clk_noop_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc) 542{ 543 544 return (0); 545} 546 547static int 548am335x_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc) 549{ 550 struct am335x_prcm_softc *sc = am335x_prcm_sc; 551 struct am335x_clk_details* clk_details; 552 uint32_t reg; 553 554 if (sc == NULL) 555 return ENXIO; 556 557 clk_details = am335x_clk_details(clkdev->id); 558 559 if (clk_details == NULL) 560 return (ENXIO); 561 562 switch (clksrc) { 563 case EXT_CLK: 564 reg = 0; /* SEL2: TCLKIN clock */ 565 break; 566 case SYSCLK_CLK: 567 reg = 1; /* SEL1: CLK_M_OSC clock */ 568 break; 569 case F32KHZ_CLK: 570 reg = 2; /* SEL3: CLK_32KHZ clock */ 571 break; 572 default: 573 return (ENXIO); 574 } 575 576 prcm_write_4(clk_details->clksel_reg, reg); 577 while ((prcm_read_4(clk_details->clksel_reg) & 0x3) != reg) 578 DELAY(10); 579 580 return (0); 581} 582 583static int 584am335x_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 585{ 586 *freq = 96000000; 587 return (0); 588} 589 590static int 591am335x_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 592{ 593 uint32_t ctrl_status; 594 595 /* Read the input clock freq from the control module */ 596 /* control_status reg (0x40) */ 597 if (ti_scm_reg_read_4(0x40, &ctrl_status)) 598 return ENXIO; 599 600 switch ((ctrl_status>>22) & 0x3) { 601 case 0x0: 602 /* 19.2Mhz */ 603 *freq = 19200000; 604 break; 605 case 0x1: 606 /* 24Mhz */ 607 *freq = 24000000; 608 break; 609 case 0x2: 610 /* 25Mhz */ 611 *freq = 25000000; 612 break; 613 case 0x3: 614 /* 26Mhz */ 615 *freq = 26000000; 616 break; 617 } 618 619 return (0); 620} 621 622#define DPLL_BYP_CLKSEL(reg) ((reg>>23) & 1) 623#define DPLL_DIV(reg) ((reg & 0x7f)+1) 624#define DPLL_MULT(reg) ((reg>>8) & 0x7FF) 625 626static int 627am335x_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 628{ 629 uint32_t reg; 630 uint32_t sysclk; 631 632 reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_MPU); 633 634 /*Check if we are running in bypass */ 635 if (DPLL_BYP_CLKSEL(reg)) 636 return ENXIO; 637 638 am335x_clk_get_sysclk_freq(NULL, &sysclk); 639 *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg)); 640 return(0); 641} 642 643static int 644am335x_clk_get_arm_disp_freq(struct ti_clock_dev *clkdev, unsigned int *freq) 645{ 646 uint32_t reg; 647 uint32_t sysclk; 648 649 reg = prcm_read_4(CM_WKUP_CM_CLKSEL_DPLL_DISP); 650 651 /*Check if we are running in bypass */ 652 if (DPLL_BYP_CLKSEL(reg)) 653 return ENXIO; 654 655 am335x_clk_get_sysclk_freq(NULL, &sysclk); 656 *freq = DPLL_MULT(reg) * (sysclk / DPLL_DIV(reg)); 657 return(0); 658} 659 660static void 661am335x_prcm_reset(void) 662{ 663 prcm_write_4(PRM_RSTCTRL, (1<<1)); 664} 665 666static int 667am335x_clk_cpsw_activate(struct ti_clock_dev *clkdev) 668{ 669 struct am335x_prcm_softc *sc = am335x_prcm_sc; 670 671 if (sc == NULL) 672 return ENXIO; 673 674 /* set MODULENAME to ENABLE */ 675 prcm_write_4(CM_PER_CPGMAC0_CLKCTRL, 2); 676 677 /* wait for IDLEST to become Func(0) */ 678 while(prcm_read_4(CM_PER_CPGMAC0_CLKCTRL) & (3<<16)); 679 680 /*set CLKTRCTRL to SW_WKUP(2) */ 681 prcm_write_4(CM_PER_CPSW_CLKSTCTRL, 2); 682 683 /* wait for 125 MHz OCP clock to become active */ 684 while((prcm_read_4(CM_PER_CPSW_CLKSTCTRL) & (1<<4)) == 0); 685 return(0); 686} 687 688static int 689am335x_clk_musb0_activate(struct ti_clock_dev *clkdev) 690{ 691 struct am335x_prcm_softc *sc = am335x_prcm_sc; 692 693 if (sc == NULL) 694 return ENXIO; 695 696 /* set ST_DPLL_CLKDCOLDO(9) to CLK_GATED(1) */ 697 /* set DPLL_CLKDCOLDO_GATE_CTRL(8) to CLK_ENABLE(1)*/ 698 prcm_write_4(CM_WKUP_CM_CLKDCOLDO_DPLL_PER, 0x300); 699 700 /*set MODULEMODE to ENABLE(2) */ 701 prcm_write_4(CM_PER_USB0_CLKCTRL, 2); 702 703 /* wait for MODULEMODE to become ENABLE(2) */ 704 while ((prcm_read_4(CM_PER_USB0_CLKCTRL) & 0x3) != 2) 705 DELAY(10); 706 707 /* wait for IDLEST to become Func(0) */ 708 while(prcm_read_4(CM_PER_USB0_CLKCTRL) & (3<<16)) 709 DELAY(10); 710 711 return(0); 712} 713 714static int 715am335x_clk_lcdc_activate(struct ti_clock_dev *clkdev) 716{ 717 struct am335x_prcm_softc *sc = am335x_prcm_sc; 718 719 if (sc == NULL) 720 return (ENXIO); 721 722 /* Bypass mode */ 723 prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x4); 724 725 /* Make sure it's in bypass mode */ 726 while (!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) 727 & (1 << 8))) 728 DELAY(10); 729 730 /* 731 * For now set frequency to 99*SYSFREQ/8 which is twice as 732 * HDMI 1080p pixel clock (minimum LCDC freq divisor is 2) 733 */ 734 prcm_write_4(CM_WKUP_CM_CLKSEL_DPLL_DISP, (99 << 8) | 8); 735 736 /* Locked mode */ 737 prcm_write_4(CM_WKUP_CM_CLKMODE_DPLL_DISP, 0x7); 738 739 int timeout = 10000; 740 while ((!(prcm_read_4(CM_WKUP_CM_IDLEST_DPLL_DISP) 741 & (1 << 0))) && timeout--) 742 DELAY(10); 743 744 /*set MODULEMODE to ENABLE(2) */ 745 prcm_write_4(CM_PER_LCDC_CLKCTRL, 2); 746 747 /* wait for MODULEMODE to become ENABLE(2) */ 748 while ((prcm_read_4(CM_PER_LCDC_CLKCTRL) & 0x3) != 2) 749 DELAY(10); 750 751 /* wait for IDLEST to become Func(0) */ 752 while(prcm_read_4(CM_PER_LCDC_CLKCTRL) & (3<<16)) 753 DELAY(10); 754 755 return (0); 756} 757 758static int 759am335x_clk_pruss_activate(struct ti_clock_dev *clkdev) 760{ 761 struct am335x_prcm_softc *sc = am335x_prcm_sc; 762 763 if (sc == NULL) 764 return (ENXIO); 765 766 /* Set MODULEMODE to ENABLE(2) */ 767 prcm_write_4(CM_PER_PRUSS_CLKCTRL, 2); 768 769 /* Wait for MODULEMODE to become ENABLE(2) */ 770 while ((prcm_read_4(CM_PER_PRUSS_CLKCTRL) & 0x3) != 2) 771 DELAY(10); 772 773 /* Set CLKTRCTRL to SW_WKUP(2) */ 774 prcm_write_4(CM_PER_PRUSS_CLKSTCTRL, 2); 775 776 /* Wait for the 200 MHz OCP clock to become active */ 777 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<4)) == 0) 778 DELAY(10); 779 780 /* Wait for the 200 MHz IEP clock to become active */ 781 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<5)) == 0) 782 DELAY(10); 783 784 /* Wait for the 192 MHz UART clock to become active */ 785 while ((prcm_read_4(CM_PER_PRUSS_CLKSTCTRL) & (1<<6)) == 0) 786 DELAY(10); 787 788 /* Select L3F as OCP clock */ 789 prcm_write_4(CLKSEL_PRUSS_OCP_CLK, 0); 790 while ((prcm_read_4(CLKSEL_PRUSS_OCP_CLK) & 0x3) != 0) 791 DELAY(10); 792 793 /* Clear the RESET bit */ 794 prcm_write_4(PRM_PER_RSTCTRL, prcm_read_4(PRM_PER_RSTCTRL) & ~2); 795 796 return (0); 797} 798