1/*- 2 * Copyright (c) 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/11/sys/arm/ti/am335x/am335x_musb.c 308401 2016-11-07 08:36:06Z hselasky $"); 28 29#include <sys/stdint.h> 30#include <sys/stddef.h> 31#include <sys/param.h> 32#include <sys/queue.h> 33#include <sys/types.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/bus.h> 37#include <sys/module.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/condvar.h> 41#include <sys/sysctl.h> 42#include <sys/sx.h> 43#include <sys/unistd.h> 44#include <sys/callout.h> 45#include <sys/malloc.h> 46#include <sys/priv.h> 47 48#include <dev/fdt/fdt_common.h> 49#include <dev/ofw/openfirm.h> 50#include <dev/ofw/ofw_bus.h> 51#include <dev/ofw/ofw_bus_subr.h> 52 53#include <dev/usb/usb.h> 54#include <dev/usb/usbdi.h> 55 56#include <dev/usb/usb_core.h> 57#include <dev/usb/usb_busdma.h> 58#include <dev/usb/usb_process.h> 59#include <dev/usb/usb_util.h> 60 61#define USB_DEBUG_VAR usbssdebug 62 63#include <dev/usb/usb_controller.h> 64#include <dev/usb/usb_bus.h> 65#include <dev/usb/controller/musb_otg.h> 66#include <dev/usb/usb_debug.h> 67 68#include <sys/rman.h> 69 70#include <arm/ti/ti_prcm.h> 71#include <arm/ti/ti_scm.h> 72#include <arm/ti/am335x/am335x_scm.h> 73 74#define USBCTRL_REV 0x00 75#define USBCTRL_CTRL 0x14 76#define USBCTRL_STAT 0x18 77#define USBCTRL_IRQ_STAT0 0x30 78#define IRQ_STAT0_RXSHIFT 16 79#define IRQ_STAT0_TXSHIFT 0 80#define USBCTRL_IRQ_STAT1 0x34 81#define IRQ_STAT1_DRVVBUS (1 << 8) 82#define USBCTRL_INTEN_SET0 0x38 83#define USBCTRL_INTEN_SET1 0x3C 84#define USBCTRL_INTEN_USB_ALL 0x1ff 85#define USBCTRL_INTEN_USB_SOF (1 << 3) 86#define USBCTRL_INTEN_CLR0 0x40 87#define USBCTRL_INTEN_CLR1 0x44 88#define USBCTRL_UTMI 0xE0 89#define USBCTRL_UTMI_FSDATAEXT (1 << 1) 90#define USBCTRL_MODE 0xE8 91#define USBCTRL_MODE_IDDIG (1 << 8) 92#define USBCTRL_MODE_IDDIGMUX (1 << 7) 93 94/* USBSS resource + 2 MUSB ports */ 95 96#define RES_USBCORE 0 97#define RES_USBCTRL 1 98 99#define USB_WRITE4(sc, idx, reg, val) do { \ 100 bus_write_4((sc)->sc_mem_res[idx], (reg), (val)); \ 101} while (0) 102 103#define USB_READ4(sc, idx, reg) bus_read_4((sc)->sc_mem_res[idx], (reg)) 104 105#define USBCTRL_WRITE4(sc, reg, val) \ 106 USB_WRITE4((sc), RES_USBCTRL, (reg), (val)) 107#define USBCTRL_READ4(sc, reg) \ 108 USB_READ4((sc), RES_USBCTRL, (reg)) 109 110static struct resource_spec am335x_musbotg_mem_spec[] = { 111 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 112 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 113 { -1, 0, 0 } 114}; 115 116#ifdef USB_DEBUG 117static int usbssdebug = 0; 118 119static SYSCTL_NODE(_hw_usb, OID_AUTO, am335x_usbss, CTLFLAG_RW, 0, "AM335x USBSS"); 120SYSCTL_INT(_hw_usb_am335x_usbss, OID_AUTO, debug, CTLFLAG_RW, 121 &usbssdebug, 0, "Debug level"); 122#endif 123 124static device_probe_t musbotg_probe; 125static device_attach_t musbotg_attach; 126static device_detach_t musbotg_detach; 127 128struct musbotg_super_softc { 129 struct musbotg_softc sc_otg; 130 struct resource *sc_mem_res[2]; 131 int sc_irq_rid; 132}; 133 134static void 135musbotg_vbus_poll(struct musbotg_super_softc *sc) 136{ 137 uint32_t stat; 138 139 if (sc->sc_otg.sc_mode == MUSB2_DEVICE_MODE) 140 musbotg_vbus_interrupt(&sc->sc_otg, 1); 141 else { 142 stat = USBCTRL_READ4(sc, USBCTRL_STAT); 143 musbotg_vbus_interrupt(&sc->sc_otg, stat & 1); 144 } 145} 146 147/* 148 * Arg to musbotg_clocks_on and musbot_clocks_off is 149 * a uint32_t * pointing to the SCM register offset. 150 */ 151static uint32_t USB_CTRL[] = {SCM_USB_CTRL0, SCM_USB_CTRL1}; 152 153static void 154musbotg_clocks_on(void *arg) 155{ 156 struct musbotg_softc *sc; 157 uint32_t c, reg; 158 159 sc = arg; 160 reg = USB_CTRL[sc->sc_id]; 161 162 ti_scm_reg_read_4(reg, &c); 163 c &= ~3; /* Enable power */ 164 c |= 1 << 19; /* VBUS detect enable */ 165 c |= 1 << 20; /* Session end enable */ 166 ti_scm_reg_write_4(reg, c); 167} 168 169static void 170musbotg_clocks_off(void *arg) 171{ 172 struct musbotg_softc *sc; 173 uint32_t c, reg; 174 175 sc = arg; 176 reg = USB_CTRL[sc->sc_id]; 177 178 /* Disable power to PHY */ 179 ti_scm_reg_read_4(reg, &c); 180 ti_scm_reg_write_4(reg, c | 3); 181} 182 183static void 184musbotg_ep_int_set(struct musbotg_softc *sc, int ep, int on) 185{ 186 struct musbotg_super_softc *ssc = sc->sc_platform_data; 187 uint32_t epmask; 188 189 epmask = ((1 << ep) << IRQ_STAT0_RXSHIFT); 190 epmask |= ((1 << ep) << IRQ_STAT0_TXSHIFT); 191 if (on) 192 USBCTRL_WRITE4(ssc, USBCTRL_INTEN_SET0, epmask); 193 else 194 USBCTRL_WRITE4(ssc, USBCTRL_INTEN_CLR0, epmask); 195} 196 197static void 198musbotg_wrapper_interrupt(void *arg) 199{ 200 struct musbotg_softc *sc = arg; 201 struct musbotg_super_softc *ssc = sc->sc_platform_data; 202 uint32_t stat, stat0, stat1; 203 204 stat = USBCTRL_READ4(ssc, USBCTRL_STAT); 205 stat0 = USBCTRL_READ4(ssc, USBCTRL_IRQ_STAT0); 206 stat1 = USBCTRL_READ4(ssc, USBCTRL_IRQ_STAT1); 207 if (stat0) 208 USBCTRL_WRITE4(ssc, USBCTRL_IRQ_STAT0, stat0); 209 if (stat1) 210 USBCTRL_WRITE4(ssc, USBCTRL_IRQ_STAT1, stat1); 211 212 DPRINTFN(4, "port%d: stat0=%08x stat1=%08x, stat=%08x\n", 213 sc->sc_id, stat0, stat1, stat); 214 215 if (stat1 & IRQ_STAT1_DRVVBUS) 216 musbotg_vbus_interrupt(sc, stat & 1); 217 218 musbotg_interrupt(arg, ((stat0 >> 16) & 0xffff), 219 stat0 & 0xffff, stat1 & 0xff); 220} 221 222static int 223musbotg_probe(device_t dev) 224{ 225 if (!ofw_bus_status_okay(dev)) 226 return (ENXIO); 227 228 if (!ofw_bus_is_compatible(dev, "ti,musb-am33xx")) 229 return (ENXIO); 230 231 device_set_desc(dev, "TI AM33xx integrated USB OTG controller"); 232 233 return (BUS_PROBE_DEFAULT); 234} 235 236static int 237musbotg_attach(device_t dev) 238{ 239 struct musbotg_super_softc *sc = device_get_softc(dev); 240 char mode[16]; 241 int err; 242 uint32_t reg; 243 244 sc->sc_otg.sc_id = device_get_unit(dev); 245 246 /* Request the memory resources */ 247 err = bus_alloc_resources(dev, am335x_musbotg_mem_spec, 248 sc->sc_mem_res); 249 if (err) { 250 device_printf(dev, 251 "Error: could not allocate mem resources\n"); 252 return (ENXIO); 253 } 254 255 /* Request the IRQ resources */ 256 sc->sc_otg.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 257 &sc->sc_irq_rid, RF_ACTIVE); 258 if (sc->sc_otg.sc_irq_res == NULL) { 259 device_printf(dev, 260 "Error: could not allocate irq resources\n"); 261 return (ENXIO); 262 } 263 264 /* setup MUSB OTG USB controller interface softc */ 265 sc->sc_otg.sc_clocks_on = &musbotg_clocks_on; 266 sc->sc_otg.sc_clocks_off = &musbotg_clocks_off; 267 sc->sc_otg.sc_clocks_arg = &sc->sc_otg; 268 269 sc->sc_otg.sc_ep_int_set = musbotg_ep_int_set; 270 271 /* initialise some bus fields */ 272 sc->sc_otg.sc_bus.parent = dev; 273 sc->sc_otg.sc_bus.devices = sc->sc_otg.sc_devices; 274 sc->sc_otg.sc_bus.devices_max = MUSB2_MAX_DEVICES; 275 sc->sc_otg.sc_bus.dma_bits = 32; 276 277 /* get all DMA memory */ 278 if (usb_bus_mem_alloc_all(&sc->sc_otg.sc_bus, 279 USB_GET_DMA_TAG(dev), NULL)) { 280 device_printf(dev, 281 "Failed allocate bus mem for musb\n"); 282 return (ENOMEM); 283 } 284 sc->sc_otg.sc_io_res = sc->sc_mem_res[RES_USBCORE]; 285 sc->sc_otg.sc_io_tag = 286 rman_get_bustag(sc->sc_otg.sc_io_res); 287 sc->sc_otg.sc_io_hdl = 288 rman_get_bushandle(sc->sc_otg.sc_io_res); 289 sc->sc_otg.sc_io_size = 290 rman_get_size(sc->sc_otg.sc_io_res); 291 292 sc->sc_otg.sc_bus.bdev = device_add_child(dev, "usbus", -1); 293 if (!(sc->sc_otg.sc_bus.bdev)) { 294 device_printf(dev, "No busdev for musb\n"); 295 goto error; 296 } 297 device_set_ivars(sc->sc_otg.sc_bus.bdev, 298 &sc->sc_otg.sc_bus); 299 300 err = bus_setup_intr(dev, sc->sc_otg.sc_irq_res, 301 INTR_TYPE_BIO | INTR_MPSAFE, 302 NULL, (driver_intr_t *)musbotg_wrapper_interrupt, 303 &sc->sc_otg, &sc->sc_otg.sc_intr_hdl); 304 if (err) { 305 sc->sc_otg.sc_intr_hdl = NULL; 306 device_printf(dev, 307 "Failed to setup interrupt for musb\n"); 308 goto error; 309 } 310 311 sc->sc_otg.sc_platform_data = sc; 312 if (OF_getprop(ofw_bus_get_node(dev), "dr_mode", mode, 313 sizeof(mode)) > 0) { 314 if (strcasecmp(mode, "host") == 0) 315 sc->sc_otg.sc_mode = MUSB2_HOST_MODE; 316 else 317 sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE; 318 } else { 319 /* Beaglebone defaults: USB0 device, USB1 HOST. */ 320 if (sc->sc_otg.sc_id == 0) 321 sc->sc_otg.sc_mode = MUSB2_DEVICE_MODE; 322 else 323 sc->sc_otg.sc_mode = MUSB2_HOST_MODE; 324 } 325 326 /* 327 * software-controlled function 328 */ 329 330 if (sc->sc_otg.sc_mode == MUSB2_HOST_MODE) { 331 reg = USBCTRL_READ4(sc, USBCTRL_MODE); 332 reg |= USBCTRL_MODE_IDDIGMUX; 333 reg &= ~USBCTRL_MODE_IDDIG; 334 USBCTRL_WRITE4(sc, USBCTRL_MODE, reg); 335 USBCTRL_WRITE4(sc, USBCTRL_UTMI, 336 USBCTRL_UTMI_FSDATAEXT); 337 } else { 338 reg = USBCTRL_READ4(sc, USBCTRL_MODE); 339 reg |= USBCTRL_MODE_IDDIGMUX; 340 reg |= USBCTRL_MODE_IDDIG; 341 USBCTRL_WRITE4(sc, USBCTRL_MODE, reg); 342 } 343 344 reg = USBCTRL_INTEN_USB_ALL & ~USBCTRL_INTEN_USB_SOF; 345 USBCTRL_WRITE4(sc, USBCTRL_INTEN_SET1, reg); 346 USBCTRL_WRITE4(sc, USBCTRL_INTEN_CLR0, 0xffffffff); 347 348 err = musbotg_init(&sc->sc_otg); 349 if (!err) 350 err = device_probe_and_attach(sc->sc_otg.sc_bus.bdev); 351 352 if (err) 353 goto error; 354 355 /* poll VBUS one time */ 356 musbotg_vbus_poll(sc); 357 358 return (0); 359 360error: 361 musbotg_detach(dev); 362 return (ENXIO); 363} 364 365static int 366musbotg_detach(device_t dev) 367{ 368 struct musbotg_super_softc *sc = device_get_softc(dev); 369 int err; 370 371 /* during module unload there are lots of children leftover */ 372 device_delete_children(dev); 373 374 if (sc->sc_otg.sc_irq_res && sc->sc_otg.sc_intr_hdl) { 375 /* 376 * only call musbotg_uninit() after musbotg_init() 377 */ 378 musbotg_uninit(&sc->sc_otg); 379 380 err = bus_teardown_intr(dev, sc->sc_otg.sc_irq_res, 381 sc->sc_otg.sc_intr_hdl); 382 sc->sc_otg.sc_intr_hdl = NULL; 383 } 384 385 usb_bus_mem_free_all(&sc->sc_otg.sc_bus, NULL); 386 387 /* Free resources if any */ 388 if (sc->sc_mem_res[0]) 389 bus_release_resources(dev, am335x_musbotg_mem_spec, 390 sc->sc_mem_res); 391 392 if (sc->sc_otg.sc_irq_res) 393 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 394 sc->sc_otg.sc_irq_res); 395 396 return (0); 397} 398 399static device_method_t musbotg_methods[] = { 400 /* Device interface */ 401 DEVMETHOD(device_probe, musbotg_probe), 402 DEVMETHOD(device_attach, musbotg_attach), 403 DEVMETHOD(device_detach, musbotg_detach), 404 DEVMETHOD(device_suspend, bus_generic_suspend), 405 DEVMETHOD(device_resume, bus_generic_resume), 406 DEVMETHOD(device_shutdown, bus_generic_shutdown), 407 408 DEVMETHOD_END 409}; 410 411static driver_t musbotg_driver = { 412 .name = "musbotg", 413 .methods = musbotg_methods, 414 .size = sizeof(struct musbotg_super_softc), 415}; 416 417static devclass_t musbotg_devclass; 418 419DRIVER_MODULE(musbotg, usbss, musbotg_driver, musbotg_devclass, 0, 0); 420MODULE_DEPEND(musbotg, usbss, 1, 1, 1); 421