am335x_lcd.c revision 277716
1/*- 2 * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/ti/am335x/am335x_lcd.c 277716 2015-01-25 22:08:36Z gonzo $"); 29 30#include "opt_syscons.h" 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/clock.h> 36#include <sys/time.h> 37#include <sys/bus.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/resource.h> 41#include <sys/rman.h> 42#include <sys/sysctl.h> 43#include <vm/vm.h> 44#include <vm/pmap.h> 45#include <sys/fbio.h> 46#include <sys/consio.h> 47 48#include <machine/bus.h> 49 50#include <dev/fdt/fdt_common.h> 51#include <dev/ofw/openfirm.h> 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54 55#include <dev/fb/fbreg.h> 56#ifdef DEV_SC 57#include <dev/syscons/syscons.h> 58#else /* VT */ 59#include <dev/vt/vt.h> 60#endif 61 62#include <arm/ti/ti_prcm.h> 63#include <arm/ti/ti_scm.h> 64 65#include "am335x_lcd.h" 66#include "am335x_pwm.h" 67 68#include "fb_if.h" 69 70#define LCD_PID 0x00 71#define LCD_CTRL 0x04 72#define CTRL_DIV_MASK 0xff 73#define CTRL_DIV_SHIFT 8 74#define CTRL_AUTO_UFLOW_RESTART (1 << 1) 75#define CTRL_RASTER_MODE 1 76#define CTRL_LIDD_MODE 0 77#define LCD_LIDD_CTRL 0x0C 78#define LCD_LIDD_CS0_CONF 0x10 79#define LCD_LIDD_CS0_ADDR 0x14 80#define LCD_LIDD_CS0_DATA 0x18 81#define LCD_LIDD_CS1_CONF 0x1C 82#define LCD_LIDD_CS1_ADDR 0x20 83#define LCD_LIDD_CS1_DATA 0x24 84#define LCD_RASTER_CTRL 0x28 85#define RASTER_CTRL_TFT24_UNPACKED (1 << 26) 86#define RASTER_CTRL_TFT24 (1 << 25) 87#define RASTER_CTRL_STN565 (1 << 24) 88#define RASTER_CTRL_TFTPMAP (1 << 23) 89#define RASTER_CTRL_NIBMODE (1 << 22) 90#define RASTER_CTRL_PALMODE_SHIFT 20 91#define PALETTE_PALETTE_AND_DATA 0x00 92#define PALETTE_PALETTE_ONLY 0x01 93#define PALETTE_DATA_ONLY 0x02 94#define RASTER_CTRL_REQDLY_SHIFT 12 95#define RASTER_CTRL_MONO8B (1 << 9) 96#define RASTER_CTRL_RBORDER (1 << 8) 97#define RASTER_CTRL_LCDTFT (1 << 7) 98#define RASTER_CTRL_LCDBW (1 << 1) 99#define RASTER_CTRL_LCDEN (1 << 0) 100#define LCD_RASTER_TIMING_0 0x2C 101#define RASTER_TIMING_0_HBP_SHIFT 24 102#define RASTER_TIMING_0_HFP_SHIFT 16 103#define RASTER_TIMING_0_HSW_SHIFT 10 104#define RASTER_TIMING_0_PPLLSB_SHIFT 4 105#define RASTER_TIMING_0_PPLMSB_SHIFT 3 106#define LCD_RASTER_TIMING_1 0x30 107#define RASTER_TIMING_1_VBP_SHIFT 24 108#define RASTER_TIMING_1_VFP_SHIFT 16 109#define RASTER_TIMING_1_VSW_SHIFT 10 110#define RASTER_TIMING_1_LPP_SHIFT 0 111#define LCD_RASTER_TIMING_2 0x34 112#define RASTER_TIMING_2_HSWHI_SHIFT 27 113#define RASTER_TIMING_2_LPP_B10_SHIFT 26 114#define RASTER_TIMING_2_PHSVS (1 << 25) 115#define RASTER_TIMING_2_PHSVS_RISE (1 << 24) 116#define RASTER_TIMING_2_PHSVS_FALL (0 << 24) 117#define RASTER_TIMING_2_IOE (1 << 23) 118#define RASTER_TIMING_2_IPC (1 << 22) 119#define RASTER_TIMING_2_IHS (1 << 21) 120#define RASTER_TIMING_2_IVS (1 << 20) 121#define RASTER_TIMING_2_ACBI_SHIFT 16 122#define RASTER_TIMING_2_ACB_SHIFT 8 123#define RASTER_TIMING_2_HBPHI_SHIFT 4 124#define RASTER_TIMING_2_HFPHI_SHIFT 0 125#define LCD_RASTER_SUBPANEL 0x38 126#define LCD_RASTER_SUBPANEL2 0x3C 127#define LCD_LCDDMA_CTRL 0x40 128#define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 129#define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 130#define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 131#define LCDDMA_CTRL_BYTES_SWAP (1 << 3) 132#define LCDDMA_CTRL_BE (1 << 1) 133#define LCDDMA_CTRL_FB0_ONLY 0 134#define LCDDMA_CTRL_FB0_FB1 (1 << 0) 135#define LCD_LCDDMA_FB0_BASE 0x44 136#define LCD_LCDDMA_FB0_CEILING 0x48 137#define LCD_LCDDMA_FB1_BASE 0x4C 138#define LCD_LCDDMA_FB1_CEILING 0x50 139#define LCD_SYSCONFIG 0x54 140#define SYSCONFIG_STANDBY_FORCE (0 << 4) 141#define SYSCONFIG_STANDBY_NONE (1 << 4) 142#define SYSCONFIG_STANDBY_SMART (2 << 4) 143#define SYSCONFIG_IDLE_FORCE (0 << 2) 144#define SYSCONFIG_IDLE_NONE (1 << 2) 145#define SYSCONFIG_IDLE_SMART (2 << 2) 146#define LCD_IRQSTATUS_RAW 0x58 147#define LCD_IRQSTATUS 0x5C 148#define LCD_IRQENABLE_SET 0x60 149#define LCD_IRQENABLE_CLEAR 0x64 150#define IRQ_EOF1 (1 << 9) 151#define IRQ_EOF0 (1 << 8) 152#define IRQ_PL (1 << 6) 153#define IRQ_FUF (1 << 5) 154#define IRQ_ACB (1 << 3) 155#define IRQ_SYNC_LOST (1 << 2) 156#define IRQ_RASTER_DONE (1 << 1) 157#define IRQ_FRAME_DONE (1 << 0) 158#define LCD_END_OF_INT_IND 0x68 159#define LCD_CLKC_ENABLE 0x6C 160#define CLKC_ENABLE_DMA (1 << 2) 161#define CLKC_ENABLE_LDID (1 << 1) 162#define CLKC_ENABLE_CORE (1 << 0) 163#define LCD_CLKC_RESET 0x70 164#define CLKC_RESET_MAIN (1 << 3) 165#define CLKC_RESET_DMA (1 << 2) 166#define CLKC_RESET_LDID (1 << 1) 167#define CLKC_RESET_CORE (1 << 0) 168 169#define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 170#define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 171#define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 172 device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) 173#define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 174 175#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); 176#define LCD_WRITE4(_sc, reg, value) \ 177 bus_write_4((_sc)->sc_mem_res, reg, value); 178 179 180/* Backlight is controlled by eCAS interface on PWM unit 0 */ 181#define PWM_UNIT 0 182#define PWM_PERIOD 100 183 184struct am335x_lcd_softc { 185 device_t sc_dev; 186 struct fb_info sc_fb_info; 187 struct resource *sc_mem_res; 188 struct resource *sc_irq_res; 189 void *sc_intr_hl; 190 struct mtx sc_mtx; 191 int sc_backlight; 192 struct sysctl_oid *sc_oid; 193 194 /* Framebuffer */ 195 bus_dma_tag_t sc_dma_tag; 196 bus_dmamap_t sc_dma_map; 197 size_t sc_fb_size; 198 bus_addr_t sc_fb_phys; 199 uint8_t *sc_fb_base; 200}; 201 202static void 203am335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 204{ 205 bus_addr_t *addr; 206 207 if (err) 208 return; 209 210 addr = (bus_addr_t*)arg; 211 *addr = segs[0].ds_addr; 212} 213 214static uint32_t 215am335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) 216{ 217 uint32_t div; 218 /* Raster mode case: divisors are in range from 2 to 255 */ 219 for (div = 2; div < 255; div++) 220 if (reference/div <= freq) 221 return (div); 222 223 return (255); 224} 225 226static int 227am335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) 228{ 229 struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; 230 int error; 231 int backlight; 232 233 backlight = sc->sc_backlight; 234 error = sysctl_handle_int(oidp, &backlight, 0, req); 235 236 if (error != 0 || req->newptr == NULL) 237 return (error); 238 239 if (backlight < 0) 240 backlight = 0; 241 if (backlight > 100) 242 backlight = 100; 243 244 LCD_LOCK(sc); 245 error = am335x_pwm_config_ecas(PWM_UNIT, PWM_PERIOD, 246 backlight*PWM_PERIOD/100); 247 if (error == 0) 248 sc->sc_backlight = backlight; 249 LCD_UNLOCK(sc); 250 251 return (error); 252} 253 254static int 255am335x_read_panel_property(device_t dev, const char *name, uint32_t *val) 256{ 257 phandle_t node; 258 pcell_t cell; 259 260 node = ofw_bus_get_node(dev); 261 if ((OF_getprop(node, name, &cell, sizeof(cell))) <= 0) { 262 device_printf(dev, "missing '%s' attribute in LCD panel info\n", 263 name); 264 return (ENXIO); 265 } 266 267 *val = fdt32_to_cpu(cell); 268 269 return (0); 270} 271 272static int 273am335x_read_panel_info(device_t dev, struct panel_info *panel) 274{ 275 int error; 276 277 error = 0; 278 if ((error = am335x_read_panel_property(dev, 279 "panel_width", &panel->panel_width))) 280 goto out; 281 282 if ((error = am335x_read_panel_property(dev, 283 "panel_height", &panel->panel_height))) 284 goto out; 285 286 if ((error = am335x_read_panel_property(dev, 287 "panel_hfp", &panel->panel_hfp))) 288 goto out; 289 290 if ((error = am335x_read_panel_property(dev, 291 "panel_hbp", &panel->panel_hbp))) 292 goto out; 293 294 if ((error = am335x_read_panel_property(dev, 295 "panel_hsw", &panel->panel_hsw))) 296 goto out; 297 298 if ((error = am335x_read_panel_property(dev, 299 "panel_vfp", &panel->panel_vfp))) 300 goto out; 301 302 if ((error = am335x_read_panel_property(dev, 303 "panel_vbp", &panel->panel_vbp))) 304 goto out; 305 306 if ((error = am335x_read_panel_property(dev, 307 "panel_vsw", &panel->panel_vsw))) 308 goto out; 309 310 if ((error = am335x_read_panel_property(dev, 311 "panel_pxl_clk", &panel->panel_pxl_clk))) 312 goto out; 313 314 if ((error = am335x_read_panel_property(dev, 315 "panel_invert_pxl_clk", &panel->panel_invert_pxl_clk))) 316 goto out; 317 318 if ((error = am335x_read_panel_property(dev, 319 "ac_bias", &panel->ac_bias))) 320 goto out; 321 322 if ((error = am335x_read_panel_property(dev, 323 "ac_bias_intrpt", &panel->ac_bias_intrpt))) 324 goto out; 325 326 if ((error = am335x_read_panel_property(dev, 327 "dma_burst_sz", &panel->dma_burst_sz))) 328 goto out; 329 330 if ((error = am335x_read_panel_property(dev, 331 "bpp", &panel->bpp))) 332 goto out; 333 334 if ((error = am335x_read_panel_property(dev, 335 "fdd", &panel->fdd))) 336 goto out; 337 338 if ((error = am335x_read_panel_property(dev, 339 "invert_line_clock", &panel->invert_line_clock))) 340 goto out; 341 342 if ((error = am335x_read_panel_property(dev, 343 "invert_frm_clock", &panel->invert_frm_clock))) 344 goto out; 345 346 if ((error = am335x_read_panel_property(dev, 347 "sync_edge", &panel->sync_edge))) 348 goto out; 349 350 error = am335x_read_panel_property(dev, 351 "sync_ctrl", &panel->sync_ctrl); 352 353out: 354 return (error); 355} 356 357static void 358am335x_lcd_intr(void *arg) 359{ 360 struct am335x_lcd_softc *sc = arg; 361 uint32_t reg; 362 363 reg = LCD_READ4(sc, LCD_IRQSTATUS); 364 LCD_WRITE4(sc, LCD_IRQSTATUS, reg); 365 /* Read value back to make sure it reached the hardware */ 366 reg = LCD_READ4(sc, LCD_IRQSTATUS); 367 368 if (reg & IRQ_SYNC_LOST) { 369 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 370 reg &= ~RASTER_CTRL_LCDEN; 371 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 372 373 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 374 reg |= RASTER_CTRL_LCDEN; 375 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 376 goto done; 377 } 378 379 if (reg & IRQ_PL) { 380 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 381 reg &= ~RASTER_CTRL_LCDEN; 382 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 383 384 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 385 reg |= RASTER_CTRL_LCDEN; 386 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 387 goto done; 388 } 389 390 if (reg & IRQ_EOF0) { 391 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 392 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 393 reg &= ~IRQ_EOF0; 394 } 395 396 if (reg & IRQ_EOF1) { 397 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 398 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 399 reg &= ~IRQ_EOF1; 400 } 401 402 if (reg & IRQ_FUF) { 403 /* TODO: Handle FUF */ 404 } 405 406 if (reg & IRQ_ACB) { 407 /* TODO: Handle ACB */ 408 } 409 410done: 411 LCD_WRITE4(sc, LCD_END_OF_INT_IND, 0); 412 /* Read value back to make sure it reached the hardware */ 413 reg = LCD_READ4(sc, LCD_END_OF_INT_IND); 414} 415 416static int 417am335x_lcd_probe(device_t dev) 418{ 419#ifdef DEV_SC 420 int err; 421#endif 422 423 if (!ofw_bus_status_okay(dev)) 424 return (ENXIO); 425 426 if (!ofw_bus_is_compatible(dev, "ti,am335x-lcd")) 427 return (ENXIO); 428 429 device_set_desc(dev, "AM335x LCD controller"); 430 431#ifdef DEV_SC 432 err = sc_probe_unit(device_get_unit(dev), 433 device_get_flags(dev) | SC_AUTODETECT_KBD); 434 if (err != 0) 435 return (err); 436#endif 437 438 return (BUS_PROBE_DEFAULT); 439} 440 441static int 442am335x_lcd_attach(device_t dev) 443{ 444 struct am335x_lcd_softc *sc; 445 int rid; 446 int div; 447 struct panel_info panel; 448 uint32_t reg, timing0, timing1, timing2; 449 struct sysctl_ctx_list *ctx; 450 struct sysctl_oid *tree; 451 uint32_t burst_log; 452 int err; 453 size_t dma_size; 454 uint32_t hbp, hfp, hsw; 455 uint32_t vbp, vfp, vsw; 456 uint32_t width, height; 457 458 sc = device_get_softc(dev); 459 sc->sc_dev = dev; 460 461 if (am335x_read_panel_info(dev, &panel)) 462 return (ENXIO); 463 464 int ref_freq = 0; 465 ti_prcm_clk_enable(LCDC_CLK); 466 if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { 467 device_printf(dev, "Can't get reference frequency\n"); 468 return (ENXIO); 469 } 470 471 rid = 0; 472 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 473 RF_ACTIVE); 474 if (!sc->sc_mem_res) { 475 device_printf(dev, "cannot allocate memory window\n"); 476 return (ENXIO); 477 } 478 479 rid = 0; 480 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 481 RF_ACTIVE); 482 if (!sc->sc_irq_res) { 483 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 484 device_printf(dev, "cannot allocate interrupt\n"); 485 return (ENXIO); 486 } 487 488 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 489 NULL, am335x_lcd_intr, sc, 490 &sc->sc_intr_hl) != 0) { 491 bus_release_resource(dev, SYS_RES_IRQ, rid, 492 sc->sc_irq_res); 493 bus_release_resource(dev, SYS_RES_MEMORY, rid, 494 sc->sc_mem_res); 495 device_printf(dev, "Unable to setup the irq handler.\n"); 496 return (ENXIO); 497 } 498 499 LCD_LOCK_INIT(sc); 500 501 /* Panle initialization */ 502 dma_size = round_page(panel.panel_width*panel.panel_height*panel.bpp/8); 503 504 /* 505 * Now allocate framebuffer memory 506 */ 507 err = bus_dma_tag_create( 508 bus_get_dma_tag(dev), 509 4, 0, /* alignment, boundary */ 510 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 511 BUS_SPACE_MAXADDR, /* highaddr */ 512 NULL, NULL, /* filter, filterarg */ 513 dma_size, 1, /* maxsize, nsegments */ 514 dma_size, 0, /* maxsegsize, flags */ 515 NULL, NULL, /* lockfunc, lockarg */ 516 &sc->sc_dma_tag); 517 if (err) 518 goto fail; 519 520 err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 521 BUS_DMA_COHERENT, &sc->sc_dma_map); 522 523 if (err) { 524 device_printf(dev, "cannot allocate framebuffer\n"); 525 goto fail; 526 } 527 528 err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 529 dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 530 531 if (err) { 532 device_printf(dev, "cannot load DMA map\n"); 533 goto fail; 534 } 535 536 /* Make sure it's blank */ 537 memset(sc->sc_fb_base, 0x00, dma_size); 538 539 /* Calculate actual FB Size */ 540 sc->sc_fb_size = panel.panel_width*panel.panel_height*panel.bpp/8; 541 542 /* Only raster mode is supported */ 543 reg = CTRL_RASTER_MODE; 544 div = am335x_lcd_calc_divisor(ref_freq, panel.panel_pxl_clk); 545 reg |= (div << CTRL_DIV_SHIFT); 546 LCD_WRITE4(sc, LCD_CTRL, reg); 547 548 /* Set timing */ 549 timing0 = timing1 = timing2 = 0; 550 551 hbp = panel.panel_hbp - 1; 552 hfp = panel.panel_hfp - 1; 553 hsw = panel.panel_hsw - 1; 554 555 vbp = panel.panel_vbp; 556 vfp = panel.panel_vfp; 557 vsw = panel.panel_vsw - 1; 558 559 height = panel.panel_height - 1; 560 width = panel.panel_width - 1; 561 562 /* Horizontal back porch */ 563 timing0 |= (hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; 564 timing2 |= ((hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; 565 /* Horizontal front porch */ 566 timing0 |= (hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; 567 timing2 |= ((hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; 568 /* Horizontal sync width */ 569 timing0 |= (hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; 570 timing2 |= ((hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; 571 572 /* Vertical back porch, front porch, sync width */ 573 timing1 |= (vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; 574 timing1 |= (vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; 575 timing1 |= (vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; 576 577 /* Pixels per line */ 578 timing0 |= ((width >> 10) & 1) 579 << RASTER_TIMING_0_PPLMSB_SHIFT; 580 timing0 |= ((width >> 4) & 0x3f) 581 << RASTER_TIMING_0_PPLLSB_SHIFT; 582 583 /* Lines per panel */ 584 timing1 |= (height & 0x3ff) 585 << RASTER_TIMING_1_LPP_SHIFT; 586 timing2 |= ((height >> 10 ) & 1) 587 << RASTER_TIMING_2_LPP_B10_SHIFT; 588 589 /* clock signal settings */ 590 if (panel.sync_ctrl) 591 timing2 |= RASTER_TIMING_2_PHSVS; 592 if (panel.sync_edge) 593 timing2 |= RASTER_TIMING_2_PHSVS_RISE; 594 else 595 timing2 |= RASTER_TIMING_2_PHSVS_FALL; 596 if (panel.invert_line_clock) 597 timing2 |= RASTER_TIMING_2_IHS; 598 if (panel.invert_frm_clock) 599 timing2 |= RASTER_TIMING_2_IVS; 600 if (panel.panel_invert_pxl_clk) 601 timing2 |= RASTER_TIMING_2_IPC; 602 603 /* AC bias */ 604 timing2 |= (panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); 605 timing2 |= (panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); 606 607 LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); 608 LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); 609 LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); 610 611 /* DMA settings */ 612 reg = LCDDMA_CTRL_FB0_FB1; 613 /* Find power of 2 for current burst size */ 614 switch (panel.dma_burst_sz) { 615 case 1: 616 burst_log = 0; 617 break; 618 case 2: 619 burst_log = 1; 620 break; 621 case 4: 622 burst_log = 2; 623 break; 624 case 8: 625 burst_log = 3; 626 break; 627 case 16: 628 default: 629 burst_log = 4; 630 break; 631 } 632 reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); 633 /* XXX: FIFO TH */ 634 reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); 635 LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); 636 637 LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 638 LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 639 LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 640 LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 641 642 /* Enable LCD */ 643 reg = RASTER_CTRL_LCDTFT; 644 reg |= (panel.fdd << RASTER_CTRL_REQDLY_SHIFT); 645 reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); 646 if (panel.bpp >= 24) 647 reg |= RASTER_CTRL_TFT24; 648 if (panel.bpp == 32) 649 reg |= RASTER_CTRL_TFT24_UNPACKED; 650 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 651 652 LCD_WRITE4(sc, LCD_CLKC_ENABLE, 653 CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); 654 655 LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); 656 DELAY(100); 657 LCD_WRITE4(sc, LCD_CLKC_RESET, 0); 658 659 reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | 660 IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | 661 IRQ_FRAME_DONE; 662 LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); 663 664 reg = LCD_READ4(sc, LCD_RASTER_CTRL); 665 reg |= RASTER_CTRL_LCDEN; 666 LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 667 668 LCD_WRITE4(sc, LCD_SYSCONFIG, 669 SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); 670 671 /* Init backlight interface */ 672 ctx = device_get_sysctl_ctx(sc->sc_dev); 673 tree = device_get_sysctl_tree(sc->sc_dev); 674 sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 675 "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 676 am335x_lcd_sysctl_backlight, "I", "LCD backlight"); 677 sc->sc_backlight = 0; 678 /* Check if eCAS interface is available at this point */ 679 if (am335x_pwm_config_ecas(PWM_UNIT, 680 PWM_PERIOD, PWM_PERIOD) == 0) 681 sc->sc_backlight = 100; 682 683 sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); 684 sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; 685 sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; 686 sc->sc_fb_info.fb_size = sc->sc_fb_size; 687 sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = panel.bpp; 688 sc->sc_fb_info.fb_stride = panel.panel_width*panel.bpp / 8; 689 sc->sc_fb_info.fb_width = panel.panel_width; 690 sc->sc_fb_info.fb_height = panel.panel_height; 691 692#ifdef DEV_SC 693 err = (sc_attach_unit(device_get_unit(dev), 694 device_get_flags(dev) | SC_AUTODETECT_KBD)); 695 696 if (err) { 697 device_printf(dev, "failed to attach syscons\n"); 698 goto fail; 699 } 700 701 am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); 702#else /* VT */ 703 device_t fbd = device_add_child(dev, "fbd", 704 device_get_unit(dev)); 705 if (fbd == NULL) { 706 device_printf(dev, "Failed to add fbd child\n"); 707 goto fail; 708 } 709 if (device_probe_and_attach(fbd) != 0) { 710 device_printf(dev, "Failed to attach fbd device\n"); 711 goto fail; 712 } 713#endif 714 715 return (0); 716 717fail: 718 return (err); 719} 720 721static int 722am335x_lcd_detach(device_t dev) 723{ 724 /* Do not let unload driver */ 725 return (EBUSY); 726} 727 728static struct fb_info * 729am335x_lcd_fb_getinfo(device_t dev) 730{ 731 struct am335x_lcd_softc *sc; 732 733 sc = device_get_softc(dev); 734 735 return (&sc->sc_fb_info); 736} 737 738static device_method_t am335x_lcd_methods[] = { 739 DEVMETHOD(device_probe, am335x_lcd_probe), 740 DEVMETHOD(device_attach, am335x_lcd_attach), 741 DEVMETHOD(device_detach, am335x_lcd_detach), 742 743 /* Framebuffer service methods */ 744 DEVMETHOD(fb_getinfo, am335x_lcd_fb_getinfo), 745 746 DEVMETHOD_END 747}; 748 749static driver_t am335x_lcd_driver = { 750 "fb", 751 am335x_lcd_methods, 752 sizeof(struct am335x_lcd_softc), 753}; 754 755static devclass_t am335x_lcd_devclass; 756 757DRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); 758MODULE_VERSION(am335x_lcd, 1); 759MODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); 760