am335x_lcd.c revision 267171
1251018Sgonzo/*- 2251018Sgonzo * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3251018Sgonzo * All rights reserved. 4251018Sgonzo * 5251018Sgonzo * Redistribution and use in source and binary forms, with or without 6251018Sgonzo * modification, are permitted provided that the following conditions 7251018Sgonzo * are met: 8251018Sgonzo * 1. Redistributions of source code must retain the above copyright 9251018Sgonzo * notice, this list of conditions and the following disclaimer. 10251018Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11251018Sgonzo * notice, this list of conditions and the following disclaimer in the 12251018Sgonzo * documentation and/or other materials provided with the distribution. 13251018Sgonzo * 14251018Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15251018Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16251018Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17251018Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18251018Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19251018Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20251018Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21251018Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22251018Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23251018Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24251018Sgonzo * SUCH DAMAGE. 25251018Sgonzo */ 26251018Sgonzo 27251018Sgonzo#include <sys/cdefs.h> 28251018Sgonzo__FBSDID("$FreeBSD: head/sys/arm/ti/am335x/am335x_lcd.c 267171 2014-06-06 16:37:42Z kevlo $"); 29251018Sgonzo 30251018Sgonzo#include <sys/param.h> 31251018Sgonzo#include <sys/systm.h> 32251018Sgonzo#include <sys/kernel.h> 33251018Sgonzo#include <sys/module.h> 34251018Sgonzo#include <sys/clock.h> 35251018Sgonzo#include <sys/time.h> 36251018Sgonzo#include <sys/bus.h> 37251018Sgonzo#include <sys/lock.h> 38251018Sgonzo#include <sys/mutex.h> 39251018Sgonzo#include <sys/resource.h> 40251018Sgonzo#include <sys/rman.h> 41251018Sgonzo#include <sys/sysctl.h> 42251018Sgonzo#include <vm/vm.h> 43251018Sgonzo#include <vm/pmap.h> 44251018Sgonzo 45252282Sgonzo/* syscons bits */ 46252282Sgonzo#include <sys/fbio.h> 47252282Sgonzo#include <sys/consio.h> 48252282Sgonzo 49251018Sgonzo#include <machine/bus.h> 50251018Sgonzo 51251018Sgonzo#include <dev/fdt/fdt_common.h> 52251018Sgonzo#include <dev/ofw/openfirm.h> 53251018Sgonzo#include <dev/ofw/ofw_bus.h> 54251018Sgonzo#include <dev/ofw/ofw_bus_subr.h> 55251018Sgonzo 56252282Sgonzo#include <dev/fb/fbreg.h> 57252282Sgonzo#include <dev/syscons/syscons.h> 58252282Sgonzo 59251018Sgonzo#include <arm/ti/ti_prcm.h> 60251018Sgonzo#include <arm/ti/ti_scm.h> 61251018Sgonzo 62251018Sgonzo#include "am335x_lcd.h" 63251018Sgonzo#include "am335x_pwm.h" 64251018Sgonzo 65251018Sgonzo#define LCD_PID 0x00 66251018Sgonzo#define LCD_CTRL 0x04 67251018Sgonzo#define CTRL_DIV_MASK 0xff 68251018Sgonzo#define CTRL_DIV_SHIFT 8 69251018Sgonzo#define CTRL_AUTO_UFLOW_RESTART (1 << 1) 70251018Sgonzo#define CTRL_RASTER_MODE 1 71251018Sgonzo#define CTRL_LIDD_MODE 0 72251018Sgonzo#define LCD_LIDD_CTRL 0x0C 73251018Sgonzo#define LCD_LIDD_CS0_CONF 0x10 74251018Sgonzo#define LCD_LIDD_CS0_ADDR 0x14 75251018Sgonzo#define LCD_LIDD_CS0_DATA 0x18 76251018Sgonzo#define LCD_LIDD_CS1_CONF 0x1C 77251018Sgonzo#define LCD_LIDD_CS1_ADDR 0x20 78251018Sgonzo#define LCD_LIDD_CS1_DATA 0x24 79251018Sgonzo#define LCD_RASTER_CTRL 0x28 80251018Sgonzo#define RASTER_CTRL_TFT24_UNPACKED (1 << 26) 81251018Sgonzo#define RASTER_CTRL_TFT24 (1 << 25) 82251018Sgonzo#define RASTER_CTRL_STN565 (1 << 24) 83251018Sgonzo#define RASTER_CTRL_TFTPMAP (1 << 23) 84251018Sgonzo#define RASTER_CTRL_NIBMODE (1 << 22) 85251018Sgonzo#define RASTER_CTRL_PALMODE_SHIFT 20 86251018Sgonzo#define PALETTE_PALETTE_AND_DATA 0x00 87251018Sgonzo#define PALETTE_PALETTE_ONLY 0x01 88251018Sgonzo#define PALETTE_DATA_ONLY 0x02 89251018Sgonzo#define RASTER_CTRL_REQDLY_SHIFT 12 90251018Sgonzo#define RASTER_CTRL_MONO8B (1 << 9) 91251018Sgonzo#define RASTER_CTRL_RBORDER (1 << 8) 92251018Sgonzo#define RASTER_CTRL_LCDTFT (1 << 7) 93251018Sgonzo#define RASTER_CTRL_LCDBW (1 << 1) 94251018Sgonzo#define RASTER_CTRL_LCDEN (1 << 0) 95251018Sgonzo#define LCD_RASTER_TIMING_0 0x2C 96251018Sgonzo#define RASTER_TIMING_0_HBP_SHIFT 24 97251018Sgonzo#define RASTER_TIMING_0_HFP_SHIFT 16 98251018Sgonzo#define RASTER_TIMING_0_HSW_SHIFT 10 99251018Sgonzo#define RASTER_TIMING_0_PPLLSB_SHIFT 4 100251018Sgonzo#define RASTER_TIMING_0_PPLMSB_SHIFT 3 101251018Sgonzo#define LCD_RASTER_TIMING_1 0x30 102251018Sgonzo#define RASTER_TIMING_1_VBP_SHIFT 24 103251018Sgonzo#define RASTER_TIMING_1_VFP_SHIFT 16 104251018Sgonzo#define RASTER_TIMING_1_VSW_SHIFT 10 105251018Sgonzo#define RASTER_TIMING_1_LPP_SHIFT 0 106251018Sgonzo#define LCD_RASTER_TIMING_2 0x34 107251018Sgonzo#define RASTER_TIMING_2_HSWHI_SHIFT 27 108251018Sgonzo#define RASTER_TIMING_2_LPP_B10_SHIFT 26 109251018Sgonzo#define RASTER_TIMING_2_PHSVS (1 << 25) 110251018Sgonzo#define RASTER_TIMING_2_PHSVS_RISE (1 << 24) 111251018Sgonzo#define RASTER_TIMING_2_PHSVS_FALL (0 << 24) 112251018Sgonzo#define RASTER_TIMING_2_IOE (1 << 23) 113251018Sgonzo#define RASTER_TIMING_2_IPC (1 << 22) 114251018Sgonzo#define RASTER_TIMING_2_IHS (1 << 21) 115251018Sgonzo#define RASTER_TIMING_2_IVS (1 << 20) 116251018Sgonzo#define RASTER_TIMING_2_ACBI_SHIFT 16 117251018Sgonzo#define RASTER_TIMING_2_ACB_SHIFT 8 118251018Sgonzo#define RASTER_TIMING_2_HBPHI_SHIFT 4 119251018Sgonzo#define RASTER_TIMING_2_HFPHI_SHIFT 0 120251018Sgonzo#define LCD_RASTER_SUBPANEL 0x38 121251018Sgonzo#define LCD_RASTER_SUBPANEL2 0x3C 122251018Sgonzo#define LCD_LCDDMA_CTRL 0x40 123251018Sgonzo#define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 124251018Sgonzo#define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 125251018Sgonzo#define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 126251018Sgonzo#define LCDDMA_CTRL_BYTES_SWAP (1 << 3) 127251018Sgonzo#define LCDDMA_CTRL_BE (1 << 1) 128251018Sgonzo#define LCDDMA_CTRL_FB0_ONLY 0 129251018Sgonzo#define LCDDMA_CTRL_FB0_FB1 (1 << 0) 130251018Sgonzo#define LCD_LCDDMA_FB0_BASE 0x44 131251018Sgonzo#define LCD_LCDDMA_FB0_CEILING 0x48 132251018Sgonzo#define LCD_LCDDMA_FB1_BASE 0x4C 133251018Sgonzo#define LCD_LCDDMA_FB1_CEILING 0x50 134251018Sgonzo#define LCD_SYSCONFIG 0x54 135251018Sgonzo#define SYSCONFIG_STANDBY_FORCE (0 << 4) 136251018Sgonzo#define SYSCONFIG_STANDBY_NONE (1 << 4) 137251018Sgonzo#define SYSCONFIG_STANDBY_SMART (2 << 4) 138251018Sgonzo#define SYSCONFIG_IDLE_FORCE (0 << 2) 139251018Sgonzo#define SYSCONFIG_IDLE_NONE (1 << 2) 140251018Sgonzo#define SYSCONFIG_IDLE_SMART (2 << 2) 141251018Sgonzo#define LCD_IRQSTATUS_RAW 0x58 142251018Sgonzo#define LCD_IRQSTATUS 0x5C 143251018Sgonzo#define LCD_IRQENABLE_SET 0x60 144251018Sgonzo#define LCD_IRQENABLE_CLEAR 0x64 145251018Sgonzo#define IRQ_EOF1 (1 << 9) 146251018Sgonzo#define IRQ_EOF0 (1 << 8) 147251018Sgonzo#define IRQ_PL (1 << 6) 148251018Sgonzo#define IRQ_FUF (1 << 5) 149251018Sgonzo#define IRQ_ACB (1 << 3) 150251018Sgonzo#define IRQ_SYNC_LOST (1 << 2) 151251018Sgonzo#define IRQ_RASTER_DONE (1 << 1) 152251018Sgonzo#define IRQ_FRAME_DONE (1 << 0) 153251018Sgonzo#define LCD_CLKC_ENABLE 0x6C 154251018Sgonzo#define CLKC_ENABLE_DMA (1 << 2) 155251018Sgonzo#define CLKC_ENABLE_LDID (1 << 1) 156251018Sgonzo#define CLKC_ENABLE_CORE (1 << 0) 157251018Sgonzo#define LCD_CLKC_RESET 0x70 158251018Sgonzo#define CLKC_RESET_MAIN (1 << 3) 159251018Sgonzo#define CLKC_RESET_DMA (1 << 2) 160251018Sgonzo#define CLKC_RESET_LDID (1 << 1) 161251018Sgonzo#define CLKC_RESET_CORE (1 << 0) 162251018Sgonzo 163251018Sgonzo#define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 164251018Sgonzo#define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 165251018Sgonzo#define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 166251018Sgonzo device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) 167251018Sgonzo#define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 168251018Sgonzo 169251018Sgonzo#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); 170251018Sgonzo#define LCD_WRITE4(_sc, reg, value) \ 171251018Sgonzo bus_write_4((_sc)->sc_mem_res, reg, value); 172251018Sgonzo 173251018Sgonzo 174251018Sgonzo/* Backlight is controlled by eCAS interface on PWM unit 0 */ 175251018Sgonzo#define PWM_UNIT 0 176251018Sgonzo#define PWM_PERIOD 100 177251018Sgonzo 178251018Sgonzostruct am335x_lcd_softc { 179251018Sgonzo device_t sc_dev; 180251018Sgonzo struct resource *sc_mem_res; 181251018Sgonzo struct resource *sc_irq_res; 182251018Sgonzo void *sc_intr_hl; 183251018Sgonzo struct mtx sc_mtx; 184251018Sgonzo int sc_backlight; 185251018Sgonzo struct sysctl_oid *sc_oid; 186251018Sgonzo 187251018Sgonzo /* Framebuffer */ 188251018Sgonzo bus_dma_tag_t sc_dma_tag; 189251018Sgonzo bus_dmamap_t sc_dma_map; 190251018Sgonzo size_t sc_fb_size; 191251018Sgonzo bus_addr_t sc_fb_phys; 192251018Sgonzo uint8_t *sc_fb_base; 193251018Sgonzo}; 194251018Sgonzo 195251018Sgonzostatic void 196251018Sgonzoam335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 197251018Sgonzo{ 198251018Sgonzo bus_addr_t *addr; 199251018Sgonzo 200251018Sgonzo if (err) 201251018Sgonzo return; 202251018Sgonzo 203251018Sgonzo addr = (bus_addr_t*)arg; 204251018Sgonzo *addr = segs[0].ds_addr; 205251018Sgonzo} 206251018Sgonzo 207251018Sgonzostatic uint32_t 208251018Sgonzoam335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) 209251018Sgonzo{ 210251018Sgonzo uint32_t div; 211251018Sgonzo /* Raster mode case: divisors are in range from 2 to 255 */ 212251018Sgonzo for (div = 2; div < 255; div++) 213251018Sgonzo if (reference/div <= freq) 214251018Sgonzo return (div); 215251018Sgonzo 216251018Sgonzo return (255); 217251018Sgonzo} 218251018Sgonzo 219251018Sgonzostatic int 220251018Sgonzoam335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) 221251018Sgonzo{ 222251018Sgonzo struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; 223251018Sgonzo int error; 224251018Sgonzo int backlight; 225251018Sgonzo 226267171Skevlo backlight = sc->sc_backlight; 227251018Sgonzo error = sysctl_handle_int(oidp, &backlight, 0, req); 228251018Sgonzo 229251018Sgonzo if (error != 0 || req->newptr == NULL) 230251018Sgonzo return (error); 231251018Sgonzo 232251018Sgonzo if (backlight < 0) 233251018Sgonzo backlight = 0; 234251018Sgonzo if (backlight > 100) 235251018Sgonzo backlight = 100; 236251018Sgonzo 237251018Sgonzo LCD_LOCK(sc); 238251018Sgonzo error = am335x_pwm_config_ecas(PWM_UNIT, PWM_PERIOD, 239251018Sgonzo backlight*PWM_PERIOD/100); 240251018Sgonzo if (error == 0) 241251018Sgonzo sc->sc_backlight = backlight; 242251018Sgonzo LCD_UNLOCK(sc); 243251018Sgonzo 244251018Sgonzo return (error); 245251018Sgonzo} 246251018Sgonzo 247251018Sgonzostatic int 248251018Sgonzoam335x_read_panel_property(device_t dev, const char *name, uint32_t *val) 249251018Sgonzo{ 250251018Sgonzo phandle_t node; 251251018Sgonzo pcell_t cell; 252251018Sgonzo 253251018Sgonzo node = ofw_bus_get_node(dev); 254251018Sgonzo if ((OF_getprop(node, name, &cell, sizeof(cell))) <= 0) { 255251018Sgonzo device_printf(dev, "missing '%s' attribute in LCD panel info\n", 256251018Sgonzo name); 257251018Sgonzo return (ENXIO); 258251018Sgonzo } 259251018Sgonzo 260251018Sgonzo *val = fdt32_to_cpu(cell); 261251018Sgonzo 262251018Sgonzo return (0); 263251018Sgonzo} 264251018Sgonzo 265251018Sgonzostatic int 266251018Sgonzoam335x_read_panel_info(device_t dev, struct panel_info *panel) 267251018Sgonzo{ 268251018Sgonzo int error; 269251018Sgonzo 270251018Sgonzo error = 0; 271251018Sgonzo if ((error = am335x_read_panel_property(dev, 272251018Sgonzo "panel_width", &panel->panel_width))) 273251018Sgonzo goto out; 274251018Sgonzo 275251018Sgonzo if ((error = am335x_read_panel_property(dev, 276251018Sgonzo "panel_height", &panel->panel_height))) 277251018Sgonzo goto out; 278251018Sgonzo 279251018Sgonzo if ((error = am335x_read_panel_property(dev, 280251018Sgonzo "panel_hfp", &panel->panel_hfp))) 281251018Sgonzo goto out; 282251018Sgonzo 283251018Sgonzo if ((error = am335x_read_panel_property(dev, 284251018Sgonzo "panel_hbp", &panel->panel_hbp))) 285251018Sgonzo goto out; 286251018Sgonzo 287251018Sgonzo if ((error = am335x_read_panel_property(dev, 288251018Sgonzo "panel_hsw", &panel->panel_hsw))) 289251018Sgonzo goto out; 290251018Sgonzo 291251018Sgonzo if ((error = am335x_read_panel_property(dev, 292251018Sgonzo "panel_vfp", &panel->panel_vfp))) 293251018Sgonzo goto out; 294251018Sgonzo 295251018Sgonzo if ((error = am335x_read_panel_property(dev, 296251018Sgonzo "panel_vbp", &panel->panel_vbp))) 297251018Sgonzo goto out; 298251018Sgonzo 299251018Sgonzo if ((error = am335x_read_panel_property(dev, 300251018Sgonzo "panel_vsw", &panel->panel_vsw))) 301251018Sgonzo goto out; 302251018Sgonzo 303251018Sgonzo if ((error = am335x_read_panel_property(dev, 304251018Sgonzo "panel_pxl_clk", &panel->panel_pxl_clk))) 305251018Sgonzo goto out; 306251018Sgonzo 307251018Sgonzo if ((error = am335x_read_panel_property(dev, 308251018Sgonzo "panel_invert_pxl_clk", &panel->panel_invert_pxl_clk))) 309251018Sgonzo goto out; 310251018Sgonzo 311251018Sgonzo if ((error = am335x_read_panel_property(dev, 312251018Sgonzo "ac_bias", &panel->ac_bias))) 313251018Sgonzo goto out; 314251018Sgonzo 315251018Sgonzo if ((error = am335x_read_panel_property(dev, 316251018Sgonzo "ac_bias_intrpt", &panel->ac_bias_intrpt))) 317251018Sgonzo goto out; 318251018Sgonzo 319251018Sgonzo if ((error = am335x_read_panel_property(dev, 320251018Sgonzo "dma_burst_sz", &panel->dma_burst_sz))) 321251018Sgonzo goto out; 322251018Sgonzo 323251018Sgonzo if ((error = am335x_read_panel_property(dev, 324251018Sgonzo "bpp", &panel->bpp))) 325251018Sgonzo goto out; 326251018Sgonzo 327251018Sgonzo if ((error = am335x_read_panel_property(dev, 328251018Sgonzo "fdd", &panel->fdd))) 329251018Sgonzo goto out; 330251018Sgonzo 331251018Sgonzo if ((error = am335x_read_panel_property(dev, 332251018Sgonzo "invert_line_clock", &panel->invert_line_clock))) 333251018Sgonzo goto out; 334251018Sgonzo 335251018Sgonzo if ((error = am335x_read_panel_property(dev, 336251018Sgonzo "invert_frm_clock", &panel->invert_frm_clock))) 337251018Sgonzo goto out; 338251018Sgonzo 339251018Sgonzo if ((error = am335x_read_panel_property(dev, 340251018Sgonzo "sync_edge", &panel->sync_edge))) 341251018Sgonzo goto out; 342251018Sgonzo 343251018Sgonzo error = am335x_read_panel_property(dev, 344251018Sgonzo "sync_ctrl", &panel->sync_ctrl); 345251018Sgonzo 346251018Sgonzoout: 347251018Sgonzo return (error); 348251018Sgonzo} 349251018Sgonzo 350251018Sgonzostatic void 351251018Sgonzoam335x_lcd_intr(void *arg) 352251018Sgonzo{ 353251018Sgonzo struct am335x_lcd_softc *sc = arg; 354251018Sgonzo uint32_t reg; 355251018Sgonzo 356251018Sgonzo reg = LCD_READ4(sc, LCD_IRQSTATUS); 357251018Sgonzo LCD_WRITE4(sc, LCD_IRQSTATUS, reg); 358251018Sgonzo 359251018Sgonzo if (reg & IRQ_SYNC_LOST) { 360251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 361251018Sgonzo reg &= ~RASTER_CTRL_LCDEN; 362251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 363251018Sgonzo 364251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 365251018Sgonzo reg |= RASTER_CTRL_LCDEN; 366251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 367251018Sgonzo return; 368251018Sgonzo } 369251018Sgonzo 370251018Sgonzo if (reg & IRQ_PL) { 371251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 372251018Sgonzo reg &= ~RASTER_CTRL_LCDEN; 373251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 374251018Sgonzo 375251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 376251018Sgonzo reg |= RASTER_CTRL_LCDEN; 377251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 378251018Sgonzo return; 379251018Sgonzo } 380251018Sgonzo 381251018Sgonzo if (reg & IRQ_EOF0) { 382251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 383251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 384251018Sgonzo reg &= ~IRQ_EOF0; 385251018Sgonzo } 386251018Sgonzo 387251018Sgonzo if (reg & IRQ_EOF1) { 388251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 389251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 390251018Sgonzo reg &= ~IRQ_EOF1; 391251018Sgonzo } 392251018Sgonzo 393251018Sgonzo if (reg & IRQ_FUF) { 394251018Sgonzo /* TODO: Handle FUF */ 395251018Sgonzo } 396251018Sgonzo 397251018Sgonzo if (reg & IRQ_ACB) { 398251018Sgonzo /* TODO: Handle ACB */ 399251018Sgonzo } 400251018Sgonzo} 401251018Sgonzo 402251018Sgonzostatic int 403251018Sgonzoam335x_lcd_probe(device_t dev) 404251018Sgonzo{ 405252282Sgonzo int err; 406252282Sgonzo 407261410Sian if (!ofw_bus_status_okay(dev)) 408261410Sian return (ENXIO); 409261410Sian 410251018Sgonzo if (!ofw_bus_is_compatible(dev, "ti,am335x-lcd")) 411251018Sgonzo return (ENXIO); 412251018Sgonzo 413251018Sgonzo device_set_desc(dev, "AM335x LCD controller"); 414251018Sgonzo 415252282Sgonzo err = sc_probe_unit(device_get_unit(dev), 416252282Sgonzo device_get_flags(dev) | SC_AUTODETECT_KBD); 417252282Sgonzo if (err != 0) 418252282Sgonzo return (err); 419252282Sgonzo 420252282Sgonzo return (BUS_PROBE_DEFAULT); 421251018Sgonzo} 422251018Sgonzo 423251018Sgonzostatic int 424251018Sgonzoam335x_lcd_attach(device_t dev) 425251018Sgonzo{ 426251018Sgonzo struct am335x_lcd_softc *sc; 427251018Sgonzo int rid; 428251018Sgonzo int div; 429251018Sgonzo struct panel_info panel; 430251018Sgonzo uint32_t reg, timing0, timing1, timing2; 431251018Sgonzo struct sysctl_ctx_list *ctx; 432251018Sgonzo struct sysctl_oid *tree; 433251018Sgonzo uint32_t burst_log; 434251018Sgonzo int err; 435251018Sgonzo size_t dma_size; 436251018Sgonzo 437251018Sgonzo sc = device_get_softc(dev); 438251018Sgonzo sc->sc_dev = dev; 439251018Sgonzo 440251018Sgonzo if (am335x_read_panel_info(dev, &panel)) 441251018Sgonzo return (ENXIO); 442251018Sgonzo 443251018Sgonzo int ref_freq = 0; 444251018Sgonzo ti_prcm_clk_enable(LCDC_CLK); 445251018Sgonzo if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { 446251018Sgonzo device_printf(dev, "Can't get reference frequency\n"); 447251018Sgonzo return (ENXIO); 448251018Sgonzo } 449251018Sgonzo 450251018Sgonzo rid = 0; 451251018Sgonzo sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 452251018Sgonzo RF_ACTIVE); 453251018Sgonzo if (!sc->sc_mem_res) { 454251018Sgonzo device_printf(dev, "cannot allocate memory window\n"); 455251018Sgonzo return (ENXIO); 456251018Sgonzo } 457251018Sgonzo 458251018Sgonzo rid = 0; 459251018Sgonzo sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 460251018Sgonzo RF_ACTIVE); 461251018Sgonzo if (!sc->sc_irq_res) { 462251018Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 463251018Sgonzo device_printf(dev, "cannot allocate interrupt\n"); 464251018Sgonzo return (ENXIO); 465251018Sgonzo } 466251018Sgonzo 467251018Sgonzo if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 468251018Sgonzo NULL, am335x_lcd_intr, sc, 469251018Sgonzo &sc->sc_intr_hl) != 0) { 470251018Sgonzo bus_release_resource(dev, SYS_RES_IRQ, rid, 471251018Sgonzo sc->sc_irq_res); 472251018Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, rid, 473251018Sgonzo sc->sc_mem_res); 474251018Sgonzo device_printf(dev, "Unable to setup the irq handler.\n"); 475251018Sgonzo return (ENXIO); 476251018Sgonzo } 477251018Sgonzo 478251018Sgonzo LCD_LOCK_INIT(sc); 479251018Sgonzo 480251018Sgonzo /* Panle initialization */ 481251018Sgonzo dma_size = round_page(panel.panel_width*panel.panel_height*panel.bpp/8); 482251018Sgonzo 483251018Sgonzo /* 484251018Sgonzo * Now allocate framebuffer memory 485251018Sgonzo */ 486251018Sgonzo err = bus_dma_tag_create( 487251018Sgonzo bus_get_dma_tag(dev), 488251018Sgonzo 4, 0, /* alignment, boundary */ 489251018Sgonzo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 490251018Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 491251018Sgonzo NULL, NULL, /* filter, filterarg */ 492251018Sgonzo dma_size, 1, /* maxsize, nsegments */ 493251018Sgonzo dma_size, 0, /* maxsegsize, flags */ 494251018Sgonzo NULL, NULL, /* lockfunc, lockarg */ 495251018Sgonzo &sc->sc_dma_tag); 496251018Sgonzo if (err) 497251018Sgonzo goto fail; 498251018Sgonzo 499251018Sgonzo err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 500252282Sgonzo BUS_DMA_COHERENT, &sc->sc_dma_map); 501251018Sgonzo 502251018Sgonzo if (err) { 503251018Sgonzo device_printf(dev, "cannot allocate framebuffer\n"); 504251018Sgonzo goto fail; 505251018Sgonzo } 506251018Sgonzo 507251018Sgonzo err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 508251018Sgonzo dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 509251018Sgonzo 510251018Sgonzo if (err) { 511251018Sgonzo device_printf(dev, "cannot load DMA map\n"); 512251018Sgonzo goto fail; 513251018Sgonzo } 514251018Sgonzo 515251018Sgonzo /* Make sure it's blank */ 516251018Sgonzo memset(sc->sc_fb_base, 0x00, dma_size); 517251018Sgonzo 518251018Sgonzo /* Calculate actual FB Size */ 519251018Sgonzo sc->sc_fb_size = panel.panel_width*panel.panel_height*panel.bpp/8; 520251018Sgonzo 521251018Sgonzo /* Only raster mode is supported */ 522251018Sgonzo reg = CTRL_RASTER_MODE; 523251018Sgonzo div = am335x_lcd_calc_divisor(ref_freq, panel.panel_pxl_clk); 524251018Sgonzo reg |= (div << CTRL_DIV_SHIFT); 525251018Sgonzo LCD_WRITE4(sc, LCD_CTRL, reg); 526251018Sgonzo 527251018Sgonzo /* Set timing */ 528251018Sgonzo timing0 = timing1 = timing2 = 0; 529251018Sgonzo 530251018Sgonzo /* Horizontal back porch */ 531251018Sgonzo timing0 |= (panel.panel_hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; 532251018Sgonzo timing2 |= ((panel.panel_hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; 533251018Sgonzo /* Horizontal front porch */ 534251018Sgonzo timing0 |= (panel.panel_hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; 535251018Sgonzo timing2 |= ((panel.panel_hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; 536251018Sgonzo /* Horizontal sync width */ 537251018Sgonzo timing0 |= (panel.panel_hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; 538251018Sgonzo timing2 |= ((panel.panel_hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; 539251018Sgonzo 540251018Sgonzo /* Vertical back porch, front porch, sync width */ 541251018Sgonzo timing1 |= (panel.panel_vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; 542251018Sgonzo timing1 |= (panel.panel_vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; 543251018Sgonzo timing1 |= (panel.panel_vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; 544251018Sgonzo 545251018Sgonzo /* Pixels per line */ 546251018Sgonzo timing0 |= (((panel.panel_width - 1) >> 10) & 1) 547251018Sgonzo << RASTER_TIMING_0_PPLMSB_SHIFT; 548251018Sgonzo timing0 |= (((panel.panel_width - 1) >> 4) & 0x3f) 549251018Sgonzo << RASTER_TIMING_0_PPLLSB_SHIFT; 550251018Sgonzo 551251018Sgonzo /* Lines per panel */ 552251018Sgonzo timing1 |= ((panel.panel_height - 1) & 0x3ff) 553251018Sgonzo << RASTER_TIMING_1_LPP_SHIFT; 554251018Sgonzo timing2 |= (((panel.panel_height - 1) >> 10 ) & 1) 555251018Sgonzo << RASTER_TIMING_2_LPP_B10_SHIFT; 556251018Sgonzo 557251018Sgonzo /* clock signal settings */ 558251018Sgonzo if (panel.sync_ctrl) 559251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS; 560251018Sgonzo if (panel.sync_edge) 561251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS_RISE; 562251018Sgonzo else 563251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS_FALL; 564251018Sgonzo if (panel.invert_line_clock) 565251018Sgonzo timing2 |= RASTER_TIMING_2_IHS; 566251018Sgonzo if (panel.invert_frm_clock) 567251018Sgonzo timing2 |= RASTER_TIMING_2_IVS; 568251018Sgonzo if (panel.panel_invert_pxl_clk) 569251018Sgonzo timing2 |= RASTER_TIMING_2_IPC; 570251018Sgonzo 571251018Sgonzo /* AC bias */ 572251018Sgonzo timing2 |= (panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); 573251018Sgonzo timing2 |= (panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); 574251018Sgonzo 575251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); 576251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); 577251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); 578251018Sgonzo 579251018Sgonzo /* DMA settings */ 580251018Sgonzo reg = LCDDMA_CTRL_FB0_FB1; 581251018Sgonzo /* Find power of 2 for current burst size */ 582251018Sgonzo switch (panel.dma_burst_sz) { 583251018Sgonzo case 1: 584251018Sgonzo burst_log = 0; 585251018Sgonzo break; 586251018Sgonzo case 2: 587251018Sgonzo burst_log = 1; 588251018Sgonzo break; 589251018Sgonzo case 4: 590251018Sgonzo burst_log = 2; 591251018Sgonzo break; 592251018Sgonzo case 8: 593251018Sgonzo burst_log = 3; 594251018Sgonzo break; 595251018Sgonzo case 16: 596251018Sgonzo default: 597251018Sgonzo burst_log = 4; 598251018Sgonzo break; 599251018Sgonzo } 600251018Sgonzo reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); 601251018Sgonzo /* XXX: FIFO TH */ 602251018Sgonzo reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); 603251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); 604251018Sgonzo 605251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 606251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 607251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 608251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 609251018Sgonzo 610251018Sgonzo /* Enable LCD */ 611251018Sgonzo reg = RASTER_CTRL_LCDTFT; 612251018Sgonzo reg |= (panel.fdd << RASTER_CTRL_REQDLY_SHIFT); 613251018Sgonzo reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); 614251018Sgonzo if (panel.bpp >= 24) 615251018Sgonzo reg |= RASTER_CTRL_TFT24; 616251018Sgonzo if (panel.bpp == 32) 617251018Sgonzo reg |= RASTER_CTRL_TFT24_UNPACKED; 618251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 619251018Sgonzo 620251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_ENABLE, 621251018Sgonzo CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); 622251018Sgonzo 623251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); 624251018Sgonzo DELAY(100); 625251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_RESET, 0); 626251018Sgonzo 627251018Sgonzo reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | 628251018Sgonzo IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | 629251018Sgonzo IRQ_FRAME_DONE; 630251018Sgonzo LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); 631251018Sgonzo 632251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 633251018Sgonzo reg |= RASTER_CTRL_LCDEN; 634251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 635251018Sgonzo 636251018Sgonzo LCD_WRITE4(sc, LCD_SYSCONFIG, 637251018Sgonzo SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); 638251018Sgonzo 639251018Sgonzo /* Init backlight interface */ 640251018Sgonzo ctx = device_get_sysctl_ctx(sc->sc_dev); 641251018Sgonzo tree = device_get_sysctl_tree(sc->sc_dev); 642251018Sgonzo sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 643251018Sgonzo "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 644251018Sgonzo am335x_lcd_sysctl_backlight, "I", "LCD backlight"); 645251018Sgonzo sc->sc_backlight = 0; 646251018Sgonzo /* Check if eCAS interface is available at this point */ 647251018Sgonzo if (am335x_pwm_config_ecas(PWM_UNIT, 648251018Sgonzo PWM_PERIOD, PWM_PERIOD) == 0) 649251018Sgonzo sc->sc_backlight = 100; 650251018Sgonzo 651252282Sgonzo err = (sc_attach_unit(device_get_unit(dev), 652252282Sgonzo device_get_flags(dev) | SC_AUTODETECT_KBD)); 653252282Sgonzo 654252282Sgonzo if (err) { 655252282Sgonzo device_printf(dev, "failed to attach syscons\n"); 656252282Sgonzo goto fail; 657252282Sgonzo } 658252282Sgonzo 659251018Sgonzo am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); 660251018Sgonzo 661251018Sgonzo return (0); 662251018Sgonzo 663251018Sgonzofail: 664251018Sgonzo return (err); 665251018Sgonzo} 666251018Sgonzo 667251018Sgonzostatic int 668251018Sgonzoam335x_lcd_detach(device_t dev) 669251018Sgonzo{ 670251018Sgonzo /* Do not let unload driver */ 671251018Sgonzo return (EBUSY); 672251018Sgonzo} 673251018Sgonzo 674251018Sgonzostatic device_method_t am335x_lcd_methods[] = { 675251018Sgonzo DEVMETHOD(device_probe, am335x_lcd_probe), 676251018Sgonzo DEVMETHOD(device_attach, am335x_lcd_attach), 677251018Sgonzo DEVMETHOD(device_detach, am335x_lcd_detach), 678251018Sgonzo 679251018Sgonzo DEVMETHOD_END 680251018Sgonzo}; 681251018Sgonzo 682251018Sgonzostatic driver_t am335x_lcd_driver = { 683251018Sgonzo "am335x_lcd", 684251018Sgonzo am335x_lcd_methods, 685251018Sgonzo sizeof(struct am335x_lcd_softc), 686251018Sgonzo}; 687251018Sgonzo 688251018Sgonzostatic devclass_t am335x_lcd_devclass; 689251018Sgonzo 690251018SgonzoDRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); 691251018SgonzoMODULE_VERSION(am335x_lcd, 1); 692251018SgonzoMODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); 693