am335x_lcd.c revision 251018
1251018Sgonzo/*- 2251018Sgonzo * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3251018Sgonzo * All rights reserved. 4251018Sgonzo * 5251018Sgonzo * Redistribution and use in source and binary forms, with or without 6251018Sgonzo * modification, are permitted provided that the following conditions 7251018Sgonzo * are met: 8251018Sgonzo * 1. Redistributions of source code must retain the above copyright 9251018Sgonzo * notice, this list of conditions and the following disclaimer. 10251018Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11251018Sgonzo * notice, this list of conditions and the following disclaimer in the 12251018Sgonzo * documentation and/or other materials provided with the distribution. 13251018Sgonzo * 14251018Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15251018Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16251018Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17251018Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18251018Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19251018Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20251018Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21251018Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22251018Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23251018Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24251018Sgonzo * SUCH DAMAGE. 25251018Sgonzo */ 26251018Sgonzo 27251018Sgonzo#include <sys/cdefs.h> 28251018Sgonzo__FBSDID("$FreeBSD: head/sys/arm/ti/am335x/am335x_lcd.c 251018 2013-05-27 00:23:01Z gonzo $"); 29251018Sgonzo 30251018Sgonzo#include <sys/param.h> 31251018Sgonzo#include <sys/systm.h> 32251018Sgonzo#include <sys/kernel.h> 33251018Sgonzo#include <sys/module.h> 34251018Sgonzo#include <sys/clock.h> 35251018Sgonzo#include <sys/time.h> 36251018Sgonzo#include <sys/bus.h> 37251018Sgonzo#include <sys/lock.h> 38251018Sgonzo#include <sys/mutex.h> 39251018Sgonzo#include <sys/resource.h> 40251018Sgonzo#include <sys/rman.h> 41251018Sgonzo#include <sys/sysctl.h> 42251018Sgonzo#include <vm/vm.h> 43251018Sgonzo#include <vm/pmap.h> 44251018Sgonzo 45251018Sgonzo#include <machine/bus.h> 46251018Sgonzo 47251018Sgonzo#include <dev/fdt/fdt_common.h> 48251018Sgonzo#include <dev/ofw/openfirm.h> 49251018Sgonzo#include <dev/ofw/ofw_bus.h> 50251018Sgonzo#include <dev/ofw/ofw_bus_subr.h> 51251018Sgonzo 52251018Sgonzo#include <arm/ti/ti_prcm.h> 53251018Sgonzo#include <arm/ti/ti_scm.h> 54251018Sgonzo 55251018Sgonzo#include "am335x_lcd.h" 56251018Sgonzo#include "am335x_pwm.h" 57251018Sgonzo 58251018Sgonzo#define LCD_PID 0x00 59251018Sgonzo#define LCD_CTRL 0x04 60251018Sgonzo#define CTRL_DIV_MASK 0xff 61251018Sgonzo#define CTRL_DIV_SHIFT 8 62251018Sgonzo#define CTRL_AUTO_UFLOW_RESTART (1 << 1) 63251018Sgonzo#define CTRL_RASTER_MODE 1 64251018Sgonzo#define CTRL_LIDD_MODE 0 65251018Sgonzo#define LCD_LIDD_CTRL 0x0C 66251018Sgonzo#define LCD_LIDD_CS0_CONF 0x10 67251018Sgonzo#define LCD_LIDD_CS0_ADDR 0x14 68251018Sgonzo#define LCD_LIDD_CS0_DATA 0x18 69251018Sgonzo#define LCD_LIDD_CS1_CONF 0x1C 70251018Sgonzo#define LCD_LIDD_CS1_ADDR 0x20 71251018Sgonzo#define LCD_LIDD_CS1_DATA 0x24 72251018Sgonzo#define LCD_RASTER_CTRL 0x28 73251018Sgonzo#define RASTER_CTRL_TFT24_UNPACKED (1 << 26) 74251018Sgonzo#define RASTER_CTRL_TFT24 (1 << 25) 75251018Sgonzo#define RASTER_CTRL_STN565 (1 << 24) 76251018Sgonzo#define RASTER_CTRL_TFTPMAP (1 << 23) 77251018Sgonzo#define RASTER_CTRL_NIBMODE (1 << 22) 78251018Sgonzo#define RASTER_CTRL_PALMODE_SHIFT 20 79251018Sgonzo#define PALETTE_PALETTE_AND_DATA 0x00 80251018Sgonzo#define PALETTE_PALETTE_ONLY 0x01 81251018Sgonzo#define PALETTE_DATA_ONLY 0x02 82251018Sgonzo#define RASTER_CTRL_REQDLY_SHIFT 12 83251018Sgonzo#define RASTER_CTRL_MONO8B (1 << 9) 84251018Sgonzo#define RASTER_CTRL_RBORDER (1 << 8) 85251018Sgonzo#define RASTER_CTRL_LCDTFT (1 << 7) 86251018Sgonzo#define RASTER_CTRL_LCDBW (1 << 1) 87251018Sgonzo#define RASTER_CTRL_LCDEN (1 << 0) 88251018Sgonzo#define LCD_RASTER_TIMING_0 0x2C 89251018Sgonzo#define RASTER_TIMING_0_HBP_SHIFT 24 90251018Sgonzo#define RASTER_TIMING_0_HFP_SHIFT 16 91251018Sgonzo#define RASTER_TIMING_0_HSW_SHIFT 10 92251018Sgonzo#define RASTER_TIMING_0_PPLLSB_SHIFT 4 93251018Sgonzo#define RASTER_TIMING_0_PPLMSB_SHIFT 3 94251018Sgonzo#define LCD_RASTER_TIMING_1 0x30 95251018Sgonzo#define RASTER_TIMING_1_VBP_SHIFT 24 96251018Sgonzo#define RASTER_TIMING_1_VFP_SHIFT 16 97251018Sgonzo#define RASTER_TIMING_1_VSW_SHIFT 10 98251018Sgonzo#define RASTER_TIMING_1_LPP_SHIFT 0 99251018Sgonzo#define LCD_RASTER_TIMING_2 0x34 100251018Sgonzo#define RASTER_TIMING_2_HSWHI_SHIFT 27 101251018Sgonzo#define RASTER_TIMING_2_LPP_B10_SHIFT 26 102251018Sgonzo#define RASTER_TIMING_2_PHSVS (1 << 25) 103251018Sgonzo#define RASTER_TIMING_2_PHSVS_RISE (1 << 24) 104251018Sgonzo#define RASTER_TIMING_2_PHSVS_FALL (0 << 24) 105251018Sgonzo#define RASTER_TIMING_2_IOE (1 << 23) 106251018Sgonzo#define RASTER_TIMING_2_IPC (1 << 22) 107251018Sgonzo#define RASTER_TIMING_2_IHS (1 << 21) 108251018Sgonzo#define RASTER_TIMING_2_IVS (1 << 20) 109251018Sgonzo#define RASTER_TIMING_2_ACBI_SHIFT 16 110251018Sgonzo#define RASTER_TIMING_2_ACB_SHIFT 8 111251018Sgonzo#define RASTER_TIMING_2_HBPHI_SHIFT 4 112251018Sgonzo#define RASTER_TIMING_2_HFPHI_SHIFT 0 113251018Sgonzo#define LCD_RASTER_SUBPANEL 0x38 114251018Sgonzo#define LCD_RASTER_SUBPANEL2 0x3C 115251018Sgonzo#define LCD_LCDDMA_CTRL 0x40 116251018Sgonzo#define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 117251018Sgonzo#define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 118251018Sgonzo#define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 119251018Sgonzo#define LCDDMA_CTRL_BYTES_SWAP (1 << 3) 120251018Sgonzo#define LCDDMA_CTRL_BE (1 << 1) 121251018Sgonzo#define LCDDMA_CTRL_FB0_ONLY 0 122251018Sgonzo#define LCDDMA_CTRL_FB0_FB1 (1 << 0) 123251018Sgonzo#define LCD_LCDDMA_FB0_BASE 0x44 124251018Sgonzo#define LCD_LCDDMA_FB0_CEILING 0x48 125251018Sgonzo#define LCD_LCDDMA_FB1_BASE 0x4C 126251018Sgonzo#define LCD_LCDDMA_FB1_CEILING 0x50 127251018Sgonzo#define LCD_SYSCONFIG 0x54 128251018Sgonzo#define SYSCONFIG_STANDBY_FORCE (0 << 4) 129251018Sgonzo#define SYSCONFIG_STANDBY_NONE (1 << 4) 130251018Sgonzo#define SYSCONFIG_STANDBY_SMART (2 << 4) 131251018Sgonzo#define SYSCONFIG_IDLE_FORCE (0 << 2) 132251018Sgonzo#define SYSCONFIG_IDLE_NONE (1 << 2) 133251018Sgonzo#define SYSCONFIG_IDLE_SMART (2 << 2) 134251018Sgonzo#define LCD_IRQSTATUS_RAW 0x58 135251018Sgonzo#define LCD_IRQSTATUS 0x5C 136251018Sgonzo#define LCD_IRQENABLE_SET 0x60 137251018Sgonzo#define LCD_IRQENABLE_CLEAR 0x64 138251018Sgonzo#define IRQ_EOF1 (1 << 9) 139251018Sgonzo#define IRQ_EOF0 (1 << 8) 140251018Sgonzo#define IRQ_PL (1 << 6) 141251018Sgonzo#define IRQ_FUF (1 << 5) 142251018Sgonzo#define IRQ_ACB (1 << 3) 143251018Sgonzo#define IRQ_SYNC_LOST (1 << 2) 144251018Sgonzo#define IRQ_RASTER_DONE (1 << 1) 145251018Sgonzo#define IRQ_FRAME_DONE (1 << 0) 146251018Sgonzo#define LCD_CLKC_ENABLE 0x6C 147251018Sgonzo#define CLKC_ENABLE_DMA (1 << 2) 148251018Sgonzo#define CLKC_ENABLE_LDID (1 << 1) 149251018Sgonzo#define CLKC_ENABLE_CORE (1 << 0) 150251018Sgonzo#define LCD_CLKC_RESET 0x70 151251018Sgonzo#define CLKC_RESET_MAIN (1 << 3) 152251018Sgonzo#define CLKC_RESET_DMA (1 << 2) 153251018Sgonzo#define CLKC_RESET_LDID (1 << 1) 154251018Sgonzo#define CLKC_RESET_CORE (1 << 0) 155251018Sgonzo 156251018Sgonzo#define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 157251018Sgonzo#define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 158251018Sgonzo#define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 159251018Sgonzo device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) 160251018Sgonzo#define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 161251018Sgonzo 162251018Sgonzo#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); 163251018Sgonzo#define LCD_WRITE4(_sc, reg, value) \ 164251018Sgonzo bus_write_4((_sc)->sc_mem_res, reg, value); 165251018Sgonzo 166251018Sgonzo 167251018Sgonzo/* Backlight is controlled by eCAS interface on PWM unit 0 */ 168251018Sgonzo#define PWM_UNIT 0 169251018Sgonzo#define PWM_PERIOD 100 170251018Sgonzo 171251018Sgonzostruct am335x_lcd_softc { 172251018Sgonzo device_t sc_dev; 173251018Sgonzo struct resource *sc_mem_res; 174251018Sgonzo struct resource *sc_irq_res; 175251018Sgonzo void *sc_intr_hl; 176251018Sgonzo struct mtx sc_mtx; 177251018Sgonzo int sc_backlight; 178251018Sgonzo struct sysctl_oid *sc_oid; 179251018Sgonzo 180251018Sgonzo /* Framebuffer */ 181251018Sgonzo bus_dma_tag_t sc_dma_tag; 182251018Sgonzo bus_dmamap_t sc_dma_map; 183251018Sgonzo size_t sc_fb_size; 184251018Sgonzo bus_addr_t sc_fb_phys; 185251018Sgonzo uint8_t *sc_fb_base; 186251018Sgonzo}; 187251018Sgonzo 188251018Sgonzostatic void 189251018Sgonzoam335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 190251018Sgonzo{ 191251018Sgonzo bus_addr_t *addr; 192251018Sgonzo 193251018Sgonzo if (err) 194251018Sgonzo return; 195251018Sgonzo 196251018Sgonzo addr = (bus_addr_t*)arg; 197251018Sgonzo *addr = segs[0].ds_addr; 198251018Sgonzo} 199251018Sgonzo 200251018Sgonzostatic uint32_t 201251018Sgonzoam335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) 202251018Sgonzo{ 203251018Sgonzo uint32_t div; 204251018Sgonzo /* Raster mode case: divisors are in range from 2 to 255 */ 205251018Sgonzo for (div = 2; div < 255; div++) 206251018Sgonzo if (reference/div <= freq) 207251018Sgonzo return (div); 208251018Sgonzo 209251018Sgonzo return (255); 210251018Sgonzo} 211251018Sgonzo 212251018Sgonzostatic int 213251018Sgonzoam335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) 214251018Sgonzo{ 215251018Sgonzo struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; 216251018Sgonzo int error; 217251018Sgonzo int backlight; 218251018Sgonzo 219251018Sgonzo backlight = sc->sc_backlight;; 220251018Sgonzo error = sysctl_handle_int(oidp, &backlight, 0, req); 221251018Sgonzo 222251018Sgonzo if (error != 0 || req->newptr == NULL) 223251018Sgonzo return (error); 224251018Sgonzo 225251018Sgonzo if (backlight < 0) 226251018Sgonzo backlight = 0; 227251018Sgonzo if (backlight > 100) 228251018Sgonzo backlight = 100; 229251018Sgonzo 230251018Sgonzo LCD_LOCK(sc); 231251018Sgonzo error = am335x_pwm_config_ecas(PWM_UNIT, PWM_PERIOD, 232251018Sgonzo backlight*PWM_PERIOD/100); 233251018Sgonzo if (error == 0) 234251018Sgonzo sc->sc_backlight = backlight; 235251018Sgonzo LCD_UNLOCK(sc); 236251018Sgonzo 237251018Sgonzo return (error); 238251018Sgonzo} 239251018Sgonzo 240251018Sgonzostatic int 241251018Sgonzoam335x_read_panel_property(device_t dev, const char *name, uint32_t *val) 242251018Sgonzo{ 243251018Sgonzo phandle_t node; 244251018Sgonzo pcell_t cell; 245251018Sgonzo 246251018Sgonzo node = ofw_bus_get_node(dev); 247251018Sgonzo if ((OF_getprop(node, name, &cell, sizeof(cell))) <= 0) { 248251018Sgonzo device_printf(dev, "missing '%s' attribute in LCD panel info\n", 249251018Sgonzo name); 250251018Sgonzo return (ENXIO); 251251018Sgonzo } 252251018Sgonzo 253251018Sgonzo *val = fdt32_to_cpu(cell); 254251018Sgonzo 255251018Sgonzo return (0); 256251018Sgonzo} 257251018Sgonzo 258251018Sgonzostatic int 259251018Sgonzoam335x_read_panel_info(device_t dev, struct panel_info *panel) 260251018Sgonzo{ 261251018Sgonzo int error; 262251018Sgonzo 263251018Sgonzo error = 0; 264251018Sgonzo if ((error = am335x_read_panel_property(dev, 265251018Sgonzo "panel_width", &panel->panel_width))) 266251018Sgonzo goto out; 267251018Sgonzo 268251018Sgonzo if ((error = am335x_read_panel_property(dev, 269251018Sgonzo "panel_height", &panel->panel_height))) 270251018Sgonzo goto out; 271251018Sgonzo 272251018Sgonzo if ((error = am335x_read_panel_property(dev, 273251018Sgonzo "panel_hfp", &panel->panel_hfp))) 274251018Sgonzo goto out; 275251018Sgonzo 276251018Sgonzo if ((error = am335x_read_panel_property(dev, 277251018Sgonzo "panel_hbp", &panel->panel_hbp))) 278251018Sgonzo goto out; 279251018Sgonzo 280251018Sgonzo if ((error = am335x_read_panel_property(dev, 281251018Sgonzo "panel_hsw", &panel->panel_hsw))) 282251018Sgonzo goto out; 283251018Sgonzo 284251018Sgonzo if ((error = am335x_read_panel_property(dev, 285251018Sgonzo "panel_vfp", &panel->panel_vfp))) 286251018Sgonzo goto out; 287251018Sgonzo 288251018Sgonzo if ((error = am335x_read_panel_property(dev, 289251018Sgonzo "panel_vbp", &panel->panel_vbp))) 290251018Sgonzo goto out; 291251018Sgonzo 292251018Sgonzo if ((error = am335x_read_panel_property(dev, 293251018Sgonzo "panel_vsw", &panel->panel_vsw))) 294251018Sgonzo goto out; 295251018Sgonzo 296251018Sgonzo if ((error = am335x_read_panel_property(dev, 297251018Sgonzo "panel_pxl_clk", &panel->panel_pxl_clk))) 298251018Sgonzo goto out; 299251018Sgonzo 300251018Sgonzo if ((error = am335x_read_panel_property(dev, 301251018Sgonzo "panel_invert_pxl_clk", &panel->panel_invert_pxl_clk))) 302251018Sgonzo goto out; 303251018Sgonzo 304251018Sgonzo if ((error = am335x_read_panel_property(dev, 305251018Sgonzo "ac_bias", &panel->ac_bias))) 306251018Sgonzo goto out; 307251018Sgonzo 308251018Sgonzo if ((error = am335x_read_panel_property(dev, 309251018Sgonzo "ac_bias_intrpt", &panel->ac_bias_intrpt))) 310251018Sgonzo goto out; 311251018Sgonzo 312251018Sgonzo if ((error = am335x_read_panel_property(dev, 313251018Sgonzo "dma_burst_sz", &panel->dma_burst_sz))) 314251018Sgonzo goto out; 315251018Sgonzo 316251018Sgonzo if ((error = am335x_read_panel_property(dev, 317251018Sgonzo "bpp", &panel->bpp))) 318251018Sgonzo goto out; 319251018Sgonzo 320251018Sgonzo if ((error = am335x_read_panel_property(dev, 321251018Sgonzo "fdd", &panel->fdd))) 322251018Sgonzo goto out; 323251018Sgonzo 324251018Sgonzo if ((error = am335x_read_panel_property(dev, 325251018Sgonzo "invert_line_clock", &panel->invert_line_clock))) 326251018Sgonzo goto out; 327251018Sgonzo 328251018Sgonzo if ((error = am335x_read_panel_property(dev, 329251018Sgonzo "invert_frm_clock", &panel->invert_frm_clock))) 330251018Sgonzo goto out; 331251018Sgonzo 332251018Sgonzo if ((error = am335x_read_panel_property(dev, 333251018Sgonzo "sync_edge", &panel->sync_edge))) 334251018Sgonzo goto out; 335251018Sgonzo 336251018Sgonzo error = am335x_read_panel_property(dev, 337251018Sgonzo "sync_ctrl", &panel->sync_ctrl); 338251018Sgonzo 339251018Sgonzoout: 340251018Sgonzo return (error); 341251018Sgonzo} 342251018Sgonzo 343251018Sgonzostatic void 344251018Sgonzoam335x_lcd_intr(void *arg) 345251018Sgonzo{ 346251018Sgonzo struct am335x_lcd_softc *sc = arg; 347251018Sgonzo uint32_t reg; 348251018Sgonzo 349251018Sgonzo reg = LCD_READ4(sc, LCD_IRQSTATUS); 350251018Sgonzo LCD_WRITE4(sc, LCD_IRQSTATUS, reg); 351251018Sgonzo 352251018Sgonzo if (reg & IRQ_SYNC_LOST) { 353251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 354251018Sgonzo reg &= ~RASTER_CTRL_LCDEN; 355251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 356251018Sgonzo 357251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 358251018Sgonzo reg |= RASTER_CTRL_LCDEN; 359251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 360251018Sgonzo return; 361251018Sgonzo } 362251018Sgonzo 363251018Sgonzo if (reg & IRQ_PL) { 364251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 365251018Sgonzo reg &= ~RASTER_CTRL_LCDEN; 366251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 367251018Sgonzo 368251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 369251018Sgonzo reg |= RASTER_CTRL_LCDEN; 370251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 371251018Sgonzo return; 372251018Sgonzo } 373251018Sgonzo 374251018Sgonzo if (reg & IRQ_EOF0) { 375251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 376251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 377251018Sgonzo reg &= ~IRQ_EOF0; 378251018Sgonzo } 379251018Sgonzo 380251018Sgonzo if (reg & IRQ_EOF1) { 381251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 382251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 383251018Sgonzo reg &= ~IRQ_EOF1; 384251018Sgonzo } 385251018Sgonzo 386251018Sgonzo if (reg & IRQ_FUF) { 387251018Sgonzo /* TODO: Handle FUF */ 388251018Sgonzo } 389251018Sgonzo 390251018Sgonzo if (reg & IRQ_ACB) { 391251018Sgonzo /* TODO: Handle ACB */ 392251018Sgonzo } 393251018Sgonzo} 394251018Sgonzo 395251018Sgonzostatic int 396251018Sgonzoam335x_lcd_probe(device_t dev) 397251018Sgonzo{ 398251018Sgonzo if (!ofw_bus_is_compatible(dev, "ti,am335x-lcd")) 399251018Sgonzo return (ENXIO); 400251018Sgonzo 401251018Sgonzo device_set_desc(dev, "AM335x LCD controller"); 402251018Sgonzo 403251018Sgonzo return (0); 404251018Sgonzo} 405251018Sgonzo 406251018Sgonzostatic int 407251018Sgonzoam335x_lcd_attach(device_t dev) 408251018Sgonzo{ 409251018Sgonzo struct am335x_lcd_softc *sc; 410251018Sgonzo int rid; 411251018Sgonzo int div; 412251018Sgonzo struct panel_info panel; 413251018Sgonzo uint32_t reg, timing0, timing1, timing2; 414251018Sgonzo struct sysctl_ctx_list *ctx; 415251018Sgonzo struct sysctl_oid *tree; 416251018Sgonzo uint32_t burst_log; 417251018Sgonzo int err; 418251018Sgonzo size_t dma_size; 419251018Sgonzo 420251018Sgonzo sc = device_get_softc(dev); 421251018Sgonzo sc->sc_dev = dev; 422251018Sgonzo 423251018Sgonzo if (am335x_read_panel_info(dev, &panel)) 424251018Sgonzo return (ENXIO); 425251018Sgonzo 426251018Sgonzo int ref_freq = 0; 427251018Sgonzo ti_prcm_clk_enable(LCDC_CLK); 428251018Sgonzo if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { 429251018Sgonzo device_printf(dev, "Can't get reference frequency\n"); 430251018Sgonzo return (ENXIO); 431251018Sgonzo } 432251018Sgonzo 433251018Sgonzo rid = 0; 434251018Sgonzo sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 435251018Sgonzo RF_ACTIVE); 436251018Sgonzo if (!sc->sc_mem_res) { 437251018Sgonzo device_printf(dev, "cannot allocate memory window\n"); 438251018Sgonzo return (ENXIO); 439251018Sgonzo } 440251018Sgonzo 441251018Sgonzo rid = 0; 442251018Sgonzo sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 443251018Sgonzo RF_ACTIVE); 444251018Sgonzo if (!sc->sc_irq_res) { 445251018Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 446251018Sgonzo device_printf(dev, "cannot allocate interrupt\n"); 447251018Sgonzo return (ENXIO); 448251018Sgonzo } 449251018Sgonzo 450251018Sgonzo if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 451251018Sgonzo NULL, am335x_lcd_intr, sc, 452251018Sgonzo &sc->sc_intr_hl) != 0) { 453251018Sgonzo bus_release_resource(dev, SYS_RES_IRQ, rid, 454251018Sgonzo sc->sc_irq_res); 455251018Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, rid, 456251018Sgonzo sc->sc_mem_res); 457251018Sgonzo device_printf(dev, "Unable to setup the irq handler.\n"); 458251018Sgonzo return (ENXIO); 459251018Sgonzo } 460251018Sgonzo 461251018Sgonzo LCD_LOCK_INIT(sc); 462251018Sgonzo 463251018Sgonzo /* Panle initialization */ 464251018Sgonzo dma_size = round_page(panel.panel_width*panel.panel_height*panel.bpp/8); 465251018Sgonzo 466251018Sgonzo /* 467251018Sgonzo * Now allocate framebuffer memory 468251018Sgonzo */ 469251018Sgonzo err = bus_dma_tag_create( 470251018Sgonzo bus_get_dma_tag(dev), 471251018Sgonzo 4, 0, /* alignment, boundary */ 472251018Sgonzo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 473251018Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 474251018Sgonzo NULL, NULL, /* filter, filterarg */ 475251018Sgonzo dma_size, 1, /* maxsize, nsegments */ 476251018Sgonzo dma_size, 0, /* maxsegsize, flags */ 477251018Sgonzo NULL, NULL, /* lockfunc, lockarg */ 478251018Sgonzo &sc->sc_dma_tag); 479251018Sgonzo if (err) 480251018Sgonzo goto fail; 481251018Sgonzo 482251018Sgonzo err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 483251018Sgonzo 0, &sc->sc_dma_map); 484251018Sgonzo 485251018Sgonzo if (err) { 486251018Sgonzo device_printf(dev, "cannot allocate framebuffer\n"); 487251018Sgonzo goto fail; 488251018Sgonzo } 489251018Sgonzo 490251018Sgonzo err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 491251018Sgonzo dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 492251018Sgonzo 493251018Sgonzo if (err) { 494251018Sgonzo device_printf(dev, "cannot load DMA map\n"); 495251018Sgonzo goto fail; 496251018Sgonzo } 497251018Sgonzo 498251018Sgonzo /* Make sure it's blank */ 499251018Sgonzo memset(sc->sc_fb_base, 0x00, dma_size); 500251018Sgonzo 501251018Sgonzo /* Calculate actual FB Size */ 502251018Sgonzo sc->sc_fb_size = panel.panel_width*panel.panel_height*panel.bpp/8; 503251018Sgonzo 504251018Sgonzo /* Only raster mode is supported */ 505251018Sgonzo reg = CTRL_RASTER_MODE; 506251018Sgonzo div = am335x_lcd_calc_divisor(ref_freq, panel.panel_pxl_clk); 507251018Sgonzo reg |= (div << CTRL_DIV_SHIFT); 508251018Sgonzo LCD_WRITE4(sc, LCD_CTRL, reg); 509251018Sgonzo 510251018Sgonzo /* Set timing */ 511251018Sgonzo timing0 = timing1 = timing2 = 0; 512251018Sgonzo 513251018Sgonzo /* Horizontal back porch */ 514251018Sgonzo timing0 |= (panel.panel_hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; 515251018Sgonzo timing2 |= ((panel.panel_hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; 516251018Sgonzo /* Horizontal front porch */ 517251018Sgonzo timing0 |= (panel.panel_hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; 518251018Sgonzo timing2 |= ((panel.panel_hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; 519251018Sgonzo /* Horizontal sync width */ 520251018Sgonzo timing0 |= (panel.panel_hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; 521251018Sgonzo timing2 |= ((panel.panel_hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; 522251018Sgonzo 523251018Sgonzo /* Vertical back porch, front porch, sync width */ 524251018Sgonzo timing1 |= (panel.panel_vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; 525251018Sgonzo timing1 |= (panel.panel_vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; 526251018Sgonzo timing1 |= (panel.panel_vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; 527251018Sgonzo 528251018Sgonzo /* Pixels per line */ 529251018Sgonzo timing0 |= (((panel.panel_width - 1) >> 10) & 1) 530251018Sgonzo << RASTER_TIMING_0_PPLMSB_SHIFT; 531251018Sgonzo timing0 |= (((panel.panel_width - 1) >> 4) & 0x3f) 532251018Sgonzo << RASTER_TIMING_0_PPLLSB_SHIFT; 533251018Sgonzo 534251018Sgonzo /* Lines per panel */ 535251018Sgonzo timing1 |= ((panel.panel_height - 1) & 0x3ff) 536251018Sgonzo << RASTER_TIMING_1_LPP_SHIFT; 537251018Sgonzo timing2 |= (((panel.panel_height - 1) >> 10 ) & 1) 538251018Sgonzo << RASTER_TIMING_2_LPP_B10_SHIFT; 539251018Sgonzo 540251018Sgonzo /* clock signal settings */ 541251018Sgonzo if (panel.sync_ctrl) 542251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS; 543251018Sgonzo if (panel.sync_edge) 544251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS_RISE; 545251018Sgonzo else 546251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS_FALL; 547251018Sgonzo if (panel.invert_line_clock) 548251018Sgonzo timing2 |= RASTER_TIMING_2_IHS; 549251018Sgonzo if (panel.invert_frm_clock) 550251018Sgonzo timing2 |= RASTER_TIMING_2_IVS; 551251018Sgonzo if (panel.panel_invert_pxl_clk) 552251018Sgonzo timing2 |= RASTER_TIMING_2_IPC; 553251018Sgonzo 554251018Sgonzo /* AC bias */ 555251018Sgonzo timing2 |= (panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); 556251018Sgonzo timing2 |= (panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); 557251018Sgonzo 558251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); 559251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); 560251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); 561251018Sgonzo 562251018Sgonzo /* DMA settings */ 563251018Sgonzo reg = LCDDMA_CTRL_FB0_FB1; 564251018Sgonzo /* Find power of 2 for current burst size */ 565251018Sgonzo switch (panel.dma_burst_sz) { 566251018Sgonzo case 1: 567251018Sgonzo burst_log = 0; 568251018Sgonzo break; 569251018Sgonzo case 2: 570251018Sgonzo burst_log = 1; 571251018Sgonzo break; 572251018Sgonzo case 4: 573251018Sgonzo burst_log = 2; 574251018Sgonzo break; 575251018Sgonzo case 8: 576251018Sgonzo burst_log = 3; 577251018Sgonzo break; 578251018Sgonzo case 16: 579251018Sgonzo default: 580251018Sgonzo burst_log = 4; 581251018Sgonzo break; 582251018Sgonzo } 583251018Sgonzo reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); 584251018Sgonzo /* XXX: FIFO TH */ 585251018Sgonzo reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); 586251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); 587251018Sgonzo 588251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 589251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 590251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 591251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 592251018Sgonzo 593251018Sgonzo /* Enable LCD */ 594251018Sgonzo reg = RASTER_CTRL_LCDTFT; 595251018Sgonzo reg |= (panel.fdd << RASTER_CTRL_REQDLY_SHIFT); 596251018Sgonzo reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); 597251018Sgonzo if (panel.bpp >= 24) 598251018Sgonzo reg |= RASTER_CTRL_TFT24; 599251018Sgonzo if (panel.bpp == 32) 600251018Sgonzo reg |= RASTER_CTRL_TFT24_UNPACKED; 601251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 602251018Sgonzo 603251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_ENABLE, 604251018Sgonzo CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); 605251018Sgonzo 606251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); 607251018Sgonzo DELAY(100); 608251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_RESET, 0); 609251018Sgonzo 610251018Sgonzo reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | 611251018Sgonzo IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | 612251018Sgonzo IRQ_FRAME_DONE; 613251018Sgonzo LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); 614251018Sgonzo 615251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 616251018Sgonzo reg |= RASTER_CTRL_LCDEN; 617251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 618251018Sgonzo 619251018Sgonzo LCD_WRITE4(sc, LCD_SYSCONFIG, 620251018Sgonzo SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); 621251018Sgonzo 622251018Sgonzo /* Init backlight interface */ 623251018Sgonzo ctx = device_get_sysctl_ctx(sc->sc_dev); 624251018Sgonzo tree = device_get_sysctl_tree(sc->sc_dev); 625251018Sgonzo sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 626251018Sgonzo "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 627251018Sgonzo am335x_lcd_sysctl_backlight, "I", "LCD backlight"); 628251018Sgonzo sc->sc_backlight = 0; 629251018Sgonzo /* Check if eCAS interface is available at this point */ 630251018Sgonzo if (am335x_pwm_config_ecas(PWM_UNIT, 631251018Sgonzo PWM_PERIOD, PWM_PERIOD) == 0) 632251018Sgonzo sc->sc_backlight = 100; 633251018Sgonzo 634251018Sgonzo am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); 635251018Sgonzo 636251018Sgonzo return (0); 637251018Sgonzo 638251018Sgonzofail: 639251018Sgonzo return (err); 640251018Sgonzo} 641251018Sgonzo 642251018Sgonzostatic int 643251018Sgonzoam335x_lcd_detach(device_t dev) 644251018Sgonzo{ 645251018Sgonzo /* Do not let unload driver */ 646251018Sgonzo return (EBUSY); 647251018Sgonzo} 648251018Sgonzo 649251018Sgonzostatic device_method_t am335x_lcd_methods[] = { 650251018Sgonzo DEVMETHOD(device_probe, am335x_lcd_probe), 651251018Sgonzo DEVMETHOD(device_attach, am335x_lcd_attach), 652251018Sgonzo DEVMETHOD(device_detach, am335x_lcd_detach), 653251018Sgonzo 654251018Sgonzo DEVMETHOD_END 655251018Sgonzo}; 656251018Sgonzo 657251018Sgonzostatic driver_t am335x_lcd_driver = { 658251018Sgonzo "am335x_lcd", 659251018Sgonzo am335x_lcd_methods, 660251018Sgonzo sizeof(struct am335x_lcd_softc), 661251018Sgonzo}; 662251018Sgonzo 663251018Sgonzostatic devclass_t am335x_lcd_devclass; 664251018Sgonzo 665251018SgonzoDRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); 666251018SgonzoMODULE_VERSION(am335x_lcd, 1); 667251018SgonzoMODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); 668