1251018Sgonzo/*- 2251018Sgonzo * Copyright 2013 Oleksandr Tymoshenko <gonzo@freebsd.org> 3251018Sgonzo * All rights reserved. 4251018Sgonzo * 5251018Sgonzo * Redistribution and use in source and binary forms, with or without 6251018Sgonzo * modification, are permitted provided that the following conditions 7251018Sgonzo * are met: 8251018Sgonzo * 1. Redistributions of source code must retain the above copyright 9251018Sgonzo * notice, this list of conditions and the following disclaimer. 10251018Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 11251018Sgonzo * notice, this list of conditions and the following disclaimer in the 12251018Sgonzo * documentation and/or other materials provided with the distribution. 13251018Sgonzo * 14251018Sgonzo * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15251018Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16251018Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17251018Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18251018Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19251018Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20251018Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21251018Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22251018Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23251018Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24251018Sgonzo * SUCH DAMAGE. 25251018Sgonzo */ 26251018Sgonzo 27251018Sgonzo#include <sys/cdefs.h> 28251018Sgonzo__FBSDID("$FreeBSD: stable/11/sys/arm/ti/am335x/am335x_lcd.c 314503 2017-03-01 18:53:05Z ian $"); 29251018Sgonzo 30277716Sgonzo#include "opt_syscons.h" 31251018Sgonzo#include <sys/param.h> 32251018Sgonzo#include <sys/systm.h> 33251018Sgonzo#include <sys/kernel.h> 34251018Sgonzo#include <sys/module.h> 35251018Sgonzo#include <sys/clock.h> 36251018Sgonzo#include <sys/time.h> 37251018Sgonzo#include <sys/bus.h> 38251018Sgonzo#include <sys/lock.h> 39251018Sgonzo#include <sys/mutex.h> 40251018Sgonzo#include <sys/resource.h> 41251018Sgonzo#include <sys/rman.h> 42251018Sgonzo#include <sys/sysctl.h> 43251018Sgonzo#include <vm/vm.h> 44251018Sgonzo#include <vm/pmap.h> 45252282Sgonzo#include <sys/fbio.h> 46252282Sgonzo#include <sys/consio.h> 47252282Sgonzo 48251018Sgonzo#include <machine/bus.h> 49251018Sgonzo 50251018Sgonzo#include <dev/fdt/fdt_common.h> 51251018Sgonzo#include <dev/ofw/openfirm.h> 52251018Sgonzo#include <dev/ofw/ofw_bus.h> 53251018Sgonzo#include <dev/ofw/ofw_bus_subr.h> 54251018Sgonzo 55284534Sgonzo#include <dev/videomode/videomode.h> 56284534Sgonzo#include <dev/videomode/edidvar.h> 57284534Sgonzo 58252282Sgonzo#include <dev/fb/fbreg.h> 59277716Sgonzo#ifdef DEV_SC 60252282Sgonzo#include <dev/syscons/syscons.h> 61277716Sgonzo#else /* VT */ 62277716Sgonzo#include <dev/vt/vt.h> 63277716Sgonzo#endif 64252282Sgonzo 65251018Sgonzo#include <arm/ti/ti_prcm.h> 66251018Sgonzo#include <arm/ti/ti_scm.h> 67251018Sgonzo 68251018Sgonzo#include "am335x_lcd.h" 69251018Sgonzo#include "am335x_pwm.h" 70251018Sgonzo 71277716Sgonzo#include "fb_if.h" 72284534Sgonzo#include "hdmi_if.h" 73277716Sgonzo 74251018Sgonzo#define LCD_PID 0x00 75251018Sgonzo#define LCD_CTRL 0x04 76251018Sgonzo#define CTRL_DIV_MASK 0xff 77251018Sgonzo#define CTRL_DIV_SHIFT 8 78251018Sgonzo#define CTRL_AUTO_UFLOW_RESTART (1 << 1) 79251018Sgonzo#define CTRL_RASTER_MODE 1 80251018Sgonzo#define CTRL_LIDD_MODE 0 81251018Sgonzo#define LCD_LIDD_CTRL 0x0C 82251018Sgonzo#define LCD_LIDD_CS0_CONF 0x10 83251018Sgonzo#define LCD_LIDD_CS0_ADDR 0x14 84251018Sgonzo#define LCD_LIDD_CS0_DATA 0x18 85251018Sgonzo#define LCD_LIDD_CS1_CONF 0x1C 86251018Sgonzo#define LCD_LIDD_CS1_ADDR 0x20 87251018Sgonzo#define LCD_LIDD_CS1_DATA 0x24 88251018Sgonzo#define LCD_RASTER_CTRL 0x28 89251018Sgonzo#define RASTER_CTRL_TFT24_UNPACKED (1 << 26) 90251018Sgonzo#define RASTER_CTRL_TFT24 (1 << 25) 91251018Sgonzo#define RASTER_CTRL_STN565 (1 << 24) 92251018Sgonzo#define RASTER_CTRL_TFTPMAP (1 << 23) 93251018Sgonzo#define RASTER_CTRL_NIBMODE (1 << 22) 94251018Sgonzo#define RASTER_CTRL_PALMODE_SHIFT 20 95251018Sgonzo#define PALETTE_PALETTE_AND_DATA 0x00 96251018Sgonzo#define PALETTE_PALETTE_ONLY 0x01 97251018Sgonzo#define PALETTE_DATA_ONLY 0x02 98251018Sgonzo#define RASTER_CTRL_REQDLY_SHIFT 12 99251018Sgonzo#define RASTER_CTRL_MONO8B (1 << 9) 100251018Sgonzo#define RASTER_CTRL_RBORDER (1 << 8) 101251018Sgonzo#define RASTER_CTRL_LCDTFT (1 << 7) 102251018Sgonzo#define RASTER_CTRL_LCDBW (1 << 1) 103251018Sgonzo#define RASTER_CTRL_LCDEN (1 << 0) 104251018Sgonzo#define LCD_RASTER_TIMING_0 0x2C 105251018Sgonzo#define RASTER_TIMING_0_HBP_SHIFT 24 106251018Sgonzo#define RASTER_TIMING_0_HFP_SHIFT 16 107251018Sgonzo#define RASTER_TIMING_0_HSW_SHIFT 10 108251018Sgonzo#define RASTER_TIMING_0_PPLLSB_SHIFT 4 109251018Sgonzo#define RASTER_TIMING_0_PPLMSB_SHIFT 3 110251018Sgonzo#define LCD_RASTER_TIMING_1 0x30 111251018Sgonzo#define RASTER_TIMING_1_VBP_SHIFT 24 112251018Sgonzo#define RASTER_TIMING_1_VFP_SHIFT 16 113251018Sgonzo#define RASTER_TIMING_1_VSW_SHIFT 10 114251018Sgonzo#define RASTER_TIMING_1_LPP_SHIFT 0 115251018Sgonzo#define LCD_RASTER_TIMING_2 0x34 116251018Sgonzo#define RASTER_TIMING_2_HSWHI_SHIFT 27 117251018Sgonzo#define RASTER_TIMING_2_LPP_B10_SHIFT 26 118251018Sgonzo#define RASTER_TIMING_2_PHSVS (1 << 25) 119251018Sgonzo#define RASTER_TIMING_2_PHSVS_RISE (1 << 24) 120251018Sgonzo#define RASTER_TIMING_2_PHSVS_FALL (0 << 24) 121251018Sgonzo#define RASTER_TIMING_2_IOE (1 << 23) 122251018Sgonzo#define RASTER_TIMING_2_IPC (1 << 22) 123251018Sgonzo#define RASTER_TIMING_2_IHS (1 << 21) 124251018Sgonzo#define RASTER_TIMING_2_IVS (1 << 20) 125251018Sgonzo#define RASTER_TIMING_2_ACBI_SHIFT 16 126251018Sgonzo#define RASTER_TIMING_2_ACB_SHIFT 8 127251018Sgonzo#define RASTER_TIMING_2_HBPHI_SHIFT 4 128251018Sgonzo#define RASTER_TIMING_2_HFPHI_SHIFT 0 129251018Sgonzo#define LCD_RASTER_SUBPANEL 0x38 130251018Sgonzo#define LCD_RASTER_SUBPANEL2 0x3C 131251018Sgonzo#define LCD_LCDDMA_CTRL 0x40 132251018Sgonzo#define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 133251018Sgonzo#define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 134251018Sgonzo#define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 135251018Sgonzo#define LCDDMA_CTRL_BYTES_SWAP (1 << 3) 136251018Sgonzo#define LCDDMA_CTRL_BE (1 << 1) 137251018Sgonzo#define LCDDMA_CTRL_FB0_ONLY 0 138251018Sgonzo#define LCDDMA_CTRL_FB0_FB1 (1 << 0) 139251018Sgonzo#define LCD_LCDDMA_FB0_BASE 0x44 140251018Sgonzo#define LCD_LCDDMA_FB0_CEILING 0x48 141251018Sgonzo#define LCD_LCDDMA_FB1_BASE 0x4C 142251018Sgonzo#define LCD_LCDDMA_FB1_CEILING 0x50 143251018Sgonzo#define LCD_SYSCONFIG 0x54 144251018Sgonzo#define SYSCONFIG_STANDBY_FORCE (0 << 4) 145251018Sgonzo#define SYSCONFIG_STANDBY_NONE (1 << 4) 146251018Sgonzo#define SYSCONFIG_STANDBY_SMART (2 << 4) 147251018Sgonzo#define SYSCONFIG_IDLE_FORCE (0 << 2) 148251018Sgonzo#define SYSCONFIG_IDLE_NONE (1 << 2) 149251018Sgonzo#define SYSCONFIG_IDLE_SMART (2 << 2) 150251018Sgonzo#define LCD_IRQSTATUS_RAW 0x58 151251018Sgonzo#define LCD_IRQSTATUS 0x5C 152251018Sgonzo#define LCD_IRQENABLE_SET 0x60 153251018Sgonzo#define LCD_IRQENABLE_CLEAR 0x64 154251018Sgonzo#define IRQ_EOF1 (1 << 9) 155251018Sgonzo#define IRQ_EOF0 (1 << 8) 156251018Sgonzo#define IRQ_PL (1 << 6) 157251018Sgonzo#define IRQ_FUF (1 << 5) 158251018Sgonzo#define IRQ_ACB (1 << 3) 159251018Sgonzo#define IRQ_SYNC_LOST (1 << 2) 160251018Sgonzo#define IRQ_RASTER_DONE (1 << 1) 161251018Sgonzo#define IRQ_FRAME_DONE (1 << 0) 162277405Sgonzo#define LCD_END_OF_INT_IND 0x68 163251018Sgonzo#define LCD_CLKC_ENABLE 0x6C 164251018Sgonzo#define CLKC_ENABLE_DMA (1 << 2) 165251018Sgonzo#define CLKC_ENABLE_LDID (1 << 1) 166251018Sgonzo#define CLKC_ENABLE_CORE (1 << 0) 167251018Sgonzo#define LCD_CLKC_RESET 0x70 168251018Sgonzo#define CLKC_RESET_MAIN (1 << 3) 169251018Sgonzo#define CLKC_RESET_DMA (1 << 2) 170251018Sgonzo#define CLKC_RESET_LDID (1 << 1) 171251018Sgonzo#define CLKC_RESET_CORE (1 << 0) 172251018Sgonzo 173251018Sgonzo#define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 174251018Sgonzo#define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 175251018Sgonzo#define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ 176251018Sgonzo device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) 177251018Sgonzo#define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); 178251018Sgonzo 179251018Sgonzo#define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); 180251018Sgonzo#define LCD_WRITE4(_sc, reg, value) \ 181251018Sgonzo bus_write_4((_sc)->sc_mem_res, reg, value); 182251018Sgonzo 183251018Sgonzo/* Backlight is controlled by eCAS interface on PWM unit 0 */ 184251018Sgonzo#define PWM_UNIT 0 185251018Sgonzo#define PWM_PERIOD 100 186251018Sgonzo 187284534Sgonzo#define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) 188284534Sgonzo#define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) 189284534Sgonzo#define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) 190284534Sgonzo#define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) 191284534Sgonzo#define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) 192284534Sgonzo#define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) 193284534Sgonzo 194284534Sgonzo#define MAX_PIXEL_CLOCK 126000 195284534Sgonzo#define MAX_BANDWIDTH (1280*1024*60) 196284534Sgonzo 197251018Sgonzostruct am335x_lcd_softc { 198251018Sgonzo device_t sc_dev; 199277716Sgonzo struct fb_info sc_fb_info; 200251018Sgonzo struct resource *sc_mem_res; 201251018Sgonzo struct resource *sc_irq_res; 202251018Sgonzo void *sc_intr_hl; 203251018Sgonzo struct mtx sc_mtx; 204251018Sgonzo int sc_backlight; 205251018Sgonzo struct sysctl_oid *sc_oid; 206251018Sgonzo 207284534Sgonzo struct panel_info sc_panel; 208284534Sgonzo 209251018Sgonzo /* Framebuffer */ 210251018Sgonzo bus_dma_tag_t sc_dma_tag; 211251018Sgonzo bus_dmamap_t sc_dma_map; 212251018Sgonzo size_t sc_fb_size; 213251018Sgonzo bus_addr_t sc_fb_phys; 214251018Sgonzo uint8_t *sc_fb_base; 215284534Sgonzo 216284534Sgonzo /* HDMI framer */ 217284534Sgonzo phandle_t sc_hdmi_framer; 218284534Sgonzo eventhandler_tag sc_hdmi_evh; 219251018Sgonzo}; 220251018Sgonzo 221251018Sgonzostatic void 222251018Sgonzoam335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 223251018Sgonzo{ 224251018Sgonzo bus_addr_t *addr; 225251018Sgonzo 226251018Sgonzo if (err) 227251018Sgonzo return; 228251018Sgonzo 229251018Sgonzo addr = (bus_addr_t*)arg; 230251018Sgonzo *addr = segs[0].ds_addr; 231251018Sgonzo} 232251018Sgonzo 233251018Sgonzostatic uint32_t 234251018Sgonzoam335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) 235251018Sgonzo{ 236284534Sgonzo uint32_t div, i; 237284534Sgonzo uint32_t delta, min_delta; 238284534Sgonzo 239284534Sgonzo min_delta = freq; 240284534Sgonzo div = 255; 241284534Sgonzo 242251018Sgonzo /* Raster mode case: divisors are in range from 2 to 255 */ 243284534Sgonzo for (i = 2; i < 255; i++) { 244284534Sgonzo delta = abs(reference/i - freq); 245284534Sgonzo if (delta < min_delta) { 246284534Sgonzo div = i; 247284534Sgonzo min_delta = delta; 248284534Sgonzo } 249284534Sgonzo } 250251018Sgonzo 251284534Sgonzo return (div); 252251018Sgonzo} 253251018Sgonzo 254251018Sgonzostatic int 255251018Sgonzoam335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) 256251018Sgonzo{ 257251018Sgonzo struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; 258251018Sgonzo int error; 259251018Sgonzo int backlight; 260284534Sgonzo 261267171Skevlo backlight = sc->sc_backlight; 262251018Sgonzo error = sysctl_handle_int(oidp, &backlight, 0, req); 263251018Sgonzo 264251018Sgonzo if (error != 0 || req->newptr == NULL) 265251018Sgonzo return (error); 266251018Sgonzo 267251018Sgonzo if (backlight < 0) 268251018Sgonzo backlight = 0; 269251018Sgonzo if (backlight > 100) 270251018Sgonzo backlight = 100; 271251018Sgonzo 272251018Sgonzo LCD_LOCK(sc); 273283276Sgonzo error = am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD, 274251018Sgonzo backlight*PWM_PERIOD/100); 275251018Sgonzo if (error == 0) 276251018Sgonzo sc->sc_backlight = backlight; 277251018Sgonzo LCD_UNLOCK(sc); 278251018Sgonzo 279251018Sgonzo return (error); 280251018Sgonzo} 281251018Sgonzo 282284534Sgonzostatic uint32_t 283284534Sgonzoam335x_mode_vrefresh(const struct videomode *mode) 284284534Sgonzo{ 285284534Sgonzo uint32_t refresh; 286284534Sgonzo 287284534Sgonzo /* Calculate vertical refresh rate */ 288284534Sgonzo refresh = (mode->dot_clock * 1000 / mode->htotal); 289284534Sgonzo refresh = (refresh + mode->vtotal / 2) / mode->vtotal; 290284534Sgonzo 291284534Sgonzo if (mode->flags & VID_INTERLACE) 292284534Sgonzo refresh *= 2; 293284534Sgonzo if (mode->flags & VID_DBLSCAN) 294284534Sgonzo refresh /= 2; 295284534Sgonzo 296284534Sgonzo return refresh; 297284534Sgonzo} 298284534Sgonzo 299251018Sgonzostatic int 300284534Sgonzoam335x_mode_is_valid(const struct videomode *mode) 301284534Sgonzo{ 302284534Sgonzo uint32_t hbp, hfp, hsw; 303284534Sgonzo uint32_t vbp, vfp, vsw; 304284534Sgonzo 305284534Sgonzo if (mode->dot_clock > MAX_PIXEL_CLOCK) 306284534Sgonzo return (0); 307284534Sgonzo 308284534Sgonzo if (mode->hdisplay & 0xf) 309284534Sgonzo return (0); 310284534Sgonzo 311284534Sgonzo if (mode->vdisplay > 2048) 312284534Sgonzo return (0); 313284534Sgonzo 314284534Sgonzo /* Check ranges for timing parameters */ 315284534Sgonzo hbp = MODE_HBP(mode) - 1; 316284534Sgonzo hfp = MODE_HFP(mode) - 1; 317284534Sgonzo hsw = MODE_HSW(mode) - 1; 318284534Sgonzo vbp = MODE_VBP(mode); 319284534Sgonzo vfp = MODE_VFP(mode); 320284534Sgonzo vsw = MODE_VSW(mode) - 1; 321284534Sgonzo 322284534Sgonzo if (hbp > 0x3ff) 323284534Sgonzo return (0); 324284534Sgonzo if (hfp > 0x3ff) 325284534Sgonzo return (0); 326284534Sgonzo if (hsw > 0x3ff) 327284534Sgonzo return (0); 328284534Sgonzo 329284534Sgonzo if (vbp > 0xff) 330284534Sgonzo return (0); 331284534Sgonzo if (vfp > 0xff) 332284534Sgonzo return (0); 333284534Sgonzo if (vsw > 0x3f) 334284534Sgonzo return (0); 335284534Sgonzo if (mode->vdisplay*mode->hdisplay*am335x_mode_vrefresh(mode) 336284534Sgonzo > MAX_BANDWIDTH) 337284534Sgonzo return (0); 338284534Sgonzo 339284534Sgonzo return (1); 340284534Sgonzo} 341284534Sgonzo 342284534Sgonzostatic void 343284534Sgonzoam335x_read_hdmi_property(device_t dev) 344284534Sgonzo{ 345284534Sgonzo phandle_t node; 346284534Sgonzo phandle_t hdmi_xref; 347284534Sgonzo struct am335x_lcd_softc *sc; 348284534Sgonzo 349284534Sgonzo sc = device_get_softc(dev); 350284534Sgonzo node = ofw_bus_get_node(dev); 351284534Sgonzo if (OF_getencprop(node, "hdmi", &hdmi_xref, sizeof(hdmi_xref)) == -1) 352284534Sgonzo sc->sc_hdmi_framer = 0; 353284534Sgonzo else 354284534Sgonzo sc->sc_hdmi_framer = hdmi_xref; 355284534Sgonzo} 356284534Sgonzo 357284534Sgonzostatic int 358283276Sgonzoam335x_read_property(device_t dev, phandle_t node, const char *name, uint32_t *val) 359251018Sgonzo{ 360251018Sgonzo pcell_t cell; 361251018Sgonzo 362314503Sian if ((OF_getencprop(node, name, &cell, sizeof(cell))) <= 0) { 363251018Sgonzo device_printf(dev, "missing '%s' attribute in LCD panel info\n", 364251018Sgonzo name); 365251018Sgonzo return (ENXIO); 366251018Sgonzo } 367251018Sgonzo 368314503Sian *val = cell; 369251018Sgonzo 370251018Sgonzo return (0); 371251018Sgonzo} 372251018Sgonzo 373251018Sgonzostatic int 374283276Sgonzoam335x_read_timing(device_t dev, phandle_t node, struct panel_info *panel) 375251018Sgonzo{ 376251018Sgonzo int error; 377283276Sgonzo phandle_t timings_node, timing_node, native; 378251018Sgonzo 379283503Sgonzo timings_node = ofw_bus_find_child(node, "display-timings"); 380283276Sgonzo if (timings_node == 0) { 381283276Sgonzo device_printf(dev, "no \"display-timings\" node\n"); 382283276Sgonzo return (-1); 383283276Sgonzo } 384283276Sgonzo 385283276Sgonzo if (OF_searchencprop(timings_node, "native-mode", &native, 386283276Sgonzo sizeof(native)) == -1) { 387283276Sgonzo device_printf(dev, "no \"native-mode\" reference in \"timings\" node\n"); 388283276Sgonzo return (-1); 389283276Sgonzo } 390283276Sgonzo 391283276Sgonzo timing_node = OF_node_from_xref(native); 392283276Sgonzo 393251018Sgonzo error = 0; 394283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 395283276Sgonzo "hactive", &panel->panel_width))) 396251018Sgonzo goto out; 397251018Sgonzo 398283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 399283276Sgonzo "vactive", &panel->panel_height))) 400251018Sgonzo goto out; 401251018Sgonzo 402283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 403283276Sgonzo "hfront-porch", &panel->panel_hfp))) 404251018Sgonzo goto out; 405251018Sgonzo 406283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 407283276Sgonzo "hback-porch", &panel->panel_hbp))) 408251018Sgonzo goto out; 409251018Sgonzo 410283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 411283276Sgonzo "hsync-len", &panel->panel_hsw))) 412251018Sgonzo goto out; 413251018Sgonzo 414283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 415283276Sgonzo "vfront-porch", &panel->panel_vfp))) 416251018Sgonzo goto out; 417251018Sgonzo 418283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 419283276Sgonzo "vback-porch", &panel->panel_vbp))) 420251018Sgonzo goto out; 421251018Sgonzo 422283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 423283276Sgonzo "vsync-len", &panel->panel_vsw))) 424251018Sgonzo goto out; 425251018Sgonzo 426283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 427283276Sgonzo "clock-frequency", &panel->panel_pxl_clk))) 428251018Sgonzo goto out; 429251018Sgonzo 430283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 431283276Sgonzo "pixelclk-active", &panel->pixelclk_active))) 432251018Sgonzo goto out; 433251018Sgonzo 434283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 435283276Sgonzo "hsync-active", &panel->hsync_active))) 436251018Sgonzo goto out; 437251018Sgonzo 438283276Sgonzo if ((error = am335x_read_property(dev, timing_node, 439283276Sgonzo "vsync-active", &panel->vsync_active))) 440251018Sgonzo goto out; 441251018Sgonzo 442283276Sgonzoout: 443283276Sgonzo return (error); 444283276Sgonzo} 445283276Sgonzo 446283276Sgonzostatic int 447283276Sgonzoam335x_read_panel_info(device_t dev, phandle_t node, struct panel_info *panel) 448283276Sgonzo{ 449283276Sgonzo phandle_t panel_info_node; 450283276Sgonzo 451283503Sgonzo panel_info_node = ofw_bus_find_child(node, "panel-info"); 452283276Sgonzo if (panel_info_node == 0) 453283276Sgonzo return (-1); 454283276Sgonzo 455284534Sgonzo am335x_read_property(dev, panel_info_node, 456284534Sgonzo "ac-bias", &panel->ac_bias); 457283276Sgonzo 458284534Sgonzo am335x_read_property(dev, panel_info_node, 459284534Sgonzo "ac-bias-intrpt", &panel->ac_bias_intrpt); 460251018Sgonzo 461284534Sgonzo am335x_read_property(dev, panel_info_node, 462284534Sgonzo "dma-burst-sz", &panel->dma_burst_sz); 463251018Sgonzo 464284534Sgonzo am335x_read_property(dev, panel_info_node, 465284534Sgonzo "bpp", &panel->bpp); 466251018Sgonzo 467284534Sgonzo am335x_read_property(dev, panel_info_node, 468284534Sgonzo "fdd", &panel->fdd); 469251018Sgonzo 470284534Sgonzo am335x_read_property(dev, panel_info_node, 471284534Sgonzo "sync-edge", &panel->sync_edge); 472251018Sgonzo 473284534Sgonzo am335x_read_property(dev, panel_info_node, 474283276Sgonzo "sync-ctrl", &panel->sync_ctrl); 475251018Sgonzo 476284534Sgonzo return (0); 477251018Sgonzo} 478251018Sgonzo 479251018Sgonzostatic void 480251018Sgonzoam335x_lcd_intr(void *arg) 481251018Sgonzo{ 482251018Sgonzo struct am335x_lcd_softc *sc = arg; 483251018Sgonzo uint32_t reg; 484251018Sgonzo 485251018Sgonzo reg = LCD_READ4(sc, LCD_IRQSTATUS); 486251018Sgonzo LCD_WRITE4(sc, LCD_IRQSTATUS, reg); 487277632Sgonzo /* Read value back to make sure it reached the hardware */ 488277632Sgonzo reg = LCD_READ4(sc, LCD_IRQSTATUS); 489251018Sgonzo 490251018Sgonzo if (reg & IRQ_SYNC_LOST) { 491251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 492251018Sgonzo reg &= ~RASTER_CTRL_LCDEN; 493251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 494251018Sgonzo 495251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 496251018Sgonzo reg |= RASTER_CTRL_LCDEN; 497251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 498277522Sgonzo goto done; 499251018Sgonzo } 500251018Sgonzo 501251018Sgonzo if (reg & IRQ_PL) { 502251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 503251018Sgonzo reg &= ~RASTER_CTRL_LCDEN; 504251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 505251018Sgonzo 506251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 507251018Sgonzo reg |= RASTER_CTRL_LCDEN; 508251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 509277522Sgonzo goto done; 510251018Sgonzo } 511251018Sgonzo 512251018Sgonzo if (reg & IRQ_EOF0) { 513251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 514251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 515251018Sgonzo reg &= ~IRQ_EOF0; 516251018Sgonzo } 517251018Sgonzo 518251018Sgonzo if (reg & IRQ_EOF1) { 519251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 520251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 521251018Sgonzo reg &= ~IRQ_EOF1; 522251018Sgonzo } 523251018Sgonzo 524251018Sgonzo if (reg & IRQ_FUF) { 525251018Sgonzo /* TODO: Handle FUF */ 526251018Sgonzo } 527251018Sgonzo 528251018Sgonzo if (reg & IRQ_ACB) { 529251018Sgonzo /* TODO: Handle ACB */ 530251018Sgonzo } 531277405Sgonzo 532277522Sgonzodone: 533277405Sgonzo LCD_WRITE4(sc, LCD_END_OF_INT_IND, 0); 534277632Sgonzo /* Read value back to make sure it reached the hardware */ 535277632Sgonzo reg = LCD_READ4(sc, LCD_END_OF_INT_IND); 536251018Sgonzo} 537251018Sgonzo 538284534Sgonzostatic const struct videomode * 539284534Sgonzoam335x_lcd_pick_mode(struct edid_info *ei) 540251018Sgonzo{ 541284534Sgonzo const struct videomode *videomode; 542284534Sgonzo const struct videomode *m; 543284534Sgonzo int n; 544252282Sgonzo 545284534Sgonzo /* Get standard VGA as default */ 546284534Sgonzo videomode = NULL; 547261410Sian 548284534Sgonzo /* 549284534Sgonzo * Pick a mode. 550284534Sgonzo */ 551284534Sgonzo if (ei->edid_preferred_mode != NULL) { 552284534Sgonzo if (am335x_mode_is_valid(ei->edid_preferred_mode)) 553284534Sgonzo videomode = ei->edid_preferred_mode; 554284534Sgonzo } 555251018Sgonzo 556284534Sgonzo if (videomode == NULL) { 557284534Sgonzo m = ei->edid_modes; 558251018Sgonzo 559284534Sgonzo sort_modes(ei->edid_modes, 560284534Sgonzo &ei->edid_preferred_mode, 561284534Sgonzo ei->edid_nmodes); 562284534Sgonzo for (n = 0; n < ei->edid_nmodes; n++) 563284534Sgonzo if (am335x_mode_is_valid(&m[n])) { 564284534Sgonzo videomode = &m[n]; 565284534Sgonzo break; 566284534Sgonzo } 567284534Sgonzo } 568252282Sgonzo 569284534Sgonzo return videomode; 570251018Sgonzo} 571251018Sgonzo 572251018Sgonzostatic int 573284534Sgonzoam335x_lcd_configure(struct am335x_lcd_softc *sc) 574251018Sgonzo{ 575251018Sgonzo int div; 576251018Sgonzo uint32_t reg, timing0, timing1, timing2; 577251018Sgonzo uint32_t burst_log; 578251018Sgonzo size_t dma_size; 579277313Sgonzo uint32_t hbp, hfp, hsw; 580277313Sgonzo uint32_t vbp, vfp, vsw; 581277313Sgonzo uint32_t width, height; 582284534Sgonzo unsigned int ref_freq; 583284534Sgonzo int err; 584251018Sgonzo 585284534Sgonzo /* 586284534Sgonzo * try to adjust clock to get double of requested frequency 587284534Sgonzo * HDMI/DVI displays are very sensitive to error in frequncy value 588284534Sgonzo */ 589284534Sgonzo if (ti_prcm_clk_set_source_freq(LCDC_CLK, sc->sc_panel.panel_pxl_clk*2)) { 590284534Sgonzo device_printf(sc->sc_dev, "can't set source frequency\n"); 591251018Sgonzo return (ENXIO); 592283276Sgonzo } 593251018Sgonzo 594251018Sgonzo if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { 595284534Sgonzo device_printf(sc->sc_dev, "can't get reference frequency\n"); 596251018Sgonzo return (ENXIO); 597251018Sgonzo } 598251018Sgonzo 599251018Sgonzo /* Panle initialization */ 600284534Sgonzo dma_size = round_page(sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8); 601251018Sgonzo 602251018Sgonzo /* 603251018Sgonzo * Now allocate framebuffer memory 604251018Sgonzo */ 605251018Sgonzo err = bus_dma_tag_create( 606284534Sgonzo bus_get_dma_tag(sc->sc_dev), 607251018Sgonzo 4, 0, /* alignment, boundary */ 608251018Sgonzo BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 609251018Sgonzo BUS_SPACE_MAXADDR, /* highaddr */ 610251018Sgonzo NULL, NULL, /* filter, filterarg */ 611251018Sgonzo dma_size, 1, /* maxsize, nsegments */ 612251018Sgonzo dma_size, 0, /* maxsegsize, flags */ 613251018Sgonzo NULL, NULL, /* lockfunc, lockarg */ 614251018Sgonzo &sc->sc_dma_tag); 615251018Sgonzo if (err) 616284534Sgonzo goto done; 617251018Sgonzo 618251018Sgonzo err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, 619252282Sgonzo BUS_DMA_COHERENT, &sc->sc_dma_map); 620251018Sgonzo 621251018Sgonzo if (err) { 622284534Sgonzo device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); 623284534Sgonzo goto done; 624251018Sgonzo } 625251018Sgonzo 626251018Sgonzo err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, 627251018Sgonzo dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); 628251018Sgonzo 629251018Sgonzo if (err) { 630284534Sgonzo device_printf(sc->sc_dev, "cannot load DMA map\n"); 631284534Sgonzo goto done; 632251018Sgonzo } 633251018Sgonzo 634251018Sgonzo /* Make sure it's blank */ 635284534Sgonzo memset(sc->sc_fb_base, 0x0, dma_size); 636251018Sgonzo 637251018Sgonzo /* Calculate actual FB Size */ 638284534Sgonzo sc->sc_fb_size = sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8; 639251018Sgonzo 640251018Sgonzo /* Only raster mode is supported */ 641251018Sgonzo reg = CTRL_RASTER_MODE; 642284534Sgonzo div = am335x_lcd_calc_divisor(ref_freq, sc->sc_panel.panel_pxl_clk); 643251018Sgonzo reg |= (div << CTRL_DIV_SHIFT); 644251018Sgonzo LCD_WRITE4(sc, LCD_CTRL, reg); 645251018Sgonzo 646251018Sgonzo /* Set timing */ 647251018Sgonzo timing0 = timing1 = timing2 = 0; 648251018Sgonzo 649284534Sgonzo hbp = sc->sc_panel.panel_hbp - 1; 650284534Sgonzo hfp = sc->sc_panel.panel_hfp - 1; 651284534Sgonzo hsw = sc->sc_panel.panel_hsw - 1; 652277313Sgonzo 653284534Sgonzo vbp = sc->sc_panel.panel_vbp; 654284534Sgonzo vfp = sc->sc_panel.panel_vfp; 655284534Sgonzo vsw = sc->sc_panel.panel_vsw - 1; 656277313Sgonzo 657284534Sgonzo height = sc->sc_panel.panel_height - 1; 658284534Sgonzo width = sc->sc_panel.panel_width - 1; 659277313Sgonzo 660251018Sgonzo /* Horizontal back porch */ 661277313Sgonzo timing0 |= (hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; 662277313Sgonzo timing2 |= ((hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; 663251018Sgonzo /* Horizontal front porch */ 664277313Sgonzo timing0 |= (hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; 665277313Sgonzo timing2 |= ((hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; 666251018Sgonzo /* Horizontal sync width */ 667277313Sgonzo timing0 |= (hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; 668277313Sgonzo timing2 |= ((hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; 669251018Sgonzo 670251018Sgonzo /* Vertical back porch, front porch, sync width */ 671277313Sgonzo timing1 |= (vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; 672277313Sgonzo timing1 |= (vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; 673277313Sgonzo timing1 |= (vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; 674251018Sgonzo 675251018Sgonzo /* Pixels per line */ 676277313Sgonzo timing0 |= ((width >> 10) & 1) 677251018Sgonzo << RASTER_TIMING_0_PPLMSB_SHIFT; 678277313Sgonzo timing0 |= ((width >> 4) & 0x3f) 679251018Sgonzo << RASTER_TIMING_0_PPLLSB_SHIFT; 680251018Sgonzo 681251018Sgonzo /* Lines per panel */ 682277313Sgonzo timing1 |= (height & 0x3ff) 683251018Sgonzo << RASTER_TIMING_1_LPP_SHIFT; 684277313Sgonzo timing2 |= ((height >> 10 ) & 1) 685251018Sgonzo << RASTER_TIMING_2_LPP_B10_SHIFT; 686251018Sgonzo 687251018Sgonzo /* clock signal settings */ 688284534Sgonzo if (sc->sc_panel.sync_ctrl) 689251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS; 690284534Sgonzo if (sc->sc_panel.sync_edge) 691251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS_RISE; 692251018Sgonzo else 693251018Sgonzo timing2 |= RASTER_TIMING_2_PHSVS_FALL; 694284534Sgonzo if (sc->sc_panel.hsync_active == 0) 695251018Sgonzo timing2 |= RASTER_TIMING_2_IHS; 696284534Sgonzo if (sc->sc_panel.vsync_active == 0) 697251018Sgonzo timing2 |= RASTER_TIMING_2_IVS; 698284534Sgonzo if (sc->sc_panel.pixelclk_active == 0) 699251018Sgonzo timing2 |= RASTER_TIMING_2_IPC; 700251018Sgonzo 701251018Sgonzo /* AC bias */ 702284534Sgonzo timing2 |= (sc->sc_panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); 703284534Sgonzo timing2 |= (sc->sc_panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); 704251018Sgonzo 705251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); 706251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); 707251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); 708251018Sgonzo 709251018Sgonzo /* DMA settings */ 710251018Sgonzo reg = LCDDMA_CTRL_FB0_FB1; 711251018Sgonzo /* Find power of 2 for current burst size */ 712284534Sgonzo switch (sc->sc_panel.dma_burst_sz) { 713251018Sgonzo case 1: 714251018Sgonzo burst_log = 0; 715251018Sgonzo break; 716251018Sgonzo case 2: 717251018Sgonzo burst_log = 1; 718251018Sgonzo break; 719251018Sgonzo case 4: 720251018Sgonzo burst_log = 2; 721251018Sgonzo break; 722251018Sgonzo case 8: 723251018Sgonzo burst_log = 3; 724251018Sgonzo break; 725251018Sgonzo case 16: 726251018Sgonzo default: 727251018Sgonzo burst_log = 4; 728251018Sgonzo break; 729251018Sgonzo } 730251018Sgonzo reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); 731251018Sgonzo /* XXX: FIFO TH */ 732251018Sgonzo reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); 733251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); 734251018Sgonzo 735251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); 736251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 737251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); 738251018Sgonzo LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); 739251018Sgonzo 740251018Sgonzo /* Enable LCD */ 741251018Sgonzo reg = RASTER_CTRL_LCDTFT; 742284534Sgonzo reg |= (sc->sc_panel.fdd << RASTER_CTRL_REQDLY_SHIFT); 743251018Sgonzo reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); 744284534Sgonzo if (sc->sc_panel.bpp >= 24) 745251018Sgonzo reg |= RASTER_CTRL_TFT24; 746284534Sgonzo if (sc->sc_panel.bpp == 32) 747251018Sgonzo reg |= RASTER_CTRL_TFT24_UNPACKED; 748251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 749251018Sgonzo 750251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_ENABLE, 751251018Sgonzo CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); 752251018Sgonzo 753251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); 754251018Sgonzo DELAY(100); 755251018Sgonzo LCD_WRITE4(sc, LCD_CLKC_RESET, 0); 756251018Sgonzo 757251018Sgonzo reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | 758251018Sgonzo IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | 759251018Sgonzo IRQ_FRAME_DONE; 760251018Sgonzo LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); 761251018Sgonzo 762251018Sgonzo reg = LCD_READ4(sc, LCD_RASTER_CTRL); 763251018Sgonzo reg |= RASTER_CTRL_LCDEN; 764251018Sgonzo LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); 765251018Sgonzo 766251018Sgonzo LCD_WRITE4(sc, LCD_SYSCONFIG, 767251018Sgonzo SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); 768251018Sgonzo 769277716Sgonzo sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); 770277716Sgonzo sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; 771277716Sgonzo sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; 772277716Sgonzo sc->sc_fb_info.fb_size = sc->sc_fb_size; 773284534Sgonzo sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = sc->sc_panel.bpp; 774284534Sgonzo sc->sc_fb_info.fb_stride = sc->sc_panel.panel_width*sc->sc_panel.bpp / 8; 775284534Sgonzo sc->sc_fb_info.fb_width = sc->sc_panel.panel_width; 776284534Sgonzo sc->sc_fb_info.fb_height = sc->sc_panel.panel_height; 777277716Sgonzo 778277716Sgonzo#ifdef DEV_SC 779284534Sgonzo err = (sc_attach_unit(device_get_unit(sc->sc_dev), 780284534Sgonzo device_get_flags(sc->sc_dev) | SC_AUTODETECT_KBD)); 781252282Sgonzo 782252282Sgonzo if (err) { 783284534Sgonzo device_printf(sc->sc_dev, "failed to attach syscons\n"); 784252282Sgonzo goto fail; 785252282Sgonzo } 786252282Sgonzo 787251018Sgonzo am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); 788277716Sgonzo#else /* VT */ 789284534Sgonzo device_t fbd = device_add_child(sc->sc_dev, "fbd", 790284534Sgonzo device_get_unit(sc->sc_dev)); 791284534Sgonzo if (fbd != NULL) { 792284534Sgonzo if (device_probe_and_attach(fbd) != 0) 793284534Sgonzo device_printf(sc->sc_dev, "failed to attach fbd device\n"); 794284534Sgonzo } else 795284534Sgonzo device_printf(sc->sc_dev, "failed to add fbd child\n"); 796284534Sgonzo#endif 797284534Sgonzo 798284534Sgonzodone: 799284534Sgonzo return (err); 800284534Sgonzo} 801284534Sgonzo 802284534Sgonzostatic void 803290831Sgonzoam335x_lcd_hdmi_event(void *arg, device_t hdmi, int event) 804284534Sgonzo{ 805284534Sgonzo struct am335x_lcd_softc *sc; 806284534Sgonzo const struct videomode *videomode; 807284534Sgonzo struct videomode hdmi_mode; 808284534Sgonzo device_t hdmi_dev; 809284534Sgonzo uint8_t *edid; 810284534Sgonzo uint32_t edid_len; 811284534Sgonzo struct edid_info ei; 812284534Sgonzo 813284534Sgonzo sc = arg; 814284534Sgonzo 815284534Sgonzo /* Nothing to work with */ 816284534Sgonzo if (!sc->sc_hdmi_framer) { 817284534Sgonzo device_printf(sc->sc_dev, "HDMI event without HDMI framer set\n"); 818284534Sgonzo return; 819277716Sgonzo } 820284534Sgonzo 821284534Sgonzo hdmi_dev = OF_device_from_xref(sc->sc_hdmi_framer); 822284534Sgonzo if (!hdmi_dev) { 823284534Sgonzo device_printf(sc->sc_dev, "no actual device for \"hdmi\" property\n"); 824284534Sgonzo return; 825277716Sgonzo } 826284534Sgonzo 827284534Sgonzo edid = NULL; 828284534Sgonzo edid_len = 0; 829284534Sgonzo if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { 830284534Sgonzo device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); 831284534Sgonzo return; 832284534Sgonzo } 833284534Sgonzo 834284534Sgonzo videomode = NULL; 835284534Sgonzo 836284534Sgonzo if (edid_parse(edid, &ei) == 0) { 837284534Sgonzo edid_print(&ei); 838284534Sgonzo videomode = am335x_lcd_pick_mode(&ei); 839284534Sgonzo } else 840284534Sgonzo device_printf(sc->sc_dev, "failed to parse EDID\n"); 841284534Sgonzo 842284534Sgonzo /* Use standard VGA as fallback */ 843284534Sgonzo if (videomode == NULL) 844284534Sgonzo videomode = pick_mode_by_ref(640, 480, 60); 845284534Sgonzo 846284534Sgonzo if (videomode == NULL) { 847284534Sgonzo device_printf(sc->sc_dev, "failed to find usable videomode"); 848284534Sgonzo return; 849284534Sgonzo } 850284534Sgonzo 851284534Sgonzo device_printf(sc->sc_dev, "detected videomode: %dx%d @ %dKHz\n", videomode->hdisplay, 852284534Sgonzo videomode->vdisplay, am335x_mode_vrefresh(videomode)); 853284534Sgonzo 854284534Sgonzo sc->sc_panel.panel_width = videomode->hdisplay; 855284534Sgonzo sc->sc_panel.panel_height = videomode->vdisplay; 856284534Sgonzo sc->sc_panel.panel_hfp = videomode->hsync_start - videomode->hdisplay; 857284534Sgonzo sc->sc_panel.panel_hbp = videomode->htotal - videomode->hsync_end; 858284534Sgonzo sc->sc_panel.panel_hsw = videomode->hsync_end - videomode->hsync_start; 859284534Sgonzo sc->sc_panel.panel_vfp = videomode->vsync_start - videomode->vdisplay; 860284534Sgonzo sc->sc_panel.panel_vbp = videomode->vtotal - videomode->vsync_end; 861284534Sgonzo sc->sc_panel.panel_vsw = videomode->vsync_end - videomode->vsync_start; 862284534Sgonzo sc->sc_panel.pixelclk_active = 1; 863284534Sgonzo 864284534Sgonzo /* logic for HSYNC should be reversed */ 865284534Sgonzo if (videomode->flags & VID_NHSYNC) 866284534Sgonzo sc->sc_panel.hsync_active = 1; 867284534Sgonzo else 868284534Sgonzo sc->sc_panel.hsync_active = 0; 869284534Sgonzo 870284534Sgonzo if (videomode->flags & VID_NVSYNC) 871284534Sgonzo sc->sc_panel.vsync_active = 0; 872284534Sgonzo else 873284534Sgonzo sc->sc_panel.vsync_active = 1; 874284534Sgonzo 875284534Sgonzo sc->sc_panel.panel_pxl_clk = videomode->dot_clock * 1000; 876284534Sgonzo 877284534Sgonzo am335x_lcd_configure(sc); 878284534Sgonzo 879284534Sgonzo memcpy(&hdmi_mode, videomode, sizeof(hdmi_mode)); 880284534Sgonzo hdmi_mode.hskew = videomode->hsync_end - videomode->hsync_start; 881284534Sgonzo hdmi_mode.flags |= VID_HSKEW; 882284534Sgonzo 883284534Sgonzo HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode); 884284534Sgonzo} 885284534Sgonzo 886284534Sgonzostatic int 887284534Sgonzoam335x_lcd_probe(device_t dev) 888284534Sgonzo{ 889284534Sgonzo#ifdef DEV_SC 890284534Sgonzo int err; 891277716Sgonzo#endif 892251018Sgonzo 893284534Sgonzo if (!ofw_bus_status_okay(dev)) 894284534Sgonzo return (ENXIO); 895251018Sgonzo 896284534Sgonzo if (!ofw_bus_is_compatible(dev, "ti,am33xx-tilcdc")) 897284534Sgonzo return (ENXIO); 898284534Sgonzo 899284534Sgonzo device_set_desc(dev, "AM335x LCD controller"); 900284534Sgonzo 901284534Sgonzo#ifdef DEV_SC 902284534Sgonzo err = sc_probe_unit(device_get_unit(dev), 903284534Sgonzo device_get_flags(dev) | SC_AUTODETECT_KBD); 904284534Sgonzo if (err != 0) 905284534Sgonzo return (err); 906284534Sgonzo#endif 907284534Sgonzo 908284534Sgonzo return (BUS_PROBE_DEFAULT); 909251018Sgonzo} 910251018Sgonzo 911251018Sgonzostatic int 912284534Sgonzoam335x_lcd_attach(device_t dev) 913284534Sgonzo{ 914284534Sgonzo struct am335x_lcd_softc *sc; 915284534Sgonzo 916284534Sgonzo int err; 917284534Sgonzo int rid; 918284534Sgonzo struct sysctl_ctx_list *ctx; 919284534Sgonzo struct sysctl_oid *tree; 920284534Sgonzo phandle_t root, panel_node; 921284534Sgonzo 922284534Sgonzo err = 0; 923284534Sgonzo sc = device_get_softc(dev); 924284534Sgonzo sc->sc_dev = dev; 925284534Sgonzo 926284534Sgonzo am335x_read_hdmi_property(dev); 927284534Sgonzo 928284534Sgonzo root = OF_finddevice("/"); 929284534Sgonzo if (root == 0) { 930284534Sgonzo device_printf(dev, "failed to get FDT root node\n"); 931284534Sgonzo return (ENXIO); 932284534Sgonzo } 933284534Sgonzo 934284534Sgonzo sc->sc_panel.ac_bias = 255; 935284534Sgonzo sc->sc_panel.ac_bias_intrpt = 0; 936284534Sgonzo sc->sc_panel.dma_burst_sz = 16; 937284534Sgonzo sc->sc_panel.bpp = 16; 938284534Sgonzo sc->sc_panel.fdd = 128; 939284534Sgonzo sc->sc_panel.sync_edge = 0; 940284534Sgonzo sc->sc_panel.sync_ctrl = 1; 941284534Sgonzo 942284534Sgonzo panel_node = fdt_find_compatible(root, "ti,tilcdc,panel", 1); 943284534Sgonzo if (panel_node != 0) { 944284534Sgonzo device_printf(dev, "using static panel info\n"); 945284534Sgonzo if (am335x_read_panel_info(dev, panel_node, &sc->sc_panel)) { 946284534Sgonzo device_printf(dev, "failed to read panel info\n"); 947284534Sgonzo return (ENXIO); 948284534Sgonzo } 949284534Sgonzo 950284534Sgonzo if (am335x_read_timing(dev, panel_node, &sc->sc_panel)) { 951284534Sgonzo device_printf(dev, "failed to read timings\n"); 952284534Sgonzo return (ENXIO); 953284534Sgonzo } 954284534Sgonzo } 955284534Sgonzo 956284534Sgonzo ti_prcm_clk_enable(LCDC_CLK); 957284534Sgonzo 958284534Sgonzo rid = 0; 959284534Sgonzo sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 960284534Sgonzo RF_ACTIVE); 961284534Sgonzo if (!sc->sc_mem_res) { 962284534Sgonzo device_printf(dev, "cannot allocate memory window\n"); 963284534Sgonzo return (ENXIO); 964284534Sgonzo } 965284534Sgonzo 966284534Sgonzo rid = 0; 967284534Sgonzo sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 968284534Sgonzo RF_ACTIVE); 969284534Sgonzo if (!sc->sc_irq_res) { 970284534Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 971284534Sgonzo device_printf(dev, "cannot allocate interrupt\n"); 972284534Sgonzo return (ENXIO); 973284534Sgonzo } 974284534Sgonzo 975284534Sgonzo if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 976284534Sgonzo NULL, am335x_lcd_intr, sc, 977284534Sgonzo &sc->sc_intr_hl) != 0) { 978284534Sgonzo bus_release_resource(dev, SYS_RES_IRQ, rid, 979284534Sgonzo sc->sc_irq_res); 980284534Sgonzo bus_release_resource(dev, SYS_RES_MEMORY, rid, 981284534Sgonzo sc->sc_mem_res); 982284534Sgonzo device_printf(dev, "Unable to setup the irq handler.\n"); 983284534Sgonzo return (ENXIO); 984284534Sgonzo } 985284534Sgonzo 986284534Sgonzo LCD_LOCK_INIT(sc); 987284534Sgonzo 988284534Sgonzo /* Init backlight interface */ 989284534Sgonzo ctx = device_get_sysctl_ctx(sc->sc_dev); 990284534Sgonzo tree = device_get_sysctl_tree(sc->sc_dev); 991284534Sgonzo sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 992284534Sgonzo "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 993284534Sgonzo am335x_lcd_sysctl_backlight, "I", "LCD backlight"); 994284534Sgonzo sc->sc_backlight = 0; 995284534Sgonzo /* Check if eCAS interface is available at this point */ 996284534Sgonzo if (am335x_pwm_config_ecap(PWM_UNIT, 997284534Sgonzo PWM_PERIOD, PWM_PERIOD) == 0) 998284534Sgonzo sc->sc_backlight = 100; 999284534Sgonzo 1000285866Sgonzo if (panel_node != 0) 1001285866Sgonzo am335x_lcd_configure(sc); 1002285866Sgonzo else 1003285866Sgonzo sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, 1004290831Sgonzo am335x_lcd_hdmi_event, sc, EVENTHANDLER_PRI_ANY); 1005284534Sgonzo 1006284534Sgonzo return (0); 1007284534Sgonzo} 1008284534Sgonzo 1009284534Sgonzostatic int 1010251018Sgonzoam335x_lcd_detach(device_t dev) 1011251018Sgonzo{ 1012251018Sgonzo /* Do not let unload driver */ 1013251018Sgonzo return (EBUSY); 1014251018Sgonzo} 1015251018Sgonzo 1016277716Sgonzostatic struct fb_info * 1017277716Sgonzoam335x_lcd_fb_getinfo(device_t dev) 1018277716Sgonzo{ 1019277716Sgonzo struct am335x_lcd_softc *sc; 1020277716Sgonzo 1021277716Sgonzo sc = device_get_softc(dev); 1022277716Sgonzo 1023277716Sgonzo return (&sc->sc_fb_info); 1024277716Sgonzo} 1025277716Sgonzo 1026251018Sgonzostatic device_method_t am335x_lcd_methods[] = { 1027251018Sgonzo DEVMETHOD(device_probe, am335x_lcd_probe), 1028251018Sgonzo DEVMETHOD(device_attach, am335x_lcd_attach), 1029251018Sgonzo DEVMETHOD(device_detach, am335x_lcd_detach), 1030251018Sgonzo 1031277716Sgonzo /* Framebuffer service methods */ 1032277716Sgonzo DEVMETHOD(fb_getinfo, am335x_lcd_fb_getinfo), 1033277716Sgonzo 1034251018Sgonzo DEVMETHOD_END 1035251018Sgonzo}; 1036251018Sgonzo 1037251018Sgonzostatic driver_t am335x_lcd_driver = { 1038277716Sgonzo "fb", 1039251018Sgonzo am335x_lcd_methods, 1040251018Sgonzo sizeof(struct am335x_lcd_softc), 1041251018Sgonzo}; 1042251018Sgonzo 1043251018Sgonzostatic devclass_t am335x_lcd_devclass; 1044251018Sgonzo 1045251018SgonzoDRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); 1046251018SgonzoMODULE_VERSION(am335x_lcd, 1); 1047251018SgonzoMODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); 1048