am335x_dmtreg.h revision 314512
1/*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/11/sys/arm/ti/am335x/am335x_dmtreg.h 314512 2017-03-01 21:11:36Z ian $ 27 */ 28 29#ifndef AM335X_DMTREG_H 30#define AM335X_DMTREG_H 31 32#define AM335X_NUM_TIMERS 8 33 34#define DMT_TIDR 0x00 /* Identification Register */ 35#define DMT_TIOCP_CFG 0x10 /* OCP Configuration Reg */ 36#define DMT_TIOCP_RESET (1 << 0) /* TIOCP perform soft reset */ 37#define DMT_IQR_EOI 0x20 /* IRQ End-Of-Interrupt Reg */ 38#define DMT_IRQSTATUS_RAW 0x24 /* IRQSTATUS Raw Reg */ 39#define DMT_IRQSTATUS 0x28 /* IRQSTATUS Reg */ 40#define DMT_IRQENABLE_SET 0x2c /* IRQSTATUS Set Reg */ 41#define DMT_IRQENABLE_CLR 0x30 /* IRQSTATUS Clear Reg */ 42#define DMT_IRQWAKEEN 0x34 /* IRQ Wakeup Enable Reg */ 43#define DMT_IRQ_MAT (1 << 0) /* IRQ: Match */ 44#define DMT_IRQ_OVF (1 << 1) /* IRQ: Overflow */ 45#define DMT_IRQ_TCAR (1 << 2) /* IRQ: Capture */ 46#define DMT_IRQ_MASK (DMT_IRQ_TCAR | DMT_IRQ_OVF | DMT_IRQ_MAT) 47#define DMT_TCLR 0x38 /* Control Register */ 48#define DMT_TCLR_START (1 << 0) /* Start timer */ 49#define DMT_TCLR_AUTOLOAD (1 << 1) /* Auto-reload on overflow */ 50#define DMT_TCLR_PRES_MASK (7 << 2) /* Prescaler mask */ 51#define DMT_TCLR_PRES_ENABLE (1 << 5) /* Prescaler enable */ 52#define DMT_TCLR_COMP_ENABLE (1 << 6) /* Compare enable */ 53#define DMT_TCLR_PWM_HIGH (1 << 7) /* PWM default output high */ 54#define DMT_TCLR_CAPTRAN_MASK (3 << 8) /* Capture transition mask */ 55#define DMT_TCLR_CAPTRAN_NONE (0 << 8) /* Capture: none */ 56#define DMT_TCLR_CAPTRAN_LOHI (1 << 8) /* Capture lo->hi transition */ 57#define DMT_TCLR_CAPTRAN_HILO (2 << 8) /* Capture hi->lo transition */ 58#define DMT_TCLR_CAPTRAN_BOTH (3 << 8) /* Capture both transitions */ 59#define DMT_TCLR_TRGMODE_MASK (3 << 10) /* Trigger output mode mask */ 60#define DMT_TCLR_TRGMODE_NONE (0 << 10) /* Trigger off */ 61#define DMT_TCLR_TRGMODE_OVFL (1 << 10) /* Trigger on overflow */ 62#define DMT_TCLR_TRGMODE_BOTH (2 << 10) /* Trigger on match + ovflow */ 63#define DMT_TCLR_PWM_PTOGGLE (1 << 12) /* PWM toggles */ 64#define DMT_TCLR_CAP_MODE_2ND (1 << 13) /* Capture second event mode */ 65#define DMT_TCLR_GPO_CFG (1 << 14) /* Tmr pin conf, 0=out, 1=in */ 66#define DMT_TCRR 0x3C /* Counter Register */ 67#define DMT_TLDR 0x40 /* Load Reg */ 68#define DMT_TTGR 0x44 /* Trigger Reg */ 69#define DMT_TWPS 0x48 /* Write Posted Status Reg */ 70#define DMT_TMAR 0x4C /* Match Reg */ 71#define DMT_TCAR1 0x50 /* Capture Reg */ 72#define DMT_TSICR 0x54 /* Synchr. Interface Ctrl Reg */ 73#define DMT_TSICR_RESET (1 << 1) /* TSICR perform soft reset */ 74#define DMT_TCAR2 0x48 /* Capture Reg */ 75 76#endif /* AM335X_DMTREG_H */ 77