1286696Sian/*- 2286696Sian * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3286696Sian * All rights reserved. 4286696Sian * 5286696Sian * Redistribution and use in source and binary forms, with or without 6286696Sian * modification, are permitted provided that the following conditions 7286696Sian * are met: 8286696Sian * 1. Redistributions of source code must retain the above copyright 9286696Sian * notice, this list of conditions and the following disclaimer. 10286696Sian * 2. Redistributions in binary form must reproduce the above copyright 11286696Sian * notice, this list of conditions and the following disclaimer in the 12286696Sian * documentation and/or other materials provided with the distribution. 13286696Sian * 14286696Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15286696Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16286696Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17286696Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18286696Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19286696Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20286696Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21286696Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22286696Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23286696Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24286696Sian * SUCH DAMAGE. 25286696Sian * 26286696Sian * $FreeBSD: stable/11/sys/arm/ti/am335x/am335x_dmtreg.h 314512 2017-03-01 21:11:36Z ian $ 27286696Sian */ 28286696Sian 29286696Sian#ifndef AM335X_DMTREG_H 30286696Sian#define AM335X_DMTREG_H 31286696Sian 32286696Sian#define AM335X_NUM_TIMERS 8 33286696Sian 34286696Sian#define DMT_TIDR 0x00 /* Identification Register */ 35286696Sian#define DMT_TIOCP_CFG 0x10 /* OCP Configuration Reg */ 36286696Sian#define DMT_TIOCP_RESET (1 << 0) /* TIOCP perform soft reset */ 37286696Sian#define DMT_IQR_EOI 0x20 /* IRQ End-Of-Interrupt Reg */ 38286696Sian#define DMT_IRQSTATUS_RAW 0x24 /* IRQSTATUS Raw Reg */ 39286696Sian#define DMT_IRQSTATUS 0x28 /* IRQSTATUS Reg */ 40286696Sian#define DMT_IRQENABLE_SET 0x2c /* IRQSTATUS Set Reg */ 41286696Sian#define DMT_IRQENABLE_CLR 0x30 /* IRQSTATUS Clear Reg */ 42286696Sian#define DMT_IRQWAKEEN 0x34 /* IRQ Wakeup Enable Reg */ 43286696Sian#define DMT_IRQ_MAT (1 << 0) /* IRQ: Match */ 44286696Sian#define DMT_IRQ_OVF (1 << 1) /* IRQ: Overflow */ 45286696Sian#define DMT_IRQ_TCAR (1 << 2) /* IRQ: Capture */ 46286696Sian#define DMT_IRQ_MASK (DMT_IRQ_TCAR | DMT_IRQ_OVF | DMT_IRQ_MAT) 47286696Sian#define DMT_TCLR 0x38 /* Control Register */ 48286696Sian#define DMT_TCLR_START (1 << 0) /* Start timer */ 49286696Sian#define DMT_TCLR_AUTOLOAD (1 << 1) /* Auto-reload on overflow */ 50286696Sian#define DMT_TCLR_PRES_MASK (7 << 2) /* Prescaler mask */ 51286696Sian#define DMT_TCLR_PRES_ENABLE (1 << 5) /* Prescaler enable */ 52286696Sian#define DMT_TCLR_COMP_ENABLE (1 << 6) /* Compare enable */ 53286696Sian#define DMT_TCLR_PWM_HIGH (1 << 7) /* PWM default output high */ 54286696Sian#define DMT_TCLR_CAPTRAN_MASK (3 << 8) /* Capture transition mask */ 55286696Sian#define DMT_TCLR_CAPTRAN_NONE (0 << 8) /* Capture: none */ 56286696Sian#define DMT_TCLR_CAPTRAN_LOHI (1 << 8) /* Capture lo->hi transition */ 57286696Sian#define DMT_TCLR_CAPTRAN_HILO (2 << 8) /* Capture hi->lo transition */ 58286696Sian#define DMT_TCLR_CAPTRAN_BOTH (3 << 8) /* Capture both transitions */ 59286696Sian#define DMT_TCLR_TRGMODE_MASK (3 << 10) /* Trigger output mode mask */ 60286696Sian#define DMT_TCLR_TRGMODE_NONE (0 << 10) /* Trigger off */ 61286696Sian#define DMT_TCLR_TRGMODE_OVFL (1 << 10) /* Trigger on overflow */ 62286696Sian#define DMT_TCLR_TRGMODE_BOTH (2 << 10) /* Trigger on match + ovflow */ 63286696Sian#define DMT_TCLR_PWM_PTOGGLE (1 << 12) /* PWM toggles */ 64286696Sian#define DMT_TCLR_CAP_MODE_2ND (1 << 13) /* Capture second event mode */ 65314512Sian#define DMT_TCLR_GPO_CFG (1 << 14) /* Tmr pin conf, 0=out, 1=in */ 66286696Sian#define DMT_TCRR 0x3C /* Counter Register */ 67286696Sian#define DMT_TLDR 0x40 /* Load Reg */ 68286696Sian#define DMT_TTGR 0x44 /* Trigger Reg */ 69286696Sian#define DMT_TWPS 0x48 /* Write Posted Status Reg */ 70286696Sian#define DMT_TMAR 0x4C /* Match Reg */ 71286696Sian#define DMT_TCAR1 0x50 /* Capture Reg */ 72286696Sian#define DMT_TSICR 0x54 /* Synchr. Interface Ctrl Reg */ 73286696Sian#define DMT_TSICR_RESET (1 << 1) /* TSICR perform soft reset */ 74286696Sian#define DMT_TCAR2 0x48 /* Capture Reg */ 75286696Sian 76286696Sian#endif /* AM335X_DMTREG_H */ 77