exynos5_mct.c revision 257200 
1/*-
2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * This module just enables Exynos MCT, so ARMv7 Generic Timer will works
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/arm/samsung/exynos/arch_timer.c 257200 2013-10-27 01:34:10Z ian $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/malloc.h>
40#include <sys/rman.h>
41#include <sys/timeet.h>
42#include <sys/timetc.h>
43#include <sys/watchdog.h>
44#include <machine/bus.h>
45#include <machine/cpu.h>
46#include <machine/intr.h>
47
48#include <dev/fdt/fdt_common.h>
49#include <dev/ofw/openfirm.h>
50#include <dev/ofw/ofw_bus.h>
51#include <dev/ofw/ofw_bus_subr.h>
52
53#include <machine/bus.h>
54#include <machine/fdt.h>
55
56#define	MCT_CTRL_START		(1 << 8)
57#define	MCT_CTRL		(0x240)
58#define	MCT_WRITE_STAT		(0x24C)
59
60struct arm_tmr_softc {
61	struct resource		*tmr_res[1];
62	bus_space_tag_t		bst;
63	bus_space_handle_t	bsh;
64};
65
66static struct resource_spec arm_tmr_spec[] = {
67	{ SYS_RES_MEMORY,       0,      RF_ACTIVE },    /* Timer registers */
68	{ -1, 0 }
69};
70
71static int
72arm_tmr_probe(device_t dev)
73{
74	if (!ofw_bus_is_compatible(dev, "exynos,mct"))
75		return (ENXIO);
76
77	device_set_desc(dev, "Exynos MPCore Timer");
78	return (BUS_PROBE_DEFAULT);
79}
80
81static int
82arm_tmr_attach(device_t dev)
83{
84	struct arm_tmr_softc *sc;
85	int reg, i;
86	int mask;
87
88	sc = device_get_softc(dev);
89
90	if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) {
91		device_printf(dev, "could not allocate resources\n");
92		return (ENXIO);
93	}
94
95	/* Timer interface */
96	sc->bst = rman_get_bustag(sc->tmr_res[0]);
97	sc->bsh = rman_get_bushandle(sc->tmr_res[0]);
98
99	reg = bus_space_read_4(sc->bst, sc->bsh, MCT_CTRL);
100	reg |= MCT_CTRL_START;
101	bus_space_write_4(sc->bst, sc->bsh, MCT_CTRL, reg);
102
103	mask = (1 << 16);
104
105	/* Wait 10 times until written value is applied */
106	for (i = 0; i < 10; i++) {
107		reg = bus_space_read_4(sc->bst, sc->bsh, MCT_WRITE_STAT);
108		if (reg & mask) {
109			bus_space_write_4(sc->bst, sc->bsh,
110			    MCT_WRITE_STAT, mask);
111			return (0);
112		}
113		cpufunc_nullop();
114	}
115
116	/* NOTREACHED */
117
118	panic("Can't enable timer\n");
119}
120
121static device_method_t arm_tmr_methods[] = {
122	DEVMETHOD(device_probe,		arm_tmr_probe),
123	DEVMETHOD(device_attach,	arm_tmr_attach),
124	{ 0, 0 }
125};
126
127static driver_t arm_tmr_driver = {
128	"arch_timer",
129	arm_tmr_methods,
130	sizeof(struct arm_tmr_softc),
131};
132
133static devclass_t arm_tmr_devclass;
134
135DRIVER_MODULE(arch_timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0);
136