exynos5_mct.c revision 252391 
1/*-
2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * This module just enables Exynos MCT, so ARMv7 Generic Timer will works
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/arm/samsung/exynos/arch_timer.c 252391 2013-06-29 23:39:05Z ray $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/malloc.h>
40#include <sys/rman.h>
41#include <sys/timeet.h>
42#include <sys/timetc.h>
43#include <sys/watchdog.h>
44#include <machine/bus.h>
45#include <machine/cpu.h>
46#include <machine/frame.h>
47#include <machine/intr.h>
48
49#include <dev/fdt/fdt_common.h>
50#include <dev/ofw/openfirm.h>
51#include <dev/ofw/ofw_bus.h>
52#include <dev/ofw/ofw_bus_subr.h>
53
54#include <machine/bus.h>
55#include <machine/fdt.h>
56
57#define	MCT_CTRL_START		(1 << 8)
58#define	MCT_CTRL		(0x240)
59#define	MCT_WRITE_STAT		(0x24C)
60
61struct arm_tmr_softc {
62	struct resource		*tmr_res[1];
63	bus_space_tag_t		bst;
64	bus_space_handle_t	bsh;
65};
66
67static struct resource_spec arm_tmr_spec[] = {
68	{ SYS_RES_MEMORY,       0,      RF_ACTIVE },    /* Timer registers */
69	{ -1, 0 }
70};
71
72static int
73arm_tmr_probe(device_t dev)
74{
75	if (!ofw_bus_is_compatible(dev, "exynos,mct"))
76		return (ENXIO);
77
78	device_set_desc(dev, "Exynos MPCore Timer");
79	return (BUS_PROBE_DEFAULT);
80}
81
82static int
83arm_tmr_attach(device_t dev)
84{
85	struct arm_tmr_softc *sc;
86	int reg, i;
87	int mask;
88
89	sc = device_get_softc(dev);
90
91	if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) {
92		device_printf(dev, "could not allocate resources\n");
93		return (ENXIO);
94	}
95
96	/* Timer interface */
97	sc->bst = rman_get_bustag(sc->tmr_res[0]);
98	sc->bsh = rman_get_bushandle(sc->tmr_res[0]);
99
100	reg = bus_space_read_4(sc->bst, sc->bsh, MCT_CTRL);
101	reg |= MCT_CTRL_START;
102	bus_space_write_4(sc->bst, sc->bsh, MCT_CTRL, reg);
103
104	mask = (1 << 16);
105
106	/* Wait 10 times until written value is applied */
107	for (i = 0; i < 10; i++) {
108		reg = bus_space_read_4(sc->bst, sc->bsh, MCT_WRITE_STAT);
109		if (reg & mask) {
110			bus_space_write_4(sc->bst, sc->bsh,
111			    MCT_WRITE_STAT, mask);
112			return (0);
113		}
114		cpufunc_nullop();
115	}
116
117	/* NOTREACHED */
118
119	panic("Can't enable timer\n");
120}
121
122static device_method_t arm_tmr_methods[] = {
123	DEVMETHOD(device_probe,		arm_tmr_probe),
124	DEVMETHOD(device_attach,	arm_tmr_attach),
125	{ 0, 0 }
126};
127
128static driver_t arm_tmr_driver = {
129	"arch_timer",
130	arm_tmr_methods,
131	sizeof(struct arm_tmr_softc),
132};
133
134static devclass_t arm_tmr_devclass;
135
136DRIVER_MODULE(arch_timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0);
137