tegra_sdhci.c revision 332010 
1/*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra_sdhci.c 332010 2018-04-04 11:30:20Z mmel $");
29
30/*
31 * SDHCI driver glue for NVIDIA Tegra family
32 *
33 */
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/types.h>
37#include <sys/bus.h>
38#include <sys/gpio.h>
39#include <sys/kernel.h>
40#include <sys/lock.h>
41#include <sys/malloc.h>
42#include <sys/module.h>
43#include <sys/mutex.h>
44#include <sys/resource.h>
45#include <sys/rman.h>
46#include <sys/sysctl.h>
47#include <sys/taskqueue.h>
48
49#include <machine/bus.h>
50#include <machine/resource.h>
51#include <machine/intr.h>
52
53#include <dev/extres/clk/clk.h>
54#include <dev/extres/hwreset/hwreset.h>
55#include <dev/gpio/gpiobusvar.h>
56#include <dev/mmc/bridge.h>
57#include <dev/mmc/mmcbrvar.h>
58#include <dev/ofw/ofw_bus.h>
59#include <dev/ofw/ofw_bus_subr.h>
60#include <dev/sdhci/sdhci.h>
61#include <dev/sdhci/sdhci_fdt_gpio.h>
62
63#include "sdhci_if.h"
64
65/* Tegra SDHOST controller vendor register definitions */
66#define	SDMMC_VENDOR_CLOCK_CNTRL		0x100
67#define	 VENDOR_CLOCK_CNTRL_CLK_SHIFT			8
68#define	 VENDOR_CLOCK_CNTRL_CLK_MASK			0xFF
69#define	SDMMC_VENDOR_SYS_SW_CNTRL		0x104
70#define	SDMMC_VENDOR_CAP_OVERRIDES		0x10C
71#define	SDMMC_VENDOR_BOOT_CNTRL			0x110
72#define	SDMMC_VENDOR_BOOT_ACK_TIMEOUT		0x114
73#define	SDMMC_VENDOR_BOOT_DAT_TIMEOUT		0x118
74#define	SDMMC_VENDOR_DEBOUNCE_COUNT		0x11C
75#define	SDMMC_VENDOR_MISC_CNTRL			0x120
76#define	 VENDOR_MISC_CTRL_ENABLE_SDR104			0x8
77#define	 VENDOR_MISC_CTRL_ENABLE_SDR50			0x10
78#define	 VENDOR_MISC_CTRL_ENABLE_SDHCI_SPEC_300		0x20
79#define	 VENDOR_MISC_CTRL_ENABLE_DDR50			0x200
80#define	SDMMC_MAX_CURRENT_OVERRIDE		0x124
81#define	SDMMC_MAX_CURRENT_OVERRIDE_HI		0x128
82#define	SDMMC_VENDOR_CLK_GATE_HYSTERESIS_COUNT 	0x1D0
83#define	SDMMC_VENDOR_PHWRESET_VAL0		0x1D4
84#define	SDMMC_VENDOR_PHWRESET_VAL1		0x1D8
85#define	SDMMC_VENDOR_PHWRESET_VAL2		0x1DC
86#define	SDMMC_SDMEMCOMPPADCTRL_0		0x1E0
87#define	SDMMC_AUTO_CAL_CONFIG			0x1E4
88#define	SDMMC_AUTO_CAL_INTERVAL			0x1E8
89#define	SDMMC_AUTO_CAL_STATUS			0x1EC
90#define	SDMMC_SDMMC_MCCIF_FIFOCTRL		0x1F4
91#define	SDMMC_TIMEOUT_WCOAL_SDMMC		0x1F8
92
93/* Compatible devices. */
94static struct ofw_compat_data compat_data[] = {
95	{"nvidia,tegra124-sdhci",	1},
96	{NULL,				0},
97};
98
99struct tegra_sdhci_softc {
100	device_t		dev;
101	struct resource *	mem_res;
102	struct resource *	irq_res;
103	void *			intr_cookie;
104	u_int			quirks;	/* Chip specific quirks */
105	u_int			caps;	/* If we override SDHCI_CAPABILITIES */
106	uint32_t		max_clk; /* Max possible freq */
107	clk_t			clk;
108	hwreset_t 		reset;
109	gpio_pin_t		gpio_power;
110	struct sdhci_fdt_gpio	*gpio;
111
112	int			force_card_present;
113	struct sdhci_slot	slot;
114
115};
116
117static inline uint32_t
118RD4(struct tegra_sdhci_softc *sc, bus_size_t off)
119{
120
121	return (bus_read_4(sc->mem_res, off));
122}
123
124static uint8_t
125tegra_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
126{
127	struct tegra_sdhci_softc *sc;
128
129	sc = device_get_softc(dev);
130	return (bus_read_1(sc->mem_res, off));
131}
132
133static uint16_t
134tegra_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
135{
136	struct tegra_sdhci_softc *sc;
137
138	sc = device_get_softc(dev);
139	return (bus_read_2(sc->mem_res, off));
140}
141
142static uint32_t
143tegra_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
144{
145	struct tegra_sdhci_softc *sc;
146	uint32_t val32;
147
148	sc = device_get_softc(dev);
149	val32 = bus_read_4(sc->mem_res, off);
150	/* Force the card-present state if necessary. */
151	if (off == SDHCI_PRESENT_STATE && sc->force_card_present)
152		val32 |= SDHCI_CARD_PRESENT;
153	return (val32);
154}
155
156static void
157tegra_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
158    uint32_t *data, bus_size_t count)
159{
160	struct tegra_sdhci_softc *sc;
161
162	sc = device_get_softc(dev);
163	bus_read_multi_4(sc->mem_res, off, data, count);
164}
165
166static void
167tegra_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
168    uint8_t val)
169{
170	struct tegra_sdhci_softc *sc;
171
172	sc = device_get_softc(dev);
173	bus_write_1(sc->mem_res, off, val);
174}
175
176static void
177tegra_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
178    uint16_t val)
179{
180	struct tegra_sdhci_softc *sc;
181
182	sc = device_get_softc(dev);
183	bus_write_2(sc->mem_res, off, val);
184}
185
186static void
187tegra_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
188    uint32_t val)
189{
190	struct tegra_sdhci_softc *sc;
191
192	sc = device_get_softc(dev);
193	bus_write_4(sc->mem_res, off, val);
194}
195
196static void
197tegra_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
198    uint32_t *data, bus_size_t count)
199{
200	struct tegra_sdhci_softc *sc;
201
202	sc = device_get_softc(dev);
203	bus_write_multi_4(sc->mem_res, off, data, count);
204}
205
206static void
207tegra_sdhci_intr(void *arg)
208{
209	struct tegra_sdhci_softc *sc = arg;
210
211	sdhci_generic_intr(&sc->slot);
212	RD4(sc, SDHCI_INT_STATUS);
213}
214
215static int
216tegra_sdhci_get_ro(device_t brdev, device_t reqdev)
217{
218	struct tegra_sdhci_softc *sc = device_get_softc(brdev);
219
220	return (sdhci_fdt_gpio_get_readonly(sc->gpio));
221}
222
223static bool
224tegra_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot)
225{
226	struct tegra_sdhci_softc *sc = device_get_softc(dev);
227
228	return (sdhci_fdt_gpio_get_present(sc->gpio));
229}
230
231static int
232tegra_sdhci_probe(device_t dev)
233{
234	struct tegra_sdhci_softc *sc;
235	phandle_t node;
236	pcell_t cid;
237	const struct ofw_compat_data *cd;
238
239	sc = device_get_softc(dev);
240	if (!ofw_bus_status_okay(dev))
241		return (ENXIO);
242
243	if (ofw_bus_is_compatible(dev, "nvidia,tegra124-sdhci")) {
244		device_set_desc(dev, "Tegra SDHCI controller");
245	} else
246		return (ENXIO);
247	cd = ofw_bus_search_compatible(dev, compat_data);
248	if (cd->ocd_data == 0)
249		return (ENXIO);
250
251	node = ofw_bus_get_node(dev);
252
253	/* Allow dts to patch quirks, slots, and max-frequency. */
254	if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0)
255		sc->quirks = cid;
256	if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0)
257		sc->max_clk = cid;
258
259	return (BUS_PROBE_DEFAULT);
260}
261
262static int
263tegra_sdhci_attach(device_t dev)
264{
265	struct tegra_sdhci_softc *sc;
266	int rid, rv;
267	uint64_t freq;
268	phandle_t node, prop;
269
270	sc = device_get_softc(dev);
271	sc->dev = dev;
272	node = ofw_bus_get_node(dev);
273
274	rid = 0;
275	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
276	    RF_ACTIVE);
277	if (!sc->mem_res) {
278		device_printf(dev, "cannot allocate memory window\n");
279		rv = ENXIO;
280		goto fail;
281	}
282
283	rid = 0;
284	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
285	    RF_ACTIVE);
286	if (!sc->irq_res) {
287		device_printf(dev, "cannot allocate interrupt\n");
288		rv = ENXIO;
289		goto fail;
290	}
291
292	if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
293	    NULL, tegra_sdhci_intr, sc, &sc->intr_cookie)) {
294		device_printf(dev, "cannot setup interrupt handler\n");
295		rv = ENXIO;
296		goto fail;
297	}
298
299	rv = hwreset_get_by_ofw_name(sc->dev, 0, "sdhci", &sc->reset);
300	if (rv != 0) {
301		device_printf(sc->dev, "Cannot get 'sdhci' reset\n");
302		goto fail;
303	}
304	rv = hwreset_deassert(sc->reset);
305	if (rv != 0) {
306		device_printf(dev, "Cannot unreset 'sdhci' reset\n");
307		goto fail;
308	}
309
310	gpio_pin_get_by_ofw_property(sc->dev, node, "power-gpios", &sc->gpio_power);
311
312	rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
313	if (rv != 0) {
314
315		device_printf(dev, "Cannot get clock\n");
316		goto fail;
317	}
318
319	rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
320	if (rv != 0) {
321		device_printf(dev, "Cannot get clock\n");
322		goto fail;
323	}
324	rv = clk_enable(sc->clk);
325	if (rv != 0) {
326		device_printf(dev, "Cannot enable clock\n");
327		goto fail;
328	}
329	rv = clk_set_freq(sc->clk, 48000000, CLK_SET_ROUND_DOWN);
330	if (rv != 0) {
331		device_printf(dev, "Cannot set clock\n");
332	}
333	rv = clk_get_freq(sc->clk, &freq);
334	if (rv != 0) {
335		device_printf(dev, "Cannot get clock frequency\n");
336		goto fail;
337	}
338	if (bootverbose)
339		device_printf(dev, " Base MMC clock: %lld\n", freq);
340
341	/* Fill slot information. */
342	sc->max_clk = (int)freq;
343	sc->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
344	    SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
345	    SDHCI_QUIRK_MISSING_CAPS;
346
347	/* Limit real slot capabilities. */
348	sc->caps = RD4(sc, SDHCI_CAPABILITIES);
349	if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) {
350		sc->caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
351		switch (prop) {
352		case 8:
353			sc->caps |= MMC_CAP_8_BIT_DATA;
354			/* FALLTHROUGH */
355		case 4:
356			sc->caps |= MMC_CAP_4_BIT_DATA;
357			break;
358		case 1:
359			break;
360		default:
361			device_printf(dev, "Bad bus-width value %u\n", prop);
362			break;
363		}
364	}
365	if (OF_hasprop(node, "non-removable"))
366		sc->force_card_present = 1;
367	/*
368	 * Clear clock field, so SDHCI driver uses supplied frequency.
369	 * in sc->slot.max_clk
370	 */
371	sc->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
372
373	sc->slot.quirks = sc->quirks;
374	sc->slot.max_clk = sc->max_clk;
375	sc->slot.caps = sc->caps;
376
377	rv = sdhci_init_slot(dev, &sc->slot, 0);
378	if (rv != 0) {
379		goto fail;
380	}
381
382	sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot);
383
384	bus_generic_probe(dev);
385	bus_generic_attach(dev);
386
387	sdhci_start_slot(&sc->slot);
388
389	return (0);
390
391fail:
392	if (sc->gpio != NULL)
393		sdhci_fdt_gpio_teardown(sc->gpio);
394	if (sc->intr_cookie != NULL)
395		bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
396	if (sc->gpio_power != NULL)
397		gpio_pin_release(sc->gpio_power);
398	if (sc->clk != NULL)
399		clk_release(sc->clk);
400	if (sc->reset != NULL)
401		hwreset_release(sc->reset);
402	if (sc->irq_res != NULL)
403		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
404	if (sc->mem_res != NULL)
405		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
406
407	return (rv);
408}
409
410static int
411tegra_sdhci_detach(device_t dev)
412{
413	struct tegra_sdhci_softc *sc = device_get_softc(dev);
414	struct sdhci_slot *slot = &sc->slot;
415
416	bus_generic_detach(dev);
417	sdhci_fdt_gpio_teardown(sc->gpio);
418	clk_release(sc->clk);
419	bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
420	bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res),
421			     sc->irq_res);
422
423	sdhci_cleanup_slot(slot);
424	bus_release_resource(dev, SYS_RES_MEMORY,
425			     rman_get_rid(sc->mem_res),
426			     sc->mem_res);
427	return (0);
428}
429
430static device_method_t tegra_sdhci_methods[] = {
431	/* Device interface */
432	DEVMETHOD(device_probe,		tegra_sdhci_probe),
433	DEVMETHOD(device_attach,	tegra_sdhci_attach),
434	DEVMETHOD(device_detach,	tegra_sdhci_detach),
435
436	/* Bus interface */
437	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
438	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
439
440	/* MMC bridge interface */
441	DEVMETHOD(mmcbr_update_ios,	sdhci_generic_update_ios),
442	DEVMETHOD(mmcbr_request,	sdhci_generic_request),
443	DEVMETHOD(mmcbr_get_ro,		tegra_sdhci_get_ro),
444	DEVMETHOD(mmcbr_acquire_host,	sdhci_generic_acquire_host),
445	DEVMETHOD(mmcbr_release_host,	sdhci_generic_release_host),
446
447	/* SDHCI registers accessors */
448	DEVMETHOD(sdhci_read_1,		tegra_sdhci_read_1),
449	DEVMETHOD(sdhci_read_2,		tegra_sdhci_read_2),
450	DEVMETHOD(sdhci_read_4,		tegra_sdhci_read_4),
451	DEVMETHOD(sdhci_read_multi_4,	tegra_sdhci_read_multi_4),
452	DEVMETHOD(sdhci_write_1,	tegra_sdhci_write_1),
453	DEVMETHOD(sdhci_write_2,	tegra_sdhci_write_2),
454	DEVMETHOD(sdhci_write_4,	tegra_sdhci_write_4),
455	DEVMETHOD(sdhci_write_multi_4,	tegra_sdhci_write_multi_4),
456	DEVMETHOD(sdhci_get_card_present, tegra_sdhci_get_card_present),
457
458	DEVMETHOD_END
459};
460
461static devclass_t tegra_sdhci_devclass;
462static DEFINE_CLASS_0(sdhci, tegra_sdhci_driver, tegra_sdhci_methods,
463    sizeof(struct tegra_sdhci_softc));
464DRIVER_MODULE(sdhci_tegra, simplebus, tegra_sdhci_driver, tegra_sdhci_devclass,
465    NULL, NULL);
466MODULE_DEPEND(sdhci_tegra, sdhci, 1, 1, 1);
467MMC_DECLARE_BRIDGE(sdhci);
468