tegra124_car.c revision 317012
1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra124/tegra124_car.c 317012 2017-04-16 08:18:37Z mmel $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/kobj.h> 35#include <sys/module.h> 36#include <sys/malloc.h> 37#include <sys/rman.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40 41#include <machine/bus.h> 42#include <machine/cpu.h> 43 44#include <dev/extres/clk/clk_div.h> 45#include <dev/extres/clk/clk_fixed.h> 46#include <dev/extres/clk/clk_gate.h> 47#include <dev/extres/clk/clk_mux.h> 48#include <dev/extres/hwreset/hwreset.h> 49#include <dev/ofw/openfirm.h> 50#include <dev/ofw/ofw_bus.h> 51#include <dev/ofw/ofw_bus_subr.h> 52 53#include <gnu/dts/include/dt-bindings/clock/tegra124-car.h> 54 55#include "clkdev_if.h" 56#include "hwreset_if.h" 57#include "tegra124_car.h" 58 59static struct ofw_compat_data compat_data[] = { 60 {"nvidia,tegra124-car", 1}, 61 {NULL, 0}, 62}; 63 64#define PLIST(x) static const char *x[] 65 66/* Pure multiplexer. */ 67#define MUX(_id, cname, plists, o, s, w) \ 68{ \ 69 .clkdef.id = _id, \ 70 .clkdef.name = cname, \ 71 .clkdef.parent_names = plists, \ 72 .clkdef.parent_cnt = nitems(plists), \ 73 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 74 .offset = o, \ 75 .shift = s, \ 76 .width = w, \ 77} 78 79/* Fractional divider (7.1). */ 80#define DIV7_1(_id, cname, plist, o, s) \ 81{ \ 82 .clkdef.id = _id, \ 83 .clkdef.name = cname, \ 84 .clkdef.parent_names = (const char *[]){plist}, \ 85 .clkdef.parent_cnt = 1, \ 86 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 87 .offset = o, \ 88 .i_shift = (s) + 1, \ 89 .i_width = 7, \ 90 .f_shift = s, \ 91 .f_width = 1, \ 92} 93 94/* Integer divider. */ 95#define DIV(_id, cname, plist, o, s, w, f) \ 96{ \ 97 .clkdef.id = _id, \ 98 .clkdef.name = cname, \ 99 .clkdef.parent_names = (const char *[]){plist}, \ 100 .clkdef.parent_cnt = 1, \ 101 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 102 .offset = o, \ 103 .i_shift = s, \ 104 .i_width = w, \ 105 .div_flags = f, \ 106} 107 108/* Gate in PLL block. */ 109#define GATE_PLL(_id, cname, plist, o, s) \ 110{ \ 111 .clkdef.id = _id, \ 112 .clkdef.name = cname, \ 113 .clkdef.parent_names = (const char *[]){plist}, \ 114 .clkdef.parent_cnt = 1, \ 115 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 116 .offset = o, \ 117 .shift = s, \ 118 .mask = 3, \ 119 .on_value = 3, \ 120 .off_value = 0, \ 121} 122 123/* Standard gate. */ 124#define GATE(_id, cname, plist, o, s) \ 125{ \ 126 .clkdef.id = _id, \ 127 .clkdef.name = cname, \ 128 .clkdef.parent_names = (const char *[]){plist}, \ 129 .clkdef.parent_cnt = 1, \ 130 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 131 .offset = o, \ 132 .shift = s, \ 133 .mask = 1, \ 134 .on_value = 1, \ 135 .off_value = 0, \ 136} 137 138/* Inverted gate. */ 139#define GATE_INV(_id, cname, plist, o, s) \ 140{ \ 141 .clkdef.id = _id, \ 142 .clkdef.name = cname, \ 143 .clkdef.parent_names = (const char *[]){plist}, \ 144 .clkdef.parent_cnt = 1, \ 145 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 146 .offset = o, \ 147 .shift = s, \ 148 .mask = 1, \ 149 .on_value = 0, \ 150 .off_value = 1, \ 151} 152 153/* Fixed rate clock. */ 154#define FRATE(_id, cname, _freq) \ 155{ \ 156 .clkdef.id = _id, \ 157 .clkdef.name = cname, \ 158 .clkdef.parent_names = NULL, \ 159 .clkdef.parent_cnt = 0, \ 160 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 161 .freq = _freq, \ 162} 163 164/* Fixed rate multipier/divider. */ 165#define FACT(_id, cname, pname, _mult, _div) \ 166{ \ 167 .clkdef.id = _id, \ 168 .clkdef.name = cname, \ 169 .clkdef.parent_names = (const char *[]){pname}, \ 170 .clkdef.parent_cnt = 1, \ 171 .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 172 .mult = _mult, \ 173 .div = _div, \ 174} 175 176static uint32_t osc_freqs[16] = { 177 [0] = 13000000, 178 [1] = 16800000, 179 [4] = 19200000, 180 [5] = 38400000, 181 [8] = 12000000, 182 [9] = 48000000, 183 [12] = 260000000, 184}; 185 186 187/* Parent lists. */ 188PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */ 189PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"}; 190PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"}; 191PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"}; 192PLIST(mux_pllmcp_clkm) = {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m", 193 "pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"}; 194PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"}; 195PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"}; 196 197 198/* Clocks ajusted online. */ 199static struct clk_fixed_def fixed_clk_m = 200 FRATE(TEGRA124_CLK_CLK_M, "clk_m", 12000000); 201static struct clk_fixed_def fixed_osc_div_clk = 202 FACT(0, "osc_div_clk", "clk_m", 1, 1); 203 204static struct clk_fixed_def tegra124_fixed_clks[] = { 205 /* Core clocks. */ 206 FRATE(0, "clk_s", 32768), 207 FACT(0, "clk_m_div2", "clk_m", 1, 2), 208 FACT(0, "clk_m_div4", "clk_m", 1, 3), 209 FACT(0, "pllU_60", "pllU_out", 1, 8), 210 FACT(0, "pllU_48", "pllU_out", 1, 10), 211 FACT(0, "pllU_12", "pllU_out", 1, 40), 212 FACT(TEGRA124_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2), 213 FACT(TEGRA124_CLK_PLL_D2_OUT0, "pllD2_out0", "pllD2_out", 1, 1), 214 FACT(0, "pllX_out0", "pllX_out", 1, 2), 215 FACT(0, "pllC_UD", "pllC_out0", 1, 1), 216 FACT(0, "pllM_UD", "pllM_out0", 1, 1), 217 218 /* Audio clocks. */ 219 FRATE(0, "audio0", 10000000), 220 FRATE(0, "audio1", 10000000), 221 FRATE(0, "audio2", 10000000), 222 FRATE(0, "audio3", 10000000), 223 FRATE(0, "audio4", 10000000), 224 FRATE(0, "ext_vimclk", 10000000), 225 226 /* XUSB */ 227 FACT(TEGRA124_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2), 228 229}; 230 231 232static struct clk_mux_def tegra124_mux_clks[] = { 233 /* Core clocks. */ 234 MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2), 235 MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2), 236 MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2), 237 MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1), 238 MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1), 239 240 /* Base peripheral clocks. */ 241 MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1), 242 MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1), 243 MUX(0, "emc_mux", mux_pllmcp_clkm, CLK_SOURCE_EMC, 29, 3), 244 245 /* USB. */ 246 MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1), 247 MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1), 248 249}; 250 251 252static struct clk_gate_def tegra124_gate_clks[] = { 253 /* Core clocks. */ 254 GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0), 255 GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0), 256 GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22), 257 GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0), 258 GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0), 259 GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16), 260 GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0), 261 GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16), 262 GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16), 263 GATE_PLL(0, "pllA_out0", "pllA_out1_div", PLLA_OUT, 0), 264 265 /* Base peripheral clocks. */ 266 GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0), 267 GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1), 268 GATE_INV(TEGRA124_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7), 269 GATE_INV(TEGRA124_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3), 270}; 271 272static struct clk_div_def tegra124_div_clks[] = { 273 /* Core clocks. */ 274 DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 2), 275 DIV7_1(0, "pllM_out1_div", "pllM_out0", PLLM_OUT, 8), 276 DIV7_1(0, "pllP_outX0_div", "pllP_out0", PLLP_RESHIFT, 2), 277 DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8), 278 DIV7_1(0, "pllP_out2_div", "pllP_out0", PLLP_OUTA, 24), 279 DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8), 280 DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24), 281 DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24), 282 DIV7_1(0, "pllA_out1_div", "pllA_out", PLLA_OUT, 8), 283 284 /* Base peripheral clocks. */ 285 DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0), 286 DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0), 287}; 288 289/* Initial setup table. */ 290static struct tegra124_init_item clk_init_table[] = { 291 /* clock, partent, frequency, enable */ 292 {"uarta", "pllP_out0", 408000000, 0}, 293 {"uartb", "pllP_out0", 408000000, 0}, 294 {"uartc", "pllP_out0", 408000000, 0}, 295 {"uartd", "pllP_out0", 408000000, 0}, 296 {"pllA_out", NULL, 282240000, 1}, 297 {"pllA_out0", NULL, 11289600, 1}, 298 {"extperiph1", "pllA_out0", 0, 1}, 299 {"i2s0", "pllA_out0", 11289600, 0}, 300 {"i2s1", "pllA_out0", 11289600, 0}, 301 {"i2s2", "pllA_out0", 11289600, 0}, 302 {"i2s3", "pllA_out0", 11289600, 0}, 303 {"i2s4", "pllA_out0", 11289600, 0}, 304 {"vde", "pllP_out0", 0, 0}, 305 {"host1x", "pllP_out0", 136000000, 1}, 306 {"sclk", "pllP_out2", 102000000, 1}, 307 {"dvfs_soc", "pllP_out0", 51000000, 1}, 308 {"dvfs_ref", "pllP_out0", 51000000, 1}, 309 {"pllC_out0", NULL, 600000000, 0}, 310 {"pllC_out1", NULL, 100000000, 0}, 311 {"spi4", "pllP_out0", 12000000, 1}, 312 {"tsec", "pllC3_out0", 0, 0}, 313 {"msenc", "pllC3_out0", 0, 0}, 314 {"pllREFE_out", NULL, 672000000, 0}, 315 {"pc_xusb_ss", "pllU_480", 120000000, 0}, 316 {"xusb_ss", "pc_xusb_ss", 120000000, 0}, 317 {"pc_xusb_fs", "pllU_48", 48000000, 0}, 318 {"xusb_hs", "pllU_60", 60000000, 0}, 319 {"pc_xusb_falcon", "pllREFE_out", 224000000, 0}, 320 {"xusb_core_host", "pllREFE_out", 112000000, 0}, 321 {"sata", "pllP_out0", 102000000, 0}, 322 {"sata_oob", "pllP_out0", 204000000, 0}, 323 {"sata_cold", NULL, 0, 1}, 324 {"emc", NULL, 0, 1}, 325 {"mselect", NULL, 0, 1}, 326 {"csite", NULL, 0, 1}, 327 {"tsensor", "clk_m", 400000, 0}, 328 329 /* tegra124 only*/ 330 {"soc_therm", "pllP_out0", 51000000, 0}, 331 {"cclk_g", NULL, 0, 1}, 332 {"hda", "pllP_out0", 102000000, 0}, 333 {"hda2codec_2x", "pllP_out0", 48000000, 0}, 334}; 335 336static void 337init_divs(struct tegra124_car_softc *sc, struct clk_div_def *clks, int nclks) 338{ 339 int i, rv; 340 341 for (i = 0; i < nclks; i++) { 342 rv = clknode_div_register(sc->clkdom, clks + i); 343 if (rv != 0) 344 panic("clk_div_register failed"); 345 } 346} 347 348static void 349init_gates(struct tegra124_car_softc *sc, struct clk_gate_def *clks, int nclks) 350{ 351 int i, rv; 352 353 354 for (i = 0; i < nclks; i++) { 355 rv = clknode_gate_register(sc->clkdom, clks + i); 356 if (rv != 0) 357 panic("clk_gate_register failed"); 358 } 359} 360 361static void 362init_muxes(struct tegra124_car_softc *sc, struct clk_mux_def *clks, int nclks) 363{ 364 int i, rv; 365 366 367 for (i = 0; i < nclks; i++) { 368 rv = clknode_mux_register(sc->clkdom, clks + i); 369 if (rv != 0) 370 panic("clk_mux_register failed"); 371 } 372} 373 374static void 375init_fixeds(struct tegra124_car_softc *sc, struct clk_fixed_def *clks, 376 int nclks) 377{ 378 int i, rv; 379 uint32_t val; 380 int osc_idx; 381 382 CLKDEV_READ_4(sc->dev, OSC_CTRL, &val); 383 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT; 384 fixed_clk_m.freq = osc_freqs[osc_idx]; 385 if (fixed_clk_m.freq == 0) 386 panic("Undefined input frequency"); 387 rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m); 388 if (rv != 0) panic("clk_fixed_register failed"); 389 390 val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3; 391 fixed_osc_div_clk.div = 1 << val; 392 rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div_clk); 393 if (rv != 0) panic("clk_fixed_register failed"); 394 395 for (i = 0; i < nclks; i++) { 396 rv = clknode_fixed_register(sc->clkdom, clks + i); 397 if (rv != 0) 398 panic("clk_fixed_register failed"); 399 } 400} 401 402static void 403postinit_clock(struct tegra124_car_softc *sc) 404{ 405 int i; 406 struct tegra124_init_item *tbl; 407 struct clknode *clknode; 408 int rv; 409 410 for (i = 0; i < nitems(clk_init_table); i++) { 411 tbl = &clk_init_table[i]; 412 413 clknode = clknode_find_by_name(tbl->name); 414 if (clknode == NULL) { 415 device_printf(sc->dev, "Cannot find clock %s\n", 416 tbl->name); 417 continue; 418 } 419 if (tbl->parent != NULL) { 420 rv = clknode_set_parent_by_name(clknode, tbl->parent); 421 if (rv != 0) { 422 device_printf(sc->dev, 423 "Cannot set parent for %s (to %s): %d\n", 424 tbl->name, tbl->parent, rv); 425 continue; 426 } 427 } 428 if (tbl->frequency != 0) { 429 rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999); 430 if (rv != 0) { 431 device_printf(sc->dev, 432 "Cannot set frequency for %s: %d\n", 433 tbl->name, rv); 434 continue; 435 } 436 } 437 if (tbl->enable!= 0) { 438 rv = clknode_enable(clknode); 439 if (rv != 0) { 440 device_printf(sc->dev, 441 "Cannot enable %s: %d\n", tbl->name, rv); 442 continue; 443 } 444 } 445 } 446} 447 448static void 449register_clocks(device_t dev) 450{ 451 struct tegra124_car_softc *sc; 452 453 sc = device_get_softc(dev); 454 sc->clkdom = clkdom_create(dev); 455 if (sc->clkdom == NULL) 456 panic("clkdom == NULL"); 457 458 tegra124_init_plls(sc); 459 init_fixeds(sc, tegra124_fixed_clks, nitems(tegra124_fixed_clks)); 460 init_muxes(sc, tegra124_mux_clks, nitems(tegra124_mux_clks)); 461 init_divs(sc, tegra124_div_clks, nitems(tegra124_div_clks)); 462 init_gates(sc, tegra124_gate_clks, nitems(tegra124_gate_clks)); 463 tegra124_periph_clock(sc); 464 tegra124_super_mux_clock(sc); 465 clkdom_finit(sc->clkdom); 466 clkdom_xlock(sc->clkdom); 467 postinit_clock(sc); 468 clkdom_unlock(sc->clkdom); 469 if (bootverbose) 470 clkdom_dump(sc->clkdom); 471} 472 473static int 474tegra124_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val) 475{ 476 struct tegra124_car_softc *sc; 477 478 sc = device_get_softc(dev); 479 *val = bus_read_4(sc->mem_res, addr); 480 return (0); 481} 482 483static int 484tegra124_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val) 485{ 486 struct tegra124_car_softc *sc; 487 488 sc = device_get_softc(dev); 489 bus_write_4(sc->mem_res, addr, val); 490 return (0); 491} 492 493static int 494tegra124_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask, 495 uint32_t set_mask) 496{ 497 struct tegra124_car_softc *sc; 498 uint32_t reg; 499 500 sc = device_get_softc(dev); 501 reg = bus_read_4(sc->mem_res, addr); 502 reg &= ~clear_mask; 503 reg |= set_mask; 504 bus_write_4(sc->mem_res, addr, reg); 505 return (0); 506} 507 508static void 509tegra124_car_clkdev_device_lock(device_t dev) 510{ 511 struct tegra124_car_softc *sc; 512 513 sc = device_get_softc(dev); 514 mtx_lock(&sc->mtx); 515} 516 517static void 518tegra124_car_clkdev_device_unlock(device_t dev) 519{ 520 struct tegra124_car_softc *sc; 521 522 sc = device_get_softc(dev); 523 mtx_unlock(&sc->mtx); 524} 525 526static int 527tegra124_car_detach(device_t dev) 528{ 529 530 device_printf(dev, "Error: Clock driver cannot be detached\n"); 531 return (EBUSY); 532} 533 534static int 535tegra124_car_probe(device_t dev) 536{ 537 538 if (!ofw_bus_status_okay(dev)) 539 return (ENXIO); 540 541 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 542 device_set_desc(dev, "Tegra Clock Driver"); 543 return (BUS_PROBE_DEFAULT); 544 } 545 546 return (ENXIO); 547} 548 549static int 550tegra124_car_attach(device_t dev) 551{ 552 struct tegra124_car_softc *sc = device_get_softc(dev); 553 int rid, rv; 554 555 sc->dev = dev; 556 557 mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); 558 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 559 560 /* Resource setup. */ 561 rid = 0; 562 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 563 RF_ACTIVE); 564 if (!sc->mem_res) { 565 device_printf(dev, "cannot allocate memory resource\n"); 566 rv = ENXIO; 567 goto fail; 568 } 569 570 register_clocks(dev); 571 hwreset_register_ofw_provider(dev); 572 return (0); 573 574fail: 575 if (sc->mem_res) 576 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 577 578 return (rv); 579} 580 581static int 582tegra124_car_hwreset_assert(device_t dev, intptr_t id, bool value) 583{ 584 struct tegra124_car_softc *sc = device_get_softc(dev); 585 586 return (tegra124_hwreset_by_idx(sc, id, value)); 587} 588 589static device_method_t tegra124_car_methods[] = { 590 /* Device interface */ 591 DEVMETHOD(device_probe, tegra124_car_probe), 592 DEVMETHOD(device_attach, tegra124_car_attach), 593 DEVMETHOD(device_detach, tegra124_car_detach), 594 595 /* Clkdev interface*/ 596 DEVMETHOD(clkdev_read_4, tegra124_car_clkdev_read_4), 597 DEVMETHOD(clkdev_write_4, tegra124_car_clkdev_write_4), 598 DEVMETHOD(clkdev_modify_4, tegra124_car_clkdev_modify_4), 599 DEVMETHOD(clkdev_device_lock, tegra124_car_clkdev_device_lock), 600 DEVMETHOD(clkdev_device_unlock, tegra124_car_clkdev_device_unlock), 601 602 /* Reset interface */ 603 DEVMETHOD(hwreset_assert, tegra124_car_hwreset_assert), 604 605 DEVMETHOD_END 606}; 607 608static devclass_t tegra124_car_devclass; 609static DEFINE_CLASS_0(car, tegra124_car_driver, tegra124_car_methods, 610 sizeof(struct tegra124_car_softc)); 611EARLY_DRIVER_MODULE(tegra124_car, simplebus, tegra124_car_driver, 612 tegra124_car_devclass, NULL, NULL, BUS_PASS_TIMER); 613