mvwin.h revision 240489
1/*- 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD: head/sys/arm/mv/mvwin.h 240489 2012-09-14 09:57:41Z gber $ 32 */ 33 34#ifndef _MVWIN_H_ 35#define _MVWIN_H_ 36 37/* 38 * Decode windows addresses. 39 * 40 * All decoding windows must be aligned to their size, which has to be 41 * a power of 2. 42 */ 43 44/* 45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA) 46 */ 47 48/* SoC Regs */ 49#define MV_PHYS_BASE 0xF1000000 50#define MV_SIZE (1024 * 1024) /* 1 MB */ 51 52/* SRAM */ 53#define MV_CESA_SRAM_BASE 0xF1100000 54 55/* AXI Regs */ 56#ifdef SOC_MV_DOVE 57#define MV_AXI_PHYS_BASE 0xF1800000 58#define MV_AXI_BASE MV_AXI_PHYS_BASE 59#define MV_AXI_SIZE (16 * 1024 * 1024) /* 16 MB */ 60#endif 61 62/* 63 * External devices: 0x80000000, 1 GB (VA == PA) 64 * Includes Device Bus, PCI and PCIE. 65 */ 66#if defined(SOC_MV_ORION) 67#define MV_PCI_PORTS 2 /* 1x PCI + 1x PCIE */ 68#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_FREY) 69#define MV_PCI_PORTS 1 /* 1x PCIE */ 70#elif defined(SOC_MV_DISCOVERY) 71#define MV_PCI_PORTS 8 /* 8x PCIE */ 72#elif defined(SOC_MV_DOVE) || defined(SOC_MV_LOKIPLUS) 73#define MV_PCI_PORTS 2 /* 2x PCIE */ 74#elif defined(SOC_MV_ARMADAXP) 75#define MV_PCI_PORTS 3 /* 3x PCIE */ 76#else 77#error "MV_PCI_PORTS not configured !" 78#endif 79 80/* PCI/PCIE Memory */ 81#define MV_PCI_MEM_PHYS_BASE 0x80000000 82#define MV_PCI_MEM_SIZE (512 * 1024 * 1024) /* 512 MB */ 83#define MV_PCI_MEM_BASE MV_PCI_MEM_PHYS_BASE 84#define MV_PCI_MEM_SLICE_SIZE (MV_PCI_MEM_SIZE / MV_PCI_PORTS) 85#define MV_PCI_MEM_SLICE(n) (MV_PCI_MEM_BASE + ((n) * \ 86 MV_PCI_MEM_SLICE_SIZE)) 87/* PCI/PCIE I/O */ 88#define MV_PCI_IO_PHYS_BASE 0xBF000000 89#define MV_PCI_IO_SIZE (16 * 1024 * 1024) /* 16 MB */ 90#define MV_PCI_IO_BASE MV_PCI_IO_PHYS_BASE 91#define MV_PCI_IO_SLICE_SIZE (MV_PCI_IO_SIZE / MV_PCI_PORTS) 92#define MV_PCI_IO_SLICE(n) (MV_PCI_IO_BASE + ((n) * MV_PCI_IO_SLICE_SIZE)) 93 94#if defined(SOC_MV_FREY) 95#define MV_PCI_VA_MEM_BASE MV_PCI_MEM_BASE 96#else 97#define MV_PCI_VA_MEM_BASE 0 98#endif 99#define MV_PCI_VA_IO_BASE 0 100 101/* 102 * Device Bus (VA == PA) 103 */ 104#define MV_DEV_BOOT_BASE 0xF9300000 105#define MV_DEV_BOOT_SIZE (1024 * 1024) /* 1 MB */ 106 107#define MV_DEV_CS0_BASE 0xF9400000 108#define MV_DEV_CS0_SIZE (1024 * 1024) /* 1 MB */ 109 110#define MV_DEV_CS1_BASE 0xF9500000 111#define MV_DEV_CS1_SIZE (32 * 1024 * 1024) /* 32 MB */ 112 113#define MV_DEV_CS2_BASE 0xFB500000 114#define MV_DEV_CS2_SIZE (1024 * 1024) /* 1 MB */ 115 116 117/* 118 * Integrated SoC peripherals addresses 119 */ 120#define MV_BASE MV_PHYS_BASE /* VA == PA mapping */ 121#if defined(SOC_MV_DOVE) 122#define MV_DDR_CADR_BASE (MV_AXI_BASE + 0x100) 123#elif defined(SOC_MV_LOKIPLUS) 124#define MV_DDR_CADR_BASE (MV_BASE + 0xF1500) 125#else 126#define MV_DDR_CADR_BASE (MV_BASE + 0x1500) 127#endif 128#define MV_MPP_BASE (MV_BASE + 0x10000) 129 130#if defined(SOC_MV_ARMADAXP) 131#define MV_MISC_BASE (MV_BASE + 0x18200) 132#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 133#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 134#define MV_MP_CLOCKS_BASE (MV_MBUS_BRIDGE_BASE + 0x700) 135#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x1800) 136#elif !defined(SOC_MV_FREY) 137#define MV_MBUS_BRIDGE_BASE (MV_BASE + 0x20000) 138#define MV_INTREGS_BASE (MV_MBUS_BRIDGE_BASE + 0x80) 139#define MV_CPU_CONTROL_BASE (MV_MBUS_BRIDGE_BASE + 0x100) 140#else 141#define MV_CPU_CONTROL_BASE (MV_BASE + 0x10000) 142#endif 143 144#define MV_PCI_BASE (MV_BASE + 0x30000) 145#define MV_PCI_SIZE 0x2000 146 147#if defined(SOC_MV_FREY) 148#define MV_PCIE_BASE (MV_BASE + 0x8000) 149#else 150#define MV_PCIE_BASE (MV_BASE + 0x40000) 151#endif 152#define MV_PCIE_SIZE 0x2000 153 154#define MV_PCIE00_BASE (MV_PCIE_BASE + 0x00000) 155#define MV_PCIE01_BASE (MV_PCIE_BASE + 0x04000) 156#define MV_PCIE02_BASE (MV_PCIE_BASE + 0x08000) 157#define MV_PCIE03_BASE (MV_PCIE_BASE + 0x0C000) 158#define MV_PCIE10_BASE (MV_PCIE_BASE + 0x40000) 159#define MV_PCIE11_BASE (MV_PCIE_BASE + 0x44000) 160#define MV_PCIE12_BASE (MV_PCIE_BASE + 0x48000) 161#define MV_PCIE13_BASE (MV_PCIE_BASE + 0x4C000) 162 163#define MV_SDIO_BASE (MV_BASE + 0x90000) 164#define MV_SDIO_SIZE 0x10000 165 166/* 167 * Decode windows definitions and macros 168 */ 169#if defined(SOC_MV_ARMADAXP) 170#define MV_WIN_CPU_CTRL(n) (((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) 171#define MV_WIN_CPU_BASE(n) ((((n) < 8) ? 0x10 * (n) : 0x90 + (0x8 * ((n) - 8))) + 0x4) 172#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + 0x008) 173#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + 0x00C) 174#else 175#define MV_WIN_CPU_CTRL(n) (0x10 * (n) + (((n) < 8) ? 0x000 : 0x880)) 176#define MV_WIN_CPU_BASE(n) (0x10 * (n) + (((n) < 8) ? 0x004 : 0x884)) 177#define MV_WIN_CPU_REMAP_LO(n) (0x10 * (n) + (((n) < 8) ? 0x008 : 0x888)) 178#define MV_WIN_CPU_REMAP_HI(n) (0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C)) 179#endif 180 181#if defined(SOC_MV_DISCOVERY) 182#define MV_WIN_CPU_MAX 14 183#elif defined(SOC_MV_ARMADAXP) 184#define MV_WIN_CPU_MAX 20 185#else 186#define MV_WIN_CPU_MAX 8 187#endif 188 189#define MV_WIN_CPU_ATTR_SHIFT 8 190#if defined(SOC_MV_LOKIPLUS) 191#define MV_WIN_CPU_TARGET_SHIFT 0 192#define MV_WIN_CPU_ENABLE_BIT (1 << 5) 193#else 194#define MV_WIN_CPU_TARGET_SHIFT 4 195#define MV_WIN_CPU_ENABLE_BIT 1 196#endif 197 198#if defined(SOC_MV_DOVE) 199#define MV_WIN_DDR_MAX 2 200#else /* SOC_MV_DOVE */ 201#if defined(SOC_MV_LOKIPLUS) 202#define MV_WIN_DDR_BASE(n) (0xc * (n) + 0x4) 203#define MV_WIN_DDR_SIZE(n) (0xc * (n) + 0x0) 204#else /* SOC_MV_LOKIPLUS */ 205#define MV_WIN_DDR_BASE(n) (0x8 * (n) + 0x0) 206#define MV_WIN_DDR_SIZE(n) (0x8 * (n) + 0x4) 207#endif /* SOC_MV_LOKIPLUS */ 208#define MV_WIN_DDR_MAX 4 209#endif /* SOC_MV_DOVE */ 210 211#define MV_WIN_CESA_CTRL(n) (0x8 * (n) + 0xa04) 212#define MV_WIN_CESA_BASE(n) (0x8 * (n) + 0xa00) 213#define MV_WIN_CESA_MAX 4 214 215#if defined(SOC_MV_DISCOVERY) 216#define MV_WIN_CESA_TARGET 9 217#define MV_WIN_CESA_ATTR 1 218#else 219#define MV_WIN_CESA_TARGET 3 220#define MV_WIN_CESA_ATTR 0 221#endif 222 223#define MV_WIN_USB_CTRL(n) (0x10 * (n) + 0x320) 224#define MV_WIN_USB_BASE(n) (0x10 * (n) + 0x324) 225#define MV_WIN_USB_MAX 4 226 227#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200) 228#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204) 229#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280) 230#define MV_WIN_ETH_MAX 6 231 232#define MV_WIN_IDMA_BASE(n) (0x8 * (n) + 0xa00) 233#define MV_WIN_IDMA_SIZE(n) (0x8 * (n) + 0xa04) 234#define MV_WIN_IDMA_REMAP(n) (0x4 * (n) + 0xa60) 235#define MV_WIN_IDMA_CAP(n) (0x4 * (n) + 0xa70) 236#define MV_WIN_IDMA_MAX 8 237#define MV_IDMA_CHAN_MAX 4 238 239#define MV_WIN_XOR_BASE(n, m) (0x4 * (n) + 0xa50 + (m) * 0x100) 240#define MV_WIN_XOR_SIZE(n, m) (0x4 * (n) + 0xa70 + (m) * 0x100) 241#define MV_WIN_XOR_REMAP(n, m) (0x4 * (n) + 0xa90 + (m) * 0x100) 242#define MV_WIN_XOR_CTRL(n, m) (0x4 * (n) + 0xa40 + (m) * 0x100) 243#define MV_WIN_XOR_OVERR(n, m) (0x4 * (n) + 0xaa0 + (m) * 0x100) 244#define MV_WIN_XOR_MAX 8 245#define MV_XOR_CHAN_MAX 2 246#define MV_XOR_NON_REMAP 4 247 248#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DOVE) 249#define MV_WIN_PCIE_TARGET(n) 4 250#define MV_WIN_PCIE_MEM_ATTR(n) 0xE8 251#define MV_WIN_PCIE_IO_ATTR(n) 0xE0 252#elif defined(SOC_MV_ARMADAXP) 253#define MV_WIN_PCIE_TARGET(n) (4 + (4 * ((n) % 2))) 254#define MV_WIN_PCIE_MEM_ATTR(n) (0xE8 + (0x10 * ((n) / 2))) 255#define MV_WIN_PCIE_IO_ATTR(n) (0xE0 + (0x10 * ((n) / 2))) 256#elif defined(SOC_MV_ORION) 257#define MV_WIN_PCIE_TARGET(n) 4 258#define MV_WIN_PCIE_MEM_ATTR(n) 0x59 259#define MV_WIN_PCIE_IO_ATTR(n) 0x51 260#elif defined(SOC_MV_LOKIPLUS) 261#define MV_WIN_PCIE_TARGET(n) (3 + (n)) 262#define MV_WIN_PCIE_MEM_ATTR(n) 0x59 263#define MV_WIN_PCIE_IO_ATTR(n) 0x51 264#endif 265 266#define MV_WIN_PCI_TARGET 3 267#define MV_WIN_PCI_MEM_ATTR 0x59 268#define MV_WIN_PCI_IO_ATTR 0x51 269 270#define MV_WIN_PCIE_CTRL(n) (0x10 * (((n) < 5) ? (n) : \ 271 (n) + 1) + 0x1820) 272#define MV_WIN_PCIE_BASE(n) (0x10 * (((n) < 5) ? (n) : \ 273 (n) + 1) + 0x1824) 274#define MV_WIN_PCIE_REMAP(n) (0x10 * (((n) < 5) ? (n) : \ 275 (n) + 1) + 0x182C) 276#define MV_WIN_PCIE_MAX 6 277 278#define MV_PCIE_BAR_CTRL(n) (0x04 * (n) + 0x1800) 279#define MV_PCIE_BAR_BASE(n) (0x08 * ((n) < 3 ? (n) : 4) + 0x0010) 280#define MV_PCIE_BAR_BASE_H(n) (0x08 * (n) + 0x0014) 281#define MV_PCIE_BAR_MAX 4 282#define MV_PCIE_BAR_64BIT (0x4) 283#define MV_PCIE_BAR_PREFETCH_EN (0x8) 284 285#define MV_PCIE_CONTROL (0x1a00) 286#define MV_PCIE_ROOT_CMPLX (1 << 1) 287 288#define MV_WIN_SATA_CTRL(n) (0x10 * (n) + 0x30) 289#define MV_WIN_SATA_BASE(n) (0x10 * (n) + 0x34) 290#define MV_WIN_SATA_MAX 4 291 292#define WIN_REG_IDX_RD(pre,reg,off,base) \ 293 static __inline uint32_t \ 294 pre ## _ ## reg ## _read(int i) \ 295 { \ 296 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 297 } 298 299#define WIN_REG_IDX_RD2(pre,reg,off,base) \ 300 static __inline uint32_t \ 301 pre ## _ ## reg ## _read(int i, int j) \ 302 { \ 303 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 304 } \ 305 306#define WIN_REG_BASE_IDX_RD(pre,reg,off) \ 307 static __inline uint32_t \ 308 pre ## _ ## reg ## _read(uint32_t base, int i) \ 309 { \ 310 return (bus_space_read_4(fdtbus_bs_tag, base, off(i))); \ 311 } 312 313#define WIN_REG_BASE_IDX_RD2(pre,reg,off) \ 314 static __inline uint32_t \ 315 pre ## _ ## reg ## _read(uint32_t base, int i, int j) \ 316 { \ 317 return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j))); \ 318 } 319 320#define WIN_REG_IDX_WR(pre,reg,off,base) \ 321 static __inline void \ 322 pre ## _ ## reg ## _write(int i, uint32_t val) \ 323 { \ 324 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 325 } 326 327#define WIN_REG_IDX_WR2(pre,reg,off,base) \ 328 static __inline void \ 329 pre ## _ ## reg ## _write(int i, int j, uint32_t val) \ 330 { \ 331 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 332 } 333 334#define WIN_REG_BASE_IDX_WR(pre,reg,off) \ 335 static __inline void \ 336 pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val) \ 337 { \ 338 bus_space_write_4(fdtbus_bs_tag, base, off(i), val); \ 339 } 340 341#define WIN_REG_BASE_IDX_WR2(pre,reg,off) \ 342 static __inline void \ 343 pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val) \ 344 { \ 345 bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val); \ 346 } 347 348#define WIN_REG_RD(pre,reg,off,base) \ 349 static __inline uint32_t \ 350 pre ## _ ## reg ## _read(void) \ 351 { \ 352 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 353 } 354 355#define WIN_REG_BASE_RD(pre,reg,off) \ 356 static __inline uint32_t \ 357 pre ## _ ## reg ## _read(uint32_t base) \ 358 { \ 359 return (bus_space_read_4(fdtbus_bs_tag, base, off)); \ 360 } 361 362#define WIN_REG_WR(pre,reg,off,base) \ 363 static __inline void \ 364 pre ## _ ## reg ## _write(uint32_t val) \ 365 { \ 366 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 367 } 368 369#define WIN_REG_BASE_WR(pre,reg,off) \ 370 static __inline void \ 371 pre ## _ ## reg ## _write(uint32_t base, uint32_t val) \ 372 { \ 373 bus_space_write_4(fdtbus_bs_tag, base, off, val); \ 374 } 375 376#endif /* _MVWIN_H_ */ 377