mv_pci.c revision 294883
1185089Sraj/*- 2209131Sraj * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 3209131Sraj * Copyright (c) 2010 The FreeBSD Foundation 4294430Szbb * Copyright (c) 2010-2015 Semihalf 5185089Sraj * All rights reserved. 6185089Sraj * 7185089Sraj * Developed by Semihalf. 8185089Sraj * 9209131Sraj * Portions of this software were developed by Semihalf 10209131Sraj * under sponsorship from the FreeBSD Foundation. 11209131Sraj * 12185089Sraj * Redistribution and use in source and binary forms, with or without 13185089Sraj * modification, are permitted provided that the following conditions 14185089Sraj * are met: 15185089Sraj * 1. Redistributions of source code must retain the above copyright 16185089Sraj * notice, this list of conditions and the following disclaimer. 17185089Sraj * 2. Redistributions in binary form must reproduce the above copyright 18185089Sraj * notice, this list of conditions and the following disclaimer in the 19185089Sraj * documentation and/or other materials provided with the distribution. 20185089Sraj * 3. Neither the name of MARVELL nor the names of contributors 21185089Sraj * may be used to endorse or promote products derived from this software 22185089Sraj * without specific prior written permission. 23185089Sraj * 24185089Sraj * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25185089Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26185089Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27185089Sraj * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 28185089Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29185089Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30185089Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31185089Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32185089Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33185089Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34185089Sraj * SUCH DAMAGE. 35185089Sraj */ 36185089Sraj 37185089Sraj/* 38185089Sraj * Marvell integrated PCI/PCI-Express controller driver. 39185089Sraj */ 40185089Sraj 41185089Sraj#include <sys/cdefs.h> 42185089Sraj__FBSDID("$FreeBSD: head/sys/arm/mv/mv_pci.c 294883 2016-01-27 02:23:54Z jhibbits $"); 43185089Sraj 44185089Sraj#include <sys/param.h> 45185089Sraj#include <sys/systm.h> 46185089Sraj#include <sys/kernel.h> 47185089Sraj#include <sys/lock.h> 48185089Sraj#include <sys/malloc.h> 49185089Sraj#include <sys/module.h> 50185089Sraj#include <sys/mutex.h> 51185089Sraj#include <sys/queue.h> 52185089Sraj#include <sys/bus.h> 53185089Sraj#include <sys/rman.h> 54185089Sraj#include <sys/endian.h> 55185089Sraj 56260327Snwhitehorn#include <machine/fdt.h> 57240493Sgber#include <machine/intr.h> 58240493Sgber 59185089Sraj#include <vm/vm.h> 60185089Sraj#include <vm/pmap.h> 61185089Sraj 62209131Sraj#include <dev/fdt/fdt_common.h> 63209131Sraj#include <dev/ofw/ofw_bus.h> 64259484Snwhitehorn#include <dev/ofw/ofw_pci.h> 65209131Sraj#include <dev/ofw/ofw_bus_subr.h> 66185089Sraj#include <dev/pci/pcivar.h> 67185089Sraj#include <dev/pci/pcireg.h> 68185089Sraj#include <dev/pci/pcib_private.h> 69185089Sraj 70209131Sraj#include "ofw_bus_if.h" 71185089Sraj#include "pcib_if.h" 72185089Sraj 73260340Sian#include <machine/devmap.h> 74185089Sraj#include <machine/resource.h> 75185089Sraj#include <machine/bus.h> 76185089Sraj 77185089Sraj#include <arm/mv/mvreg.h> 78185089Sraj#include <arm/mv/mvvar.h> 79209131Sraj#include <arm/mv/mvwin.h> 80185089Sraj 81240493Sgber#ifdef DEBUG 82240493Sgber#define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 83240493Sgber#else 84240493Sgber#define debugf(fmt, args...) 85240493Sgber#endif 86240493Sgber 87260340Sian/* 88260340Sian * Code and data related to fdt-based PCI configuration. 89260340Sian * 90260340Sian * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 91260340Sian * always Marvell-specific so that was deleted and the code now lives here. 92260340Sian */ 93260340Sian 94260340Sianstruct mv_pci_range { 95260340Sian u_long base_pci; 96260340Sian u_long base_parent; 97260340Sian u_long len; 98260340Sian}; 99260340Sian 100260340Sian#define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 101260340Sian 102260340Sianstatic void 103260340Sianmv_pci_range_dump(struct mv_pci_range *range) 104260340Sian{ 105260340Sian#ifdef DEBUG 106260340Sian printf("\n"); 107260340Sian printf(" base_pci = 0x%08lx\n", range->base_pci); 108260340Sian printf(" base_par = 0x%08lx\n", range->base_parent); 109260340Sian printf(" len = 0x%08lx\n", range->len); 110260340Sian#endif 111260340Sian} 112260340Sian 113260340Sianstatic int 114260340Sianmv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 115260340Sian struct mv_pci_range *mem_space) 116260340Sian{ 117260340Sian pcell_t ranges[FDT_RANGES_CELLS]; 118260340Sian struct mv_pci_range *pci_space; 119260340Sian pcell_t addr_cells, size_cells, par_addr_cells; 120260340Sian pcell_t *rangesptr; 121260340Sian pcell_t cell0, cell1, cell2; 122260340Sian int tuple_size, tuples, i, rv, offset_cells, len; 123260340Sian 124260340Sian /* 125260340Sian * Retrieve 'ranges' property. 126260340Sian */ 127260340Sian if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 128260340Sian return (EINVAL); 129260340Sian if (addr_cells != 3 || size_cells != 2) 130260340Sian return (ERANGE); 131260340Sian 132260340Sian par_addr_cells = fdt_parent_addr_cells(node); 133260340Sian if (par_addr_cells > 3) 134260340Sian return (ERANGE); 135260340Sian 136260340Sian len = OF_getproplen(node, "ranges"); 137260340Sian if (len > sizeof(ranges)) 138260340Sian return (ENOMEM); 139260340Sian 140260340Sian if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 141260340Sian return (EINVAL); 142260340Sian 143260340Sian tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 144260340Sian size_cells); 145260340Sian tuples = len / tuple_size; 146260340Sian 147260340Sian /* 148260340Sian * Initialize the ranges so that we don't have to worry about 149260340Sian * having them all defined in the FDT. In particular, it is 150260340Sian * perfectly fine not to want I/O space on PCI busses. 151260340Sian */ 152260340Sian bzero(io_space, sizeof(*io_space)); 153260340Sian bzero(mem_space, sizeof(*mem_space)); 154260340Sian 155260340Sian rangesptr = &ranges[0]; 156260340Sian offset_cells = 0; 157260340Sian for (i = 0; i < tuples; i++) { 158260340Sian cell0 = fdt_data_get((void *)rangesptr, 1); 159260340Sian rangesptr++; 160260340Sian cell1 = fdt_data_get((void *)rangesptr, 1); 161260340Sian rangesptr++; 162260340Sian cell2 = fdt_data_get((void *)rangesptr, 1); 163260340Sian rangesptr++; 164260340Sian 165260340Sian if (cell0 & 0x02000000) { 166260340Sian pci_space = mem_space; 167260340Sian } else if (cell0 & 0x01000000) { 168260340Sian pci_space = io_space; 169260340Sian } else { 170260340Sian rv = ERANGE; 171260340Sian goto out; 172260340Sian } 173260340Sian 174260340Sian if (par_addr_cells == 3) { 175260340Sian /* 176260340Sian * This is a PCI subnode 'ranges'. Skip cell0 and 177260340Sian * cell1 of this entry and only use cell2. 178260340Sian */ 179260340Sian offset_cells = 2; 180260340Sian rangesptr += offset_cells; 181260340Sian } 182260340Sian 183275799Sbr if ((par_addr_cells - offset_cells) > 2) { 184260340Sian rv = ERANGE; 185260340Sian goto out; 186260340Sian } 187260340Sian pci_space->base_parent = fdt_data_get((void *)rangesptr, 188260340Sian par_addr_cells - offset_cells); 189260340Sian rangesptr += par_addr_cells - offset_cells; 190260340Sian 191275802Sbr if (size_cells > 2) { 192260340Sian rv = ERANGE; 193260340Sian goto out; 194260340Sian } 195260340Sian pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 196260340Sian rangesptr += size_cells; 197260340Sian 198260340Sian pci_space->base_pci = cell2; 199260340Sian } 200260340Sian rv = 0; 201260340Sianout: 202260340Sian return (rv); 203260340Sian} 204260340Sian 205260340Sianstatic int 206260340Sianmv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 207260340Sian struct mv_pci_range *mem_space) 208260340Sian{ 209260340Sian int err; 210260340Sian 211260340Sian debugf("Processing PCI node: %x\n", node); 212260340Sian if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 213260340Sian debugf("could not decode parent PCI node 'ranges'\n"); 214260340Sian return (err); 215260340Sian } 216260340Sian 217260340Sian debugf("Post fixup dump:\n"); 218260340Sian mv_pci_range_dump(io_space); 219260340Sian mv_pci_range_dump(mem_space); 220260340Sian return (0); 221260340Sian} 222260340Sian 223260340Sianint 224260340Sianmv_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap, vm_offset_t io_va, 225260340Sian vm_offset_t mem_va) 226260340Sian{ 227260340Sian struct mv_pci_range io_space, mem_space; 228260340Sian int error; 229260340Sian 230260340Sian if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 231260340Sian return (error); 232260340Sian 233260340Sian devmap->pd_va = (io_va ? io_va : io_space.base_parent); 234260340Sian devmap->pd_pa = io_space.base_parent; 235260340Sian devmap->pd_size = io_space.len; 236260340Sian devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 237265852Sian devmap->pd_cache = PTE_DEVICE; 238260340Sian devmap++; 239260340Sian 240260340Sian devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 241260340Sian devmap->pd_pa = mem_space.base_parent; 242260340Sian devmap->pd_size = mem_space.len; 243260340Sian devmap->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 244265852Sian devmap->pd_cache = PTE_DEVICE; 245260340Sian return (0); 246260340Sian} 247260340Sian 248260340Sian/* 249260340Sian * Code and data related to the Marvell pcib driver. 250260340Sian */ 251260340Sian 252258780Seadler#define PCI_CFG_ENA (1U << 31) 253185089Sraj#define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 254185089Sraj#define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 255185089Sraj#define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 256185089Sraj#define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 257185089Sraj 258185089Sraj#define PCI_REG_CFG_ADDR 0x0C78 259185089Sraj#define PCI_REG_CFG_DATA 0x0C7C 260185089Sraj 261185089Sraj#define PCIE_REG_CFG_ADDR 0x18F8 262185089Sraj#define PCIE_REG_CFG_DATA 0x18FC 263185089Sraj#define PCIE_REG_CONTROL 0x1A00 264185089Sraj#define PCIE_CTRL_LINK1X 0x00000001 265185089Sraj#define PCIE_REG_STATUS 0x1A04 266185089Sraj#define PCIE_REG_IRQ_MASK 0x1910 267185089Sraj 268240489Sgber#define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 269240489Sgber#define PCIE_CONTROL_HOT_RESET (1 << 24) 270185089Sraj 271240489Sgber#define PCIE_LINK_TIMEOUT 1000000 272185089Sraj 273240489Sgber#define PCIE_STATUS_LINK_DOWN 1 274240489Sgber#define PCIE_STATUS_DEV_OFFS 16 275185089Sraj 276240489Sgber/* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 277240489Sgber#define PCI_MIN_IO_ALLOC 4 278240489Sgber#define PCI_MIN_MEM_ALLOC 16 279240489Sgber 280240489Sgber#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 281240489Sgber 282209131Srajstruct mv_pcib_softc { 283185089Sraj device_t sc_dev; 284185089Sraj 285209131Sraj struct rman sc_mem_rman; 286209131Sraj bus_addr_t sc_mem_base; 287209131Sraj bus_addr_t sc_mem_size; 288240489Sgber uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 289240489Sgber (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 290240489Sgber int sc_win_target; 291209131Sraj int sc_mem_win_attr; 292185089Sraj 293209131Sraj struct rman sc_io_rman; 294209131Sraj bus_addr_t sc_io_base; 295209131Sraj bus_addr_t sc_io_size; 296240489Sgber uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 297240489Sgber (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 298209131Sraj int sc_io_win_attr; 299185089Sraj 300185089Sraj struct resource *sc_res; 301185089Sraj bus_space_handle_t sc_bsh; 302185089Sraj bus_space_tag_t sc_bst; 303185089Sraj int sc_rid; 304185089Sraj 305240493Sgber struct mtx sc_msi_mtx; 306240493Sgber uint32_t sc_msi_bitmap; 307240493Sgber 308185089Sraj int sc_busnr; /* Host bridge bus number */ 309185089Sraj int sc_devnr; /* Host bridge device number */ 310209131Sraj int sc_type; 311240489Sgber int sc_mode; /* Endpoint / Root Complex */ 312185089Sraj 313259484Snwhitehorn struct ofw_bus_iinfo sc_pci_iinfo; 314185089Sraj}; 315185089Sraj 316209131Sraj/* Local forward prototypes */ 317209131Srajstatic int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 318209131Srajstatic void mv_pcib_hw_cfginit(void); 319209131Srajstatic uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 320209131Sraj u_int, u_int, int); 321209131Srajstatic void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 322209131Sraj u_int, u_int, uint32_t, int); 323209131Srajstatic int mv_pcib_init(struct mv_pcib_softc *, int, int); 324209131Srajstatic int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 325209131Srajstatic void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 326209131Srajstatic inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 327240489Sgberstatic void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 328240489Sgberstatic int mv_pcib_mem_init(struct mv_pcib_softc *); 329185089Sraj 330209131Sraj/* Forward prototypes */ 331209131Srajstatic int mv_pcib_probe(device_t); 332209131Srajstatic int mv_pcib_attach(device_t); 333209131Sraj 334209131Srajstatic struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 335294883Sjhibbits rman_res_t, rman_res_t, rman_res_t, u_int); 336209131Srajstatic int mv_pcib_release_resource(device_t, device_t, int, int, 337185089Sraj struct resource *); 338209131Srajstatic int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 339209131Srajstatic int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 340185089Sraj 341209131Srajstatic int mv_pcib_maxslots(device_t); 342209131Srajstatic uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 343209131Srajstatic void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 344185089Sraj uint32_t, int); 345209131Srajstatic int mv_pcib_route_interrupt(device_t, device_t, int); 346240493Sgber#if defined(SOC_MV_ARMADAXP) 347240493Sgberstatic int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 348240493Sgberstatic int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 349240493Sgberstatic int mv_pcib_release_msi(device_t, device_t, int, int *); 350240493Sgber#endif 351185089Sraj 352185089Sraj/* 353185089Sraj * Bus interface definitions. 354185089Sraj */ 355209131Srajstatic device_method_t mv_pcib_methods[] = { 356185089Sraj /* Device interface */ 357209131Sraj DEVMETHOD(device_probe, mv_pcib_probe), 358209131Sraj DEVMETHOD(device_attach, mv_pcib_attach), 359185089Sraj 360185089Sraj /* Bus interface */ 361209131Sraj DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 362209131Sraj DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 363209131Sraj DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 364209131Sraj DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 365185089Sraj DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 366185089Sraj DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 367185089Sraj DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 368185089Sraj DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 369185089Sraj 370185089Sraj /* pcib interface */ 371209131Sraj DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 372209131Sraj DEVMETHOD(pcib_read_config, mv_pcib_read_config), 373209131Sraj DEVMETHOD(pcib_write_config, mv_pcib_write_config), 374209131Sraj DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 375240493Sgber 376240493Sgber#if defined(SOC_MV_ARMADAXP) 377240493Sgber DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 378240493Sgber DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 379240493Sgber DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 380240493Sgber#endif 381240493Sgber 382209131Sraj /* OFW bus interface */ 383209131Sraj DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 384209131Sraj DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 385209131Sraj DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 386209131Sraj DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 387209131Sraj DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 388209131Sraj 389227843Smarius DEVMETHOD_END 390185089Sraj}; 391185089Sraj 392209131Srajstatic driver_t mv_pcib_driver = { 393185089Sraj "pcib", 394209131Sraj mv_pcib_methods, 395209131Sraj sizeof(struct mv_pcib_softc), 396185089Sraj}; 397185089Sraj 398185089Srajdevclass_t pcib_devclass; 399185089Sraj 400261513SnwhitehornDRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0); 401185089Sraj 402185089Srajstatic struct mtx pcicfg_mtx; 403185089Sraj 404185089Srajstatic int 405209131Srajmv_pcib_probe(device_t self) 406185089Sraj{ 407218228Smarcel phandle_t node; 408185089Sraj 409218228Smarcel node = ofw_bus_get_node(self); 410218228Smarcel if (!fdt_is_type(node, "pci")) 411209131Sraj return (ENXIO); 412218228Smarcel 413259484Snwhitehorn if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 414259484Snwhitehorn ofw_bus_is_compatible(self, "mrvl,pci"))) 415209131Sraj return (ENXIO); 416185089Sraj 417209131Sraj device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 418209131Sraj return (BUS_PROBE_DEFAULT); 419185089Sraj} 420185089Sraj 421185089Srajstatic int 422209131Srajmv_pcib_attach(device_t self) 423185089Sraj{ 424209131Sraj struct mv_pcib_softc *sc; 425209131Sraj phandle_t node, parnode; 426240489Sgber uint32_t val, unit; 427209131Sraj int err; 428185089Sraj 429185089Sraj sc = device_get_softc(self); 430209131Sraj sc->sc_dev = self; 431240489Sgber unit = fdt_get_unit(self); 432185089Sraj 433240489Sgber 434218228Smarcel node = ofw_bus_get_node(self); 435218228Smarcel parnode = OF_parent(node); 436218228Smarcel if (fdt_is_compatible(node, "mrvl,pcie")) { 437209131Sraj sc->sc_type = MV_TYPE_PCIE; 438240489Sgber sc->sc_win_target = MV_WIN_PCIE_TARGET(unit); 439240489Sgber sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit); 440240489Sgber sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit); 441218228Smarcel } else if (fdt_is_compatible(node, "mrvl,pci")) { 442209131Sraj sc->sc_type = MV_TYPE_PCI; 443240489Sgber sc->sc_win_target = MV_WIN_PCI_TARGET; 444209131Sraj sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 445209131Sraj sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 446209131Sraj } else 447185089Sraj return (ENXIO); 448185089Sraj 449209131Sraj /* 450209131Sraj * Retrieve our mem-mapped registers range. 451209131Sraj */ 452185089Sraj sc->sc_rid = 0; 453185089Sraj sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 454185089Sraj RF_ACTIVE); 455185089Sraj if (sc->sc_res == NULL) { 456209131Sraj device_printf(self, "could not map memory\n"); 457185089Sraj return (ENXIO); 458185089Sraj } 459185089Sraj sc->sc_bst = rman_get_bustag(sc->sc_res); 460185089Sraj sc->sc_bsh = rman_get_bushandle(sc->sc_res); 461185089Sraj 462240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 463240489Sgber sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 464240489Sgber MV_MODE_ENDPOINT); 465240489Sgber 466209131Sraj /* 467240489Sgber * Get PCI interrupt info. 468240489Sgber */ 469259484Snwhitehorn if (sc->sc_mode == MV_MODE_ROOT) 470259484Snwhitehorn ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 471240489Sgber 472240489Sgber /* 473209131Sraj * Configure decode windows for PCI(E) access. 474209131Sraj */ 475209131Sraj if (mv_pcib_decode_win(node, sc) != 0) 476209131Sraj return (ENXIO); 477209131Sraj 478209131Sraj mv_pcib_hw_cfginit(); 479209131Sraj 480209131Sraj /* 481240489Sgber * Enable PCIE device. 482209131Sraj */ 483240489Sgber mv_pcib_enable(sc, unit); 484185089Sraj 485240489Sgber /* 486240489Sgber * Memory management. 487240489Sgber */ 488240489Sgber err = mv_pcib_mem_init(sc); 489240489Sgber if (err) 490240489Sgber return (err); 491185089Sraj 492240489Sgber if (sc->sc_mode == MV_MODE_ROOT) { 493240489Sgber err = mv_pcib_init(sc, sc->sc_busnr, 494240489Sgber mv_pcib_maxslots(sc->sc_dev)); 495240489Sgber if (err) 496240489Sgber goto error; 497240489Sgber 498240489Sgber device_add_child(self, "pci", -1); 499240489Sgber } else { 500240489Sgber sc->sc_devnr = 1; 501240489Sgber bus_space_write_4(sc->sc_bst, sc->sc_bsh, 502240489Sgber PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 503240489Sgber device_add_child(self, "pci_ep", -1); 504240489Sgber } 505240489Sgber 506240493Sgber mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 507240489Sgber return (bus_generic_attach(self)); 508240489Sgber 509240489Sgbererror: 510240489Sgber /* XXX SYS_RES_ should be released here */ 511240489Sgber rman_fini(&sc->sc_mem_rman); 512240489Sgber rman_fini(&sc->sc_io_rman); 513240489Sgber 514240489Sgber return (err); 515240489Sgber} 516240489Sgber 517240489Sgberstatic void 518240489Sgbermv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 519240489Sgber{ 520240489Sgber uint32_t val; 521240489Sgber#if !defined(SOC_MV_ARMADAXP) 522240489Sgber int timeout; 523240489Sgber 524240489Sgber /* 525240489Sgber * Check if PCIE device is enabled. 526240489Sgber */ 527240489Sgber if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) { 528240489Sgber write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 529240489Sgber ~(CPU_CONTROL_PCIE_DISABLE(unit))); 530240489Sgber 531240489Sgber timeout = PCIE_LINK_TIMEOUT; 532240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 533240489Sgber PCIE_REG_STATUS); 534240489Sgber while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 535240489Sgber DELAY(1000); 536240489Sgber timeout -= 1000; 537240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 538240489Sgber PCIE_REG_STATUS); 539240489Sgber } 540240489Sgber } 541240489Sgber#endif 542240489Sgber 543240489Sgber 544240489Sgber if (sc->sc_mode == MV_MODE_ROOT) { 545240489Sgber /* 546240489Sgber * Enable PCI bridge. 547240489Sgber */ 548240489Sgber val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 549240489Sgber val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 550240489Sgber PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 551240489Sgber bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 552240489Sgber } 553240489Sgber} 554240489Sgber 555240489Sgberstatic int 556240489Sgbermv_pcib_mem_init(struct mv_pcib_softc *sc) 557240489Sgber{ 558240489Sgber int err; 559240489Sgber 560240489Sgber /* 561240489Sgber * Memory management. 562240489Sgber */ 563209131Sraj sc->sc_mem_rman.rm_type = RMAN_ARRAY; 564209131Sraj err = rman_init(&sc->sc_mem_rman); 565186932Sraj if (err) 566186932Sraj return (err); 567186932Sraj 568209131Sraj sc->sc_io_rman.rm_type = RMAN_ARRAY; 569209131Sraj err = rman_init(&sc->sc_io_rman); 570186932Sraj if (err) { 571209131Sraj rman_fini(&sc->sc_mem_rman); 572186932Sraj return (err); 573186932Sraj } 574186932Sraj 575209131Sraj err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 576209131Sraj sc->sc_mem_base + sc->sc_mem_size - 1); 577186932Sraj if (err) 578186932Sraj goto error; 579186932Sraj 580209131Sraj err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 581209131Sraj sc->sc_io_base + sc->sc_io_size - 1); 582186932Sraj if (err) 583186932Sraj goto error; 584186932Sraj 585240489Sgber return (0); 586185089Sraj 587186932Srajerror: 588209131Sraj rman_fini(&sc->sc_mem_rman); 589209131Sraj rman_fini(&sc->sc_io_rman); 590240489Sgber 591186932Sraj return (err); 592185089Sraj} 593185089Sraj 594240489Sgberstatic inline uint32_t 595240489Sgberpcib_bit_get(uint32_t *map, uint32_t bit) 596240489Sgber{ 597240489Sgber uint32_t n = bit / BITS_PER_UINT32; 598240489Sgber 599240489Sgber bit = bit % BITS_PER_UINT32; 600240489Sgber return (map[n] & (1 << bit)); 601240489Sgber} 602240489Sgber 603240489Sgberstatic inline void 604240489Sgberpcib_bit_set(uint32_t *map, uint32_t bit) 605240489Sgber{ 606240489Sgber uint32_t n = bit / BITS_PER_UINT32; 607240489Sgber 608240489Sgber bit = bit % BITS_PER_UINT32; 609240489Sgber map[n] |= (1 << bit); 610240489Sgber} 611240489Sgber 612240489Sgberstatic inline uint32_t 613240489Sgberpcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 614240489Sgber{ 615240489Sgber uint32_t i; 616240489Sgber 617240489Sgber for (i = start; i < start + bits; i++) 618240489Sgber if (pcib_bit_get(map, i)) 619240489Sgber return (0); 620240489Sgber 621240489Sgber return (1); 622240489Sgber} 623240489Sgber 624240489Sgberstatic inline void 625240489Sgberpcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 626240489Sgber{ 627240489Sgber uint32_t i; 628240489Sgber 629240489Sgber for (i = start; i < start + bits; i++) 630240489Sgber pcib_bit_set(map, i); 631240489Sgber} 632240489Sgber 633240489Sgber/* 634240489Sgber * The idea of this allocator is taken from ARM No-Cache memory 635240489Sgber * management code (sys/arm/arm/vm_machdep.c). 636240489Sgber */ 637240489Sgberstatic bus_addr_t 638240489Sgberpcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 639240489Sgber{ 640240489Sgber uint32_t bits, bits_limit, i, *map, min_alloc, size; 641240489Sgber bus_addr_t addr = 0; 642240489Sgber bus_addr_t base; 643240489Sgber 644240489Sgber if (smask & 1) { 645240489Sgber base = sc->sc_io_base; 646240489Sgber min_alloc = PCI_MIN_IO_ALLOC; 647240489Sgber bits_limit = sc->sc_io_size / min_alloc; 648240489Sgber map = sc->sc_io_map; 649240489Sgber smask &= ~0x3; 650240489Sgber } else { 651240489Sgber base = sc->sc_mem_base; 652240489Sgber min_alloc = PCI_MIN_MEM_ALLOC; 653240489Sgber bits_limit = sc->sc_mem_size / min_alloc; 654240489Sgber map = sc->sc_mem_map; 655240489Sgber smask &= ~0xF; 656240489Sgber } 657240489Sgber 658240489Sgber size = ~smask + 1; 659240489Sgber bits = size / min_alloc; 660240489Sgber 661240489Sgber for (i = 0; i + bits <= bits_limit; i += bits) 662240489Sgber if (pcib_map_check(map, i, bits)) { 663240489Sgber pcib_map_set(map, i, bits); 664240489Sgber addr = base + (i * min_alloc); 665240489Sgber return (addr); 666240489Sgber } 667240489Sgber 668240489Sgber return (addr); 669240489Sgber} 670240489Sgber 671185089Srajstatic int 672209131Srajmv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 673185089Sraj int barno) 674185089Sraj{ 675240489Sgber uint32_t addr, bar; 676185089Sraj int reg, width; 677185089Sraj 678185089Sraj reg = PCIR_BAR(barno); 679240489Sgber 680240489Sgber /* 681240489Sgber * Need to init the BAR register with 0xffffffff before correct 682240489Sgber * value can be read. 683240489Sgber */ 684240489Sgber mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 685209131Sraj bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 686185089Sraj if (bar == 0) 687185089Sraj return (1); 688185089Sraj 689185089Sraj /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 690185089Sraj width = ((bar & 7) == 4) ? 2 : 1; 691185089Sraj 692240489Sgber addr = pcib_alloc(sc, bar); 693240489Sgber if (!addr) 694185089Sraj return (-1); 695185089Sraj 696185089Sraj if (bootverbose) 697240489Sgber printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 698240489Sgber bus, slot, func, reg, bar, addr); 699185089Sraj 700209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 701185089Sraj if (width == 2) 702209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 703185089Sraj 0, 4); 704185089Sraj 705185089Sraj return (width); 706185089Sraj} 707185089Sraj 708185089Srajstatic void 709209131Srajmv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 710185089Sraj{ 711185089Sraj bus_addr_t io_base, mem_base; 712185089Sraj uint32_t io_limit, mem_limit; 713185089Sraj int secbus; 714185089Sraj 715209131Sraj io_base = sc->sc_io_base; 716209131Sraj io_limit = io_base + sc->sc_io_size - 1; 717209131Sraj mem_base = sc->sc_mem_base; 718209131Sraj mem_limit = mem_base + sc->sc_mem_size - 1; 719185089Sraj 720185089Sraj /* Configure I/O decode registers */ 721209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 722185639Sraj io_base >> 8, 1); 723209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 724185639Sraj io_base >> 16, 2); 725209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 726185089Sraj io_limit >> 8, 1); 727209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 728185089Sraj io_limit >> 16, 2); 729185089Sraj 730185089Sraj /* Configure memory decode registers */ 731209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 732185089Sraj mem_base >> 16, 2); 733209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 734185089Sraj mem_limit >> 16, 2); 735185089Sraj 736185089Sraj /* Disable memory prefetch decode */ 737209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 738185089Sraj 0x10, 2); 739209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 740185089Sraj 0x0, 4); 741209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 742185089Sraj 0xF, 2); 743209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 744185089Sraj 0x0, 4); 745185089Sraj 746209131Sraj secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 747185089Sraj PCIR_SECBUS_1, 1); 748185089Sraj 749185089Sraj /* Configure buses behind the bridge */ 750209131Sraj mv_pcib_init(sc, secbus, PCI_SLOTMAX); 751185089Sraj} 752185089Sraj 753185089Srajstatic int 754209131Srajmv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 755185089Sraj{ 756185089Sraj int slot, func, maxfunc, error; 757185089Sraj uint8_t hdrtype, command, class, subclass; 758185089Sraj 759185089Sraj for (slot = 0; slot <= maxslot; slot++) { 760185089Sraj maxfunc = 0; 761185089Sraj for (func = 0; func <= maxfunc; func++) { 762209131Sraj hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 763185089Sraj func, PCIR_HDRTYPE, 1); 764185089Sraj 765185089Sraj if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 766185089Sraj continue; 767185089Sraj 768185089Sraj if (func == 0 && (hdrtype & PCIM_MFDEV)) 769185089Sraj maxfunc = PCI_FUNCMAX; 770185089Sraj 771209131Sraj command = mv_pcib_read_config(sc->sc_dev, bus, slot, 772185089Sraj func, PCIR_COMMAND, 1); 773185089Sraj command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 774209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, 775185089Sraj PCIR_COMMAND, command, 1); 776185089Sraj 777209131Sraj error = mv_pcib_init_all_bars(sc, bus, slot, func, 778185089Sraj hdrtype); 779185089Sraj 780185089Sraj if (error) 781185089Sraj return (error); 782185089Sraj 783185089Sraj command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 784185089Sraj PCIM_CMD_PORTEN; 785209131Sraj mv_pcib_write_config(sc->sc_dev, bus, slot, func, 786185089Sraj PCIR_COMMAND, command, 1); 787185089Sraj 788185089Sraj /* Handle PCI-PCI bridges */ 789209131Sraj class = mv_pcib_read_config(sc->sc_dev, bus, slot, 790185089Sraj func, PCIR_CLASS, 1); 791209131Sraj subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 792185089Sraj func, PCIR_SUBCLASS, 1); 793185089Sraj 794185089Sraj if (class != PCIC_BRIDGE || 795185089Sraj subclass != PCIS_BRIDGE_PCI) 796185089Sraj continue; 797185089Sraj 798209131Sraj mv_pcib_init_bridge(sc, bus, slot, func); 799185089Sraj } 800185089Sraj } 801185089Sraj 802185089Sraj /* Enable all ABCD interrupts */ 803185089Sraj pcib_write_irq_mask(sc, (0xF << 24)); 804185089Sraj 805185089Sraj return (0); 806185089Sraj} 807185089Sraj 808209131Srajstatic int 809209131Srajmv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 810209131Sraj int func, int hdrtype) 811209131Sraj{ 812209131Sraj int maxbar, bar, i; 813209131Sraj 814209131Sraj maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 815209131Sraj bar = 0; 816209131Sraj 817209131Sraj /* Program the base address registers */ 818209131Sraj while (bar < maxbar) { 819209131Sraj i = mv_pcib_init_bar(sc, bus, slot, func, bar); 820209131Sraj bar += i; 821209131Sraj if (i < 0) { 822209131Sraj device_printf(sc->sc_dev, 823209131Sraj "PCI IO/Memory space exhausted\n"); 824209131Sraj return (ENOMEM); 825209131Sraj } 826209131Sraj } 827209131Sraj 828209131Sraj return (0); 829209131Sraj} 830209131Sraj 831185089Srajstatic struct resource * 832209131Srajmv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 833294883Sjhibbits rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 834185089Sraj{ 835209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 836186932Sraj struct rman *rm = NULL; 837186932Sraj struct resource *res; 838185089Sraj 839186932Sraj switch (type) { 840186932Sraj case SYS_RES_IOPORT: 841209131Sraj rm = &sc->sc_io_rman; 842186932Sraj break; 843186932Sraj case SYS_RES_MEMORY: 844209131Sraj rm = &sc->sc_mem_rman; 845186932Sraj break; 846186932Sraj default: 847240489Sgber return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 848186932Sraj type, rid, start, end, count, flags)); 849186932Sraj }; 850186932Sraj 851240489Sgber if ((start == 0UL) && (end == ~0UL)) { 852240489Sgber start = sc->sc_mem_base; 853240489Sgber end = sc->sc_mem_base + sc->sc_mem_size - 1; 854240489Sgber count = sc->sc_mem_size; 855240489Sgber } 856240489Sgber 857240489Sgber if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 858240489Sgber (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 859240489Sgber return (NULL); 860240489Sgber 861186932Sraj res = rman_reserve_resource(rm, start, end, count, flags, child); 862186932Sraj if (res == NULL) 863186932Sraj return (NULL); 864186932Sraj 865186932Sraj rman_set_rid(res, *rid); 866209131Sraj rman_set_bustag(res, fdtbus_bs_tag); 867186932Sraj rman_set_bushandle(res, start); 868186932Sraj 869186932Sraj if (flags & RF_ACTIVE) 870186932Sraj if (bus_activate_resource(child, type, *rid, res)) { 871186932Sraj rman_release_resource(res); 872186932Sraj return (NULL); 873186932Sraj } 874186932Sraj 875186932Sraj return (res); 876185089Sraj} 877185089Sraj 878185089Srajstatic int 879209131Srajmv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 880185089Sraj struct resource *res) 881185089Sraj{ 882185089Sraj 883186932Sraj if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 884186932Sraj return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 885186932Sraj type, rid, res)); 886186932Sraj 887186932Sraj return (rman_release_resource(res)); 888185089Sraj} 889185089Sraj 890185089Srajstatic int 891209131Srajmv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 892185089Sraj{ 893209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 894185089Sraj 895185089Sraj switch (which) { 896185089Sraj case PCIB_IVAR_BUS: 897185089Sraj *result = sc->sc_busnr; 898185089Sraj return (0); 899185089Sraj case PCIB_IVAR_DOMAIN: 900185089Sraj *result = device_get_unit(dev); 901185089Sraj return (0); 902185089Sraj } 903185089Sraj 904185089Sraj return (ENOENT); 905185089Sraj} 906185089Sraj 907185089Srajstatic int 908209131Srajmv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 909185089Sraj{ 910209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 911185089Sraj 912185089Sraj switch (which) { 913185089Sraj case PCIB_IVAR_BUS: 914185089Sraj sc->sc_busnr = value; 915185089Sraj return (0); 916185089Sraj } 917185089Sraj 918185089Sraj return (ENOENT); 919185089Sraj} 920209131Sraj 921209131Srajstatic inline void 922209131Srajpcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 923209131Sraj{ 924209131Sraj 925294510Sandrew if (sc->sc_type != MV_TYPE_PCI) 926209131Sraj return; 927209131Sraj 928209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 929209131Sraj} 930209131Sraj 931209131Srajstatic void 932209131Srajmv_pcib_hw_cfginit(void) 933209131Sraj{ 934209131Sraj static int opened = 0; 935209131Sraj 936209131Sraj if (opened) 937209131Sraj return; 938209131Sraj 939209131Sraj mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 940209131Sraj opened = 1; 941209131Sraj} 942209131Sraj 943209131Srajstatic uint32_t 944209131Srajmv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 945209131Sraj u_int func, u_int reg, int bytes) 946209131Sraj{ 947209131Sraj uint32_t addr, data, ca, cd; 948209131Sraj 949209131Sraj ca = (sc->sc_type != MV_TYPE_PCI) ? 950209131Sraj PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 951209131Sraj cd = (sc->sc_type != MV_TYPE_PCI) ? 952209131Sraj PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 953209131Sraj addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 954209131Sraj PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 955209131Sraj 956209131Sraj mtx_lock_spin(&pcicfg_mtx); 957209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 958209131Sraj 959209131Sraj data = ~0; 960209131Sraj switch (bytes) { 961209131Sraj case 1: 962209131Sraj data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 963209131Sraj cd + (reg & 3)); 964209131Sraj break; 965209131Sraj case 2: 966209131Sraj data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 967209131Sraj cd + (reg & 2))); 968209131Sraj break; 969209131Sraj case 4: 970209131Sraj data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 971209131Sraj cd)); 972209131Sraj break; 973209131Sraj } 974209131Sraj mtx_unlock_spin(&pcicfg_mtx); 975209131Sraj return (data); 976209131Sraj} 977209131Sraj 978209131Srajstatic void 979209131Srajmv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 980209131Sraj u_int func, u_int reg, uint32_t data, int bytes) 981209131Sraj{ 982209131Sraj uint32_t addr, ca, cd; 983209131Sraj 984209131Sraj ca = (sc->sc_type != MV_TYPE_PCI) ? 985209131Sraj PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 986209131Sraj cd = (sc->sc_type != MV_TYPE_PCI) ? 987209131Sraj PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 988209131Sraj addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 989209131Sraj PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 990209131Sraj 991209131Sraj mtx_lock_spin(&pcicfg_mtx); 992209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 993209131Sraj 994209131Sraj switch (bytes) { 995209131Sraj case 1: 996209131Sraj bus_space_write_1(sc->sc_bst, sc->sc_bsh, 997209131Sraj cd + (reg & 3), data); 998209131Sraj break; 999209131Sraj case 2: 1000209131Sraj bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1001209131Sraj cd + (reg & 2), htole16(data)); 1002209131Sraj break; 1003209131Sraj case 4: 1004209131Sraj bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1005209131Sraj cd, htole32(data)); 1006209131Sraj break; 1007209131Sraj } 1008209131Sraj mtx_unlock_spin(&pcicfg_mtx); 1009209131Sraj} 1010209131Sraj 1011209131Srajstatic int 1012209131Srajmv_pcib_maxslots(device_t dev) 1013209131Sraj{ 1014209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1015209131Sraj 1016209131Sraj return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1017209131Sraj} 1018209131Sraj 1019294430Szbbstatic int 1020294430Szbbmv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) 1021294430Szbb{ 1022294430Szbb#if defined(SOC_MV_ARMADA38X) 1023294430Szbb struct mv_pcib_softc *sc = device_get_softc(dev); 1024294430Szbb uint32_t vendor, device; 1025294430Szbb 1026294430Szbb vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, 1027294430Szbb PCIR_VENDOR_LENGTH); 1028294430Szbb device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, 1029294430Szbb PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; 1030294430Szbb 1031294430Szbb return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); 1032294430Szbb#else 1033294430Szbb /* On platforms other than Armada38x, root link is always at slot 0 */ 1034294430Szbb return (slot == 0); 1035294430Szbb#endif 1036294430Szbb} 1037294430Szbb 1038209131Srajstatic uint32_t 1039209131Srajmv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1040209131Sraj u_int reg, int bytes) 1041209131Sraj{ 1042209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1043209131Sraj 1044240489Sgber /* Return ~0 if link is inactive or trying to read from Root */ 1045240489Sgber if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1046294430Szbb PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1047209131Sraj return (~0U); 1048209131Sraj 1049209131Sraj return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1050209131Sraj} 1051209131Sraj 1052209131Srajstatic void 1053209131Srajmv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1054209131Sraj u_int reg, uint32_t val, int bytes) 1055209131Sraj{ 1056209131Sraj struct mv_pcib_softc *sc = device_get_softc(dev); 1057209131Sraj 1058240489Sgber /* Return if link is inactive or trying to write to Root */ 1059240489Sgber if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1060294430Szbb PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1061209131Sraj return; 1062209131Sraj 1063209131Sraj mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1064209131Sraj} 1065209131Sraj 1066209131Srajstatic int 1067259484Snwhitehornmv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1068209131Sraj{ 1069209131Sraj struct mv_pcib_softc *sc; 1070259484Snwhitehorn struct ofw_pci_register reg; 1071261351Snwhitehorn uint32_t pintr, mintr[4]; 1072261351Snwhitehorn int icells; 1073259484Snwhitehorn phandle_t iparent; 1074209131Sraj 1075259484Snwhitehorn sc = device_get_softc(bus); 1076259484Snwhitehorn pintr = pin; 1077209131Sraj 1078259484Snwhitehorn /* Fabricate imap information in case this isn't an OFW device */ 1079259484Snwhitehorn bzero(®, sizeof(reg)); 1080259484Snwhitehorn reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1081259484Snwhitehorn (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1082259484Snwhitehorn (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1083209131Sraj 1084261351Snwhitehorn icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1085261351Snwhitehorn ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1086261351Snwhitehorn &iparent); 1087261351Snwhitehorn if (icells > 0) 1088261351Snwhitehorn return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1089259484Snwhitehorn 1090259484Snwhitehorn /* Maybe it's a real interrupt, not an intpin */ 1091259484Snwhitehorn if (pin > 4) 1092259484Snwhitehorn return (pin); 1093259484Snwhitehorn 1094259484Snwhitehorn device_printf(bus, "could not route pin %d for device %d.%d\n", 1095209131Sraj pin, pci_get_slot(dev), pci_get_function(dev)); 1096209131Sraj return (PCI_INVALID_IRQ); 1097209131Sraj} 1098209131Sraj 1099209131Srajstatic int 1100209131Srajmv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1101209131Sraj{ 1102260340Sian struct mv_pci_range io_space, mem_space; 1103209131Sraj device_t dev; 1104209131Sraj int error; 1105209131Sraj 1106209131Sraj dev = sc->sc_dev; 1107209131Sraj 1108260340Sian if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1109209131Sraj device_printf(dev, "could not retrieve 'ranges' data\n"); 1110209131Sraj return (error); 1111209131Sraj } 1112209131Sraj 1113209131Sraj /* Configure CPU decoding windows */ 1114240489Sgber error = decode_win_cpu_set(sc->sc_win_target, 1115240489Sgber sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1116209131Sraj if (error < 0) { 1117209131Sraj device_printf(dev, "could not set up CPU decode " 1118209131Sraj "window for PCI IO\n"); 1119209131Sraj return (ENXIO); 1120209131Sraj } 1121240489Sgber error = decode_win_cpu_set(sc->sc_win_target, 1122240489Sgber sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1123240489Sgber mem_space.base_parent); 1124209131Sraj if (error < 0) { 1125209131Sraj device_printf(dev, "could not set up CPU decode " 1126209131Sraj "windows for PCI MEM\n"); 1127209131Sraj return (ENXIO); 1128209131Sraj } 1129209131Sraj 1130209131Sraj sc->sc_io_base = io_space.base_parent; 1131209131Sraj sc->sc_io_size = io_space.len; 1132209131Sraj 1133209131Sraj sc->sc_mem_base = mem_space.base_parent; 1134209131Sraj sc->sc_mem_size = mem_space.len; 1135209131Sraj 1136209131Sraj return (0); 1137209131Sraj} 1138209131Sraj 1139240493Sgber#if defined(SOC_MV_ARMADAXP) 1140240493Sgberstatic int 1141240493Sgbermv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1142240493Sgber uint32_t *data) 1143240493Sgber{ 1144240493Sgber struct mv_pcib_softc *sc; 1145240493Sgber 1146240493Sgber sc = device_get_softc(dev); 1147240493Sgber irq = irq - MSI_IRQ; 1148240493Sgber 1149240493Sgber /* validate parameters */ 1150240493Sgber if (isclr(&sc->sc_msi_bitmap, irq)) { 1151240493Sgber device_printf(dev, "invalid MSI 0x%x\n", irq); 1152240493Sgber return (EINVAL); 1153240493Sgber } 1154240493Sgber 1155240493Sgber mv_msi_data(irq, addr, data); 1156240493Sgber 1157240493Sgber debugf("%s: irq: %d addr: %jx data: %x\n", 1158240493Sgber __func__, irq, *addr, *data); 1159240493Sgber 1160240493Sgber return (0); 1161240493Sgber} 1162240493Sgber 1163240493Sgberstatic int 1164240493Sgbermv_pcib_alloc_msi(device_t dev, device_t child, int count, 1165240493Sgber int maxcount __unused, int *irqs) 1166240493Sgber{ 1167240493Sgber struct mv_pcib_softc *sc; 1168240493Sgber u_int start = 0, i; 1169240493Sgber 1170240493Sgber if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1171240493Sgber return (EINVAL); 1172240493Sgber 1173240493Sgber sc = device_get_softc(dev); 1174240493Sgber mtx_lock(&sc->sc_msi_mtx); 1175240493Sgber 1176240493Sgber for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1177240493Sgber for (i = start; i < start + count; i++) { 1178240493Sgber if (isset(&sc->sc_msi_bitmap, i)) 1179240493Sgber break; 1180240493Sgber } 1181240493Sgber if (i == start + count) 1182240493Sgber break; 1183240493Sgber } 1184240493Sgber 1185240493Sgber if ((start + count) == MSI_IRQ_NUM) { 1186240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1187240493Sgber return (ENXIO); 1188240493Sgber } 1189240493Sgber 1190240493Sgber for (i = start; i < start + count; i++) { 1191240493Sgber setbit(&sc->sc_msi_bitmap, i); 1192275583Szbb *irqs++ = MSI_IRQ + i; 1193240493Sgber } 1194240493Sgber debugf("%s: start: %x count: %x\n", __func__, start, count); 1195240493Sgber 1196240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1197240493Sgber return (0); 1198240493Sgber} 1199240493Sgber 1200240493Sgberstatic int 1201240493Sgbermv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1202240493Sgber{ 1203240493Sgber struct mv_pcib_softc *sc; 1204240493Sgber u_int i; 1205240493Sgber 1206240493Sgber sc = device_get_softc(dev); 1207240493Sgber mtx_lock(&sc->sc_msi_mtx); 1208240493Sgber 1209240493Sgber for (i = 0; i < count; i++) 1210240493Sgber clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1211240493Sgber 1212240493Sgber mtx_unlock(&sc->sc_msi_mtx); 1213240493Sgber return (0); 1214240493Sgber} 1215240493Sgber#endif 1216260340Sian 1217